ATMEL ATF16V8C-7PI High performance e2 pld Datasheet

Features
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Industry Standard Architecture
Emulates Many 20-Pin PALs
Low Cost Easy-to-Use Software Tools
High Speed Electrically Erasable Programmable Logic Devices
5 ns Maximum Pin-to-Pin Delay
Low Power - 100 µA Pin-Controlled Power Down Mode Option
CMOS and TTL Compatible Inputs and Outputs
I/O Pin Keeper Circuits
Advanced Flash Technology
Reprogrammable
100% Tested
High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
High
Performance
E2 PLD
ATF16V8C
Block Diagram
Note:
1. Includes optional PD control pin.
Pin Configurations
Pin Name
Function
CLK
Clock
I
Logic Inputs
I/O
Bidirectional Buffers
OE
Output Enable
VCC
+5V Supply
PD
Power Down
TSSOP Top View
ATF16V8C
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
DIP/SOIC
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
PLCC
Top view
Rev. 0425D/V16FC-D–04/98
Description
The ATF16V8C is a high performance EECMOS Programmable Logic Device that utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down
to 5 ns and a 100 µA pin-controlled power down mode option are offered. All speed ranges are specified over the
full 5V ± 10% range for industrial temperature ranges; 5V
± 5% for commercial range 5-volt devices.
modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
The ATF16V8C can significantly reduce total system
power, thereby enhancing system reliability and reducing
power supply costs. When pin 4 is configured as the
power down control pin , supply current drops to less than
100 µA whenever the pin is high. If the power down feature isn’t required for a particular application, pin 4 may be
used as a logic input. Also, the pin keeper circuits eliminate the need for internal pull-up resistors along with their
attendant power consumption.
The ATF16V8C incorporates a superset of the generic architectures, which allows direct replacement of the 16R8
family and most 20-pin combinatorial PLDs. Eight outputs
are each allocated eight product terms. Three different
Absolute Maximum Ratings*
Temperature Under Bias................... -40°C to +85°C
Storage Temperature...................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground......................... -2.0V to +7.0V (1)
Voltage on Input Pins
with Respect to Ground
During Programming.................... -2.0V to +14.0V (1)
Programming Voltage with
Respect to Ground....................... -2.0V to +14.0V (1)
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note:
1. Minimum voltage is -0.6V dc, which may undershoot to 2.0V for pulses of less than 20 ns. Maximum output pin
voltage is Vcc + 0.75V dc, which may overshoot to 7.0V
for pulses of less than 20 ns.
DC and AC Operating Conditions
Operating Temperature (Case)
VCC Power Supply
2
ATF16V8C
Commercial
Industrial
0°C - 70°C
-40°C - 85°C
5V ± 5%
5V ± 10%
ATF16V8C
DC Characteristics
Symbol Parameter
Max
Units
0 ≤ VIN ≤ VIL(MAX)
-10
µA
Input or I/O High
Leakage Current
3.5 ≤ VIN ≤ VCC
10
µA
ICC1 (1)
Power Supply Current,
Standby
15 MHz, VCC = MAX,
VIN = 0, VCC, Outputs
Open
Com.
115
mA
Ind.
130
mA
IPD
Power Supply Current,
Power Down Mode
VCC = MAX,
VIN = 0, VCC
Com.
10
100
µA
Ind.
10
105
µA
IOS
Output Short Circuit
Current
VOUT = 0.5V;
VCC= 5V; TA = 25°C
-150
mA
VIL
Input Low Voltage
MIN < VCC < MAX
-0.5
0.8
V
VIH
Input High Voltage
2.0
VCC + 1
V
VOL
Output Low Voltage
VCC = MIN; All Outputs
Com., Ind.
IOL = 24 mA
0.5
V
VOH
Output High Voltage
VCC = MIN
IOL = -4.0 mA
IOL
Output Low Current
VCC = MIN
IOH
Output High Current
V CC = MIN
IIL
Input or I/O Low
Leakage Current
IIH
Note:
Condition
Min
Typ
2.4
V
Com.
24
mA
Ind.
12
mA
Com., Ind.
-4
mA
1. All ICC parameters measured with outputs open.
AC Waveforms (1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
3
AC Characteristics
-5
Symbol Parameter
-7
Min
Max
Min
Max
Units
1
5
3
7.5
ns
3
ns
5
ns
tPD
Input or Feedback to Non-Registered
Output
tCF
Clock to Feedback
tCO
Clock to Output
1
tS
Input or Feedback Setup Time
3
5
ns
tH
Input Hold Time
0
0
ns
tP
Clock Period
6
8
ns
tW
Clock Width
3
4
ns
FMAX
3
4
2
External Feedback 1/(tS+ tCO)
142
100
MHz
Internal Feedback 1/(tS + tCF)
166
125
MHz
No Feedback 1/(tP)
166
125
MHz
tEA
Input to Output Enable —
Product Term
2
6
3
9
ns
tER
Input to Output Disable —
Product Term
2
5
2
9
ns
tPZX
OE pin to Output Enable
2
5
2
6
ns
tPXZ
OE pin to Output Disable
1.5
5
1.5
6
ns
Max
Units
Power Down AC Characteristics (1, 2, 3)
-5
Symbol Parameter
Min
Min
7.5
ns
tGVDH Valid OE Before PD High
0
0
ns
tCVDH Valid Clock Before PD High
0
0
ns
tDHIX
Input Don’t Care After PD High
5
7.5
ns
tDHGX OE Don’t Care After PD High
5
7.5
ns
tDHCX Clock Don’t Care After PD High
5
7.5
ns
tDLIV
PD Low to Valid Input
5
7.5
ns
tDLGV
PD Low to Valid OE
15
20
ns
tDLCV
PD Low to Valid Clock
15
20
ns
tDLOV
PD Low to Valid Output
20
25
ns
Notes: 1. Output data is latched and held.
2. HI-Z outputs remain HI-Z.
4
Max
5
tIVDH
Valid Input Before PD High
-7
ATF16V8C
3. Clock and input transitions are ignored.
ATF16V8C
Input Test Waveforms and
Measurement Levels:
Output Test Loads:
Commercial
tR, tF < 1.5ns (10% to 90%)
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
Units
CIN
5
8
pF
VIN = 0V
COUT
6
8
pF
VOUT = 0V
Note:
Conditions
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The ATF16V8C’s registers are designed to reset during
power up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be high on powerup.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required:
1) The VCC rise must be monotonic, from below .7 volts,
2) After reset occurs, all input and feedback setup times
must be met before driving the clock term high, and
3) The signals from which the clock is derived must remain stable during tPR.
Parameter Description
Typ
Max
Units
tPR
Power-Up
Reset Time
600
1,000
ns
VRST
Power-Up
Reset
Voltage
3.8
4.5
V
5
Power Down Mode
The ATF16V8C includes an optional pin controlled power
down feature. Device pin 4 may be configured as the
power down pin. When this feature is enabled and the
power down pin is high, total current consumption drops to
less than 100 µA. In the power down mode, all output data
and internal logic states are latched and held. All registered and combinatorial output data remains valid. Any
outputs which were in a HI-Z state at the onset of power
down will remain at HI-Z. During power down, all input signals except the power down pin are blocked. The input
and I/O pin keeper circuits remain active to insure that
pins do not float to indeterminate levels. This helps to further reduce system power.
Selection of the power down option is specified in the
ATF16V8C logic design file. The logic compiler will include
this option selection in the otherwise standard 16V8
JEDEC fuse file. When the power down feature is not
specified in the design file, pin 4 is available as a logic
input, and there is no power down pin. This allows the
ATF16V8C to be programmed using any existing standard 16V8 fuse file.
Note: Some programmers list the JEDEC-compatible
16V8C (No PD used) separately from the non-JEDEC
compatible 16V8CEXT. (EXT for extended features.)
Registered Output Preload
Security Fuse Usage
The ATF16V8C’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by approved programmers.
A single fuse is provided to prevent unauthorized copying
of the ATF16V8C fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse will be programmed last, as its effect is
immediate.
Input and I/O Pin Keeper Circuits
The ATF16V8C contains internal input and I/O pin keeper
circuits. These circuits allow each ATF16V8C pin to hold
its previous value even when it is not being driven by an
external source or by the device’s output buffer. This helps
insure that all logic array inputs are at known, valid logic
levels. This reduces system power by preventing pins
from floating to indeterminate levels. By using pin keeper
circuits rather than pull-up resistors, there is no DC current
required to hold the pins in either logic state (high or low).
Input Diagram
I/O Diagram
6
ATF16V8C
These pin keeper circuits are implemented as weak feedback inverters, as shown in the Input Diagram below.
These keeper circuits can easily be overdriven by standard TTL- or CMOS-compatible drivers. The typical overdrive current required is 40 µA.
ATF16V8C
Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the
ATF16V8C architecture. Eight configurable macrocells
can be configured as a registered output, combinatorial
I/O, combinatorial output, or dedicated input.
The ATF16V8C can be configured in one of three different
modes. Each mode makes the ATF16V8C look like a different device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The determining factors would be the usage of register versus
combinatorial outputs and dedicated outputs versus outputs with output enable control.
The ATF16V8C universal architecture can be programmed to emulate many 20-pin PAL devices. These ar-
chitectural subsets can be found in each of the configuration modes described in the following pages. The user can
download the listed subset device JEDEC programming
file to the PLD programmer, and the ATF16V8C can be
configured to act like the chosen device. Check with your
programmer manufacturer for this capability.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security
Fuse, when programmed, protects the content of the
ATF16V8C. Eight bytes (64 fuses) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision, or date. The User Signature
is accessible regardless of the state of the Security Fuse.
Compiler Mode Selection
Registered
ABEL, Atmel-ABEL
with PD ENABLE
Complex
P16V8R
P16V8PDR
Simple
P16V8C
(1)
P16V8PDC
Auto Select
P16V8AS
(1)
P16V8PD
P16V8
(1)
P16V8PDS (1)
G16V8MS
G16V8MA
G16V8AS
G16V8A
G16V8CPMS
G16V8CPMA
G16V8CPAS
G16V8CP
LOG/iC
GAL16V8_R (2)
GAL16V8_C7 (2)
GAL16V8_C8 (2)
GAL16V8
OrCAD-PLD
“Registered”
“Complex”
“Simple”
GAL16V8A
PLDesigner
P16V8R
P16V8C
P16V8C
P16V8A
Synario/Atmel-Synario
NA
NA
NA
ATF16V8C ALL
NA
NA
NA
ATF16V8C (PD) ALL (1)
G16V8R
G16V8C
G16V8AS
G16V8
CUPL, Atmel-CUPL
with PD ENABLE
with PD ENABLE
Tango-PLD
Notes: 1. Please call Atmel PLD Hotline at (408) 436-4333 for more information.
2. Only applicable for version 3.4 or lower.
7
Macrocell Configuration
Software compilers support the three different OMC
modes as different device types. These device types are
listed in the table below. Most compilers have the ability to
automatically select the device type, generally based on
the register usage and output enable (OE) usage. Register usage on the device forces the software to choose the
registered mode. All combinatorial outputs with OE controlled by the product term will force the software to
choose the complex mode. The software will choose the
simple mode only when all outputs are dedicated combinatorial without OE control. The different device types
listed in the table can be used to override the automatic
device selection by the software. For further details, refer
to the compiler software manuals.
In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These
pins cannot be configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19
and pin 12 do not have the feedback option in this mode.
In simple mode all feedback paths of the output pins are
routed via the adjacent pins. In doing so, the two inner
most pins (pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated
combinatorial output.
When using compiler software to configure the device, the
user must pay special attention to the following restrictions
in each mode.
ATF16V8C Registered Mode
PAL Device Emulation / PAL Replacement
The registered mode is used if one or more registers are
required. Each macrocell can be configured as either a
registered or combinatorial output or I/O, or as an input.
For a registered output or I/O, the output is enabled by the
OE pin, and the register is clocked by the CLK pin. Eight
product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a
product term, and seven product terms are allocated to the
sum term. When the macrocell is configured as an input,
the output enable is permanently disabled.
Any register usage will make the compiler select this
mode. The following registered devices can be emulated
using this mode:
16R8
16RP8
16R6
16RP6
16R4
16RP4
Registered Configuration
for Registered Mode (1, 2)
Combinatorial Configuration for
Registered Mode (1, 2)
Notes:
1. Pin 1 controls common CLK for the registered outputs.
Pin 11 controls common OE for the registered outputs.
Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture
control bits and checks for proper pin usage automatically.
Notes:
1. Pin 1 and Pin 11 are permanently configured as CLK and
OE.
2. The development software configures all the architecture
control bits and checks for proper pin usage automatically.
8
ATF16V8C
ATF16V8C
Registered Mode Logic Diagram
*
* Input not available if power down mode is enabled.
9
ATF16V8C Complex Mode
PAL Device Emulation/PAL Replacement
In the Complex Mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the
array. Pins 13 through 18 have pin feedback paths back to
the AND-array, which makes full I/O capability possible.
Pins 12 and 19 (outermost macrocells) are outputs only.
They do not have input capability. In this mode, each
macrocell has seven product terms going to the sum term
and one product term enabling the output.
Combinatorial applications with an OE requirement will
make the compiler select this mode. The following devices
can be emulated using this mode:
16L8
16H8
16P8
Complex Mode Option
ATF16V8C Simple Mode
PAL Device Emulation / PAL Replacement
In the Simple Mode, 8 product terms are allocated to the
sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinatorial outputs. Other macrocells can be either inputs or combinatorial outputs with pin
feedback to the AND-array. Pins 1 and 11 are regular inputs.
The compiler selects this mode when all outputs are combinatorial without OE control. The following simple PALs
can be emulated using this mode:
10L8
10H8
10P8
12L6
12H6
12P6
14L4
14H4
14P4
16L2
16H2
16P2
Simple Mode Option
VCC
0
1
0
7
XOR
Pins 15 and 16 do not have this feedback path.
* - Pins 15 and 16 are always enabled.
10
ATF16V8C
S1*
ATF16V8C
Complex Mode Logic Diagram
*
* Input not available if power down mode is enabled.
11
Simple Mode Logic Diagram
*
* Input not available if power down mode is enabled.
12
ATF16V8C
ATF16V8C
13
14
ATF16V8C
ATF16V8C
15
Ordering Information
tPD
(ns)
tS
(ns)
tCO
(ns)
Ordering Code
Package
5
3
4
ATF16V8C-5JC
20J
Commercial
(0°C to 70°C)
7.5
5
5
ATF16V8C-7JC
ATF16V8C-7PC
ATF16V8C-7SC
ATF16V8C-7XC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
ATF16V8C-7JI
ATF16V8C-7PI
ATF16V8C-7SI
ATF16V8C-7XI
20J
20P3
20S
20X
Industrial
(-40°C to 85°C)
Package Type
16
20J
20-Lead, Plastic J-Leaded Chip Carrier (PLCC)
20P3
20-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S
20-Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
20X
20-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
ATF16V8C
Operation Range
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