ATMEL AT24MAC602-X11M-T I2c-compatible (2-wire) 2-kbit serial eeprom Datasheet

Atmel AT24MAC402 and AT24MAC602
I2C-Compatible (2-wire) 2-Kbit Serial EEPROM with a
Factory-Programmed EUI-48™ or EUI-64™Address
Plus an Embedded Unique 128-bit Serial Number
2-Kbit (256 x 8)
PRELIMINARY DATASHEET
Standard Serial EEPROM Features
 Low-voltage operation

1.7V Minimum (VCC = 1.7V to 5.5V)
 Internally organized as 256 x 8 (2K)
 I2C-compatible (2-wire) serial interface
 Schmitt Trigger, filtered inputs for noise suppression
 Bi-directional data transfer protocol
 400kHz (1.7V) and 1MHz (2.5V, 5.0V) compatibility
 Write Protect pin for hardware data protection of the entire array
 Permanent and Reversible Software Write Protection for the first-half of the array

Software procedure to verify write protect status
 16-byte page write modes

Partial page writes allowed
 Self-timed write cycle (5ms max)
 High-reliability


Endurance: 1,000,000 write cycles
Data retention: 100 years
 Green package options (PB/Halide-free/RoHS compliant)

8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, and 5-lead SOT23
 Die sale options: wafer form and tape and reel
Enhanced Features in the MAC Serial EEPROM Family
 Factory-programmed EUI-48 or EUI-64 compatible address
Permanently locked, read-only value
Stored in a separate memory area
 Guaranteed unique EUI address


 Custom programming services available

Manage and program customer’s IEEE assigned OUI
 Unique factory-programmed 128-bit serial number
Unique for all Atmel® AT24CS, AT93CS, and AT25S series Serial EEPROMs
Permanently locked, read-only value
 Stored in a separate memory area


8807A–SEEPR–6/12
Description
The Atmel AT24MAC402 and AT24MAC602 provides 2048 bits of Serial Electrically-Erasable Programmable Read-Only
Memory (EEPROM) organized as 256 words of eight bits each and is accessed via an I2C-compatible (2-wire) serial
interface. In addition, AT24MAC402/602 incorporates an easy and inexpensive method to obtain a globally unique MAC
or EUI address (EUI-48 or EUI-64). AT24MAC402 is an EUI-48 compatible device that contains a 48-bit EUI address,
and AT24MAC602 is an EUI-64 compatible device that contains a 64-bit EUI address.
The EUI-48 and EUI-64 addresses can be assigned as the actual physical address of a system hardware device or node
or it can be assigned to a software instance. These addresses are factory programmed by Atmel and permanently write
protected in an extended memory block located outside of the standard 2-Kbit bit memory array.
In addition, the AT24MAC402/602 provides the value added feature of a factory-programmed, guaranteed unique 128-bit
serial number located in the extended memory block (same area as the EUI address values). The serial number is Atmel
factory-programmed and permanently write protected. This 128-bit serial number is compatible with all AT24CS,
AT93CS, and AT25S family serial numbers, therefore, providing guaranteed unique serial numbers for any application
that is also using Atmel Serial EEPROMs.
The first-half of the AT24MAC402/602 incorporates a permanent and a reversible software write protection feature while
a hardware write protect feature for the entire array is available via an external pin. The permanent software write
protection is enabled by sending a special command to the device. This protection cannot be reversed once executed.
However, the reversible software write protection can be reversed by sending and executing a special command. The
hardware write protection is controlled by the WP pin state and can be used to protect the entire array regardless of
whether or not the software write protection has been enabled. The software and hardware write protection features
allow the user the flexibility to protect no portion of the memory, the first-half of the memory, or the entire memory array
depending on the specific needs of the application.
The device is optimized for use in many industrial and commercial applications where low-power and low-voltage
operations are essential. The AT24MAC402/602 is available in space saving 8-lead JEDEC SOIC, 8-lead TSSOP,
8-pad UDFN, and 5-lead SOT23 packages. Both devices operate across a wide supply voltage range from
1.7V to 5.5V VCC.
Figure 1.
Pin Configurations
Pin Name
Function
A0 - A2
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
GND
Ground
VCC
Power Supply
8-lead TSSOP
8-lead SOIC
A0
1
8
VCC
A0
1
8
VCC
A1
2
7
WP
A1
2
7
WP
A2
3
6
SCL
A2
3
6
SCL
SDA
GND
4
5
SDA
GND
4
5
8-pad UDFN
VCC 8
1
A0
WP 7
2
A1
SCL 6
3
A2
SDA 5
4
GND
5-lead SOT23
SCL
1
GND
2
SDA
3
5
WP
4
VCC
Bottom View
Note:
For use of the 5-lead SOT23, the software A2, A1, and A0 bits in the device address word must be set to zero to
properly communicate with the device since the A2, A1, and A0 pins are not bonded out. Some functionality is
not possible due to these pins not being available. See “Write Protection” on page 11 for more details.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
2
Absolute Maximum Ratings*
Operating temperature . . . . . . . . . . .–55°C to +125°C
Storage temperature . . . . . . . . . . . . .–65°C to +150°C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . –1.0V to +7.0V
Maximum operating voltage . . . . . . . . . . . . . . . 6.25V
DC output current . . . . . . . . . . . . . . . . . . . . . . . 5.0mA
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Figure 1-1. Block Diagram
VCC
GND
WP
Start
Stop
Logic
SCL
SDA
Serial
Control
Logic
Device
Address
Comparator
Data Latches
Load
COMP
INC
Data Word
ADDR/Counter
Read/Write
A2
A1
A0
Read
Read
High Voltage
Pump & Timing
Enable
128-bit
Serial
Number
MAC-48
EUI-48
EUI-64
Address
Row Decoder
1.
EEPROM
Array
Column
Decoder
Serial MUX
DOUT / ACK
Logic
DOUT
DIN
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
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2.
Pin Description
Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open collector devices.
Device Addresses (A0, A1, A2): The A0, A1, and A2 pins are device address inputs that are hard wired for the
AT24MAC402/602. As many as eight 2K devices may be addressed on a single bus system. Device addressing is
discussed in detail under “Device Addressing” on page 10.
Write Protect (WP): The AT24MAC402/602 has a Write Protect pin that provides hardware data protection. When the
Write Protect pin is connected to ground (GND), normal Read/Write operations to the full array are possible. When the
Write Protect pin is connected to VCC, all write operations to the memory are inhibited, but read operations are still
possible. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always
connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. The
write protection operation is summarized in Table 2-1 below.
Table 2-1.
Atmel AT24MAC402/602 Write Protection Modes
WP Pin Status
Permanent Write Protect
Register
Reversible Write Protect
Register
Part of the Array Write
Protected
VCC
—
—
Full Array (2K)
GND or Floating
Not Programmed
Not Programmed
Normal Read/Write
GND or Floating
Programmed
—
First-half of Array
GND or Floating
—
Programmed
First-half of Array
Table 2-2.
Pin Capacitance(1)
Symbol
Test Condition
CI/O
CIN
Note:
1.
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
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Table 2-3.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted)
Symbol
Parameter
Max
Units
VCC
Supply Voltage
5.5
V
ICC1
Supply Current VCC = 5.0V
Read at 400kHz
0.4
1.0
mA
ICC2
Supply Current VCC = 5.0V
Write at 400kHz
2.0
3.0
mA
ISB1
Standby Current VCC = 1.7V
VIN = VCC or VSS
1.0
μA
ISB2
Standby Current VCC = 2.5V
VIN = VCC or VSS
2.0
μA
ISB3
Standby Current VCC = 5.5V
VIN = VCC or VSS, A0 = VSS
6.0
μA
ILI
Input Leakage Current
VIN = VCC or VSS
0.10
3.0
μA
ILO
Output Leakage Current
VOUT = VCC or VSS
0.05
3.0
μA
VIL
Input Low Level(1)
–0.6
VCC x 0.3
V
VIH
Input High Level(1)
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low Level VCC = 1.7V
IOL = 0.15mA
0.2
V
VOL2
Output Low Level VCC = 3.0V
IOL = 2.1mA
0.4
V
Note:
1.
Test Condition
Min
Typ
1.7
VIL min and VIH max are reference only and are not tested.
Table 2-4.
AC Characteristics
1.7V
Symbol
Parameter
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
1.2
0.4
μs
tHIGH
Clock Pulse Width High
0.6
0.4
μs
tI
Noise Suppression Time(1)
tAA
Clock Low to Data Out Valid
0.1
tBUF
Time the bus must be free before a new
transmission can start(1)
1.3
0.5
μs
tHD.STA
Start Hold Time
0.6
0.25
μs
tSU.STA
Start Set-up Time
0.6
0.25
μs
tHD.DAT
Data In Hold Time
0
0
μs
tSU.DAT
Data In Set-up Time
100
100
ns
tR
Min
2.5V, 5.0V
Inputs Rise Time
Max
Min
400
100
(1)
(1)
0.9
0.05
Max
Units
1000
kHz
50
ns
0.55
μs
0.3
0.3
μs
300
100
ns
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
0.6
0.25
μs
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
(1)
Endurance
Note:
1.
5
25°C, Page Mode, 3.3V
1,000,000
5
ms
Write cycles
This parameter is characterized and is not 100% tested.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
5
3.
Memory Organization
Atmel AT24MAC402/602, 2K Serial EEPROM: The 2-Kbit memory array is internally organized as 16 pages of 16 bytes
of EEPROM each. Random word addressing requires a 8-bit data word address.
EUI Address and Serial Number: The 48-bit EUI address in the AT24MAC402 and the 64-bit EUI address in the
AT24MAC602 are located in the extended memory block. In addition, the serial number data is also located in the
extended memory block as shown below in Figure 3-1. These EUI-48 or EUI-64 addresses are stored in a dedicated
read-only EEPROM memory block located outside the standard 2K memory array as shown below. This means the full
standard 2-Kbit EEPROM array is available for use as opposed to solutions where only half of the EEPROM memory
array is available for application usage.
Figure 3-1. Memory Organization
Permanent or
Reversible Software
Write Protection
Capable
First-half
Standard
2-Kbit
EEPROM
Device Address
‘1010’
Extended
Memory
Device Address
‘1011’
Address Range (00h-7Fh)
or
Full Array Hardware
Write Protection
Capable
Address Range (80h-FFh)
Full Array Hardware
Write Protection
Capable
128-bit Serial Number
Read-only
Second-half
Address Range (80h-8Fh)
EUI-48/64 Value
EUI-48 Address Range (9Ah-9Fh)
EUI-64 Address Range (98h-9Fh)
Read-only
The EUI-48 and EUI-64 address fields contain either six or eight bytes respectively. The first three bytes of the EUI
read-only address field are called the Organizationally Unique Identifier (OUI) and the IEEE Registration Authority has
assigned FCC23Dh as the Atmel, OUI.
Following the OUI, the remaining bytes are called the Extension Identifier and will be either three bytes or five bytes
depending on if it is an EUI-48 address (AT24MAC402) or EUI-64 address (AT24MAC602). Atmel generates this unique
24-bit/40-bit data value along with the OUI to guarantee a globally unique EUI address value and programs it at the
factory before permanently locking the extended memory region.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
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3.1
EUI-48 Support
The EUI-48 address is stored in the last six bytes of the AT24MAC402’s extended memory block as shown in Table 3-1.
For information on the protocol to read the EUI-48 value, see “Device Addressing” on page 10 and “Read Operations” on
page 15.
Table 3-1.
48-Bit EUI Address Memory Map Example
48-Bit EUI
Description
24-Bit OUI
24-Bit Extension Identifier
Memory Address
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
EUI Data Value
FCh
C2h
3Dh
Byte 1
Byte 2
Byte 3
Using an EUI-48 Value in an EUI-64 Application: An EUI-64 compatible value can be generated from the EUI-48 value
contained in the AT24MAC402 by concatenating the 24-bit OUI, an FFFEh data value, and the 24-bit Extension
Identifier. This is commonly referred to as an Encapsulated EUI-48 value. However, Atmel recommends using the
AT24MAC602 which contains a true EUI-64 value so that post read processing is not required by the application.
3.2
EUI-64 Support
For applications that utilize an EUI-64 standard, the EUI-64 address is stored in the last eight bytes of the
AT24MAC602’s extended memory block. Similar to EUI-48, the EUI-64 standard consists of the same three byte OUI
coupled with a five byte extension identifier (see Table 3-2). Atmel generates this unique 40-bit data value coupled with
the OUI to guarantee a globally unique 64-bit EUI value and requires no additional data manipulation like other solutions
where the application must manually insert a two byte FFFEh value in between the OUI and Extension Identifier. For
information on how to read the EUI read protocol, see “Device Addressing” on page 10 and “Read Operations” on page
15.
Table 3-2.
64-Bit EUI Address Memory Map Example
64-Bit EUI
Description
40-Bit Extension Identifier
Memory Address
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
EUI Data Value
FCh
C2h
3Dh
Byte 1(1)
Byte 2(1)
Byte 3
Byte 4
Byte 5
Note:
3.3
24-Bit OUI
1.
The data values FFFEh and FFFFh are prohibited beginning from the 40-bit Extension Identifier in Byte 1
and Byte 2. These values are reserved for denoting an encapsulated MAC-48 or EUI-48 value for use in an
EUI-64 environment.
Non-Atmel OUI Programming Option
For customers with their own IEEE-assigned OUI or Company ID, Atmel offers the time saving option to manage and
deliver custom AT24MAC402/602 devices with their EUI-48/64 values uniquely pre-programmed at delivery. Contact
your local Atmel Sales Office for additional information.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
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4.
Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external component such as a pull-up resistor.
Data on the SDA pin may change only during SCL low time periods (see Figure 4-4 on page 9). Data changes during
SCL high periods will indicate a Start or Stop condition as defined below.
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition which must precede any other
command (see Figure 4-5 on page 9).
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 4-5 on page 9).
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
Standby Mode: The AT24MAC402/602 features a low-power standby mode which is enabled upon

Power-up or

After the receipt of the Stop bit and the completion of any internal operations.
2-Wire Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by
following these steps:
1.
Create a start bit condition.
2.
Clock nine cycles.
3.
Create another start bit followed by Stop bit condition as shown below.
Figure 4-1. Software Reset
Dummy Clock Cycles
SCL
1
Start
Bit
2
3
8
9
Start
Bit
Stop
Bit
SDA
Figure 4-2. Bus Timing
SCL Serial Clock, SDA: Serial Data I/O
SCL
SDA IN
SDA OUT
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
8
Figure 4-3. Write Cycle Timing
SCL Serial Clock, SDA: Serial Data I/O
SCL
8th bit
SDA
ACK
WordN
t
WR
Stop
Condition
Note:
1.
(1)
Start
Condition
The write cycle time tWR is the time from a valid Stop condition of a write sequence to the end of
the internal clear/write cycle.
Figure 4-4. Data Validity
SDA
SCL
Data Stable
Data Stable
Data
Change
Figure 4-5. Start and Stop Condition
SDA
SCL
Start
Stop
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
9
Figure 4-6. Output Acknowledge
1
SCL
8
9
Data IN
Data OUT
Start
5.
Acknowledge
Device Addressing
Standard EEPROM Access: The 2K EEPROM requires an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Table 8-1 on page 16).
The device address word consists of a mandatory one-zero sequence for the first four most-significant bits ‘1010’(Ah)
for normal read and write operations and ‘0110’ (6h) for writing to the Software Write Protect Register.
The next three bits in the protocol sequence are the A2, A1, and A0 device address bits. These three bits must match
their corresponding hard-wired input pins A2, A1, and A0 in order for the part to acknowledge.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high,
and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero.
If a compare is not made, the device will return to a standby state. The device will not acknowledge if the Write Protect
Register has been programmed and the control code is ‘0110’(6h).
Serial Number Access: The AT24MAC402/602 incorporates an extended memory block containing a
factory-programmed 128-bit serial number. Access to this memory location is obtained by beginning the device address
word with a ‘1011’(Bh) sequence. The behavior of the next three bits (A2, A1, and A0) remain the same as during a
standard memory addressing sequence.
The eighth bit of the device address needs to be set to a one to read the serial number. A zero in this bit position, other
than during a dummy write sequence to set the address pointer, will result in a unknown condition and behavior. Writing
or altering the 128-bit serial number is not possible as it is permanently write protected. Further specific protocol is
needed to address the serial number feature of the part. For more details on accessing this special feature, See “Read
Operations” on page 15.
EUI Address Access: The AT24MAC402/602 utilizes an extended memory block containing a factory-programmed
read-only EUI-48 or EUI-64 address respectively. Access to this memory block is obtained by beginning the device
address word with a ‘1011’ (Bh) sequence. The behavior of the next three bits (A2, A1, and A0) remain the same as
during a standard memory addressing sequence.
The eighth bit of the device address needs to be set to a one to read the EUI address. A zero in this bit position, other
than during a dummy write sequence to set the address pointer, will result in a unknown condition and behavior.
Attempting to write or alter the EUI address is not possible as it is permanently write protected. Further specific protocol
is needed to address this feature of the part. For more details on accessing this special feature, see “Read Operations”
on page 15.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
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Table 5-1.
Device Address
Access Area
6.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EEPROM
1
0
1
0
A2
A1
A0
R/W
EUI or Serial Number Read
1
0
1
1
A2
A1
A0
1
Write Operations
Byte Write: A Byte Write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again acknowledge or respond with a zero and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the
addressing device, such as a microcontroller, must terminate the write sequence with a Stop condition. At this time, the
EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write
cycle and the EEPROM will not respond until the write is complete (see Figure 8-1 on page 16). The device will
acknowledge a write command, but not write the data if the software or hardware write protection has been enabled. The
write cycle time must be observed even when the write protection is enabled.
Page Write: The AT24MAC402/602 is capable of a 16-byte Page Write. A Page Write is initiated by the same method as
a Byte Write, but the microcontroller does not send a Stop condition after the first data word is clocked in. Instead, after
the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words.
The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write
sequence with a Stop condition (see Figure 8-2 on page 17).
The lower four data word address bits are internally incremented following the receipt of each data word. The higher data
word address bits are not incremented, retaining the memory page row location. When the internally generated word
address reaches the page boundary, the next byte is placed at the beginning of the same page. If more than sixteen data
words are transmitted to the EEPROM, the data word address will roll-over and previous data will be overwritten. The
address roll-over during write is from the last byte of the current page to the first byte of the same page. The device will
acknowledge a write command, but will not write the data if the software or hardware write protection has been enabled.
The write cycle time must be observed even when the write protection is enabled.
Acknowledge Polling: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero allowing the read or write sequence to continue.
7.
Write Protection
Once enabled, the Software Write Protection write protects only the first-half of the array (00h - 7Fh) while the hardware
write protection, via the WP pin, is used to protect the entire array (see Table 7-1 on page 13).
Permanent Software Write Protection (PSWP): The Permanent Software Write Protection is enabled by sending a
command to the device, similar to a normal write command, which programs the Permanent Write Protect Register. This
must be done with the WP pin low. The Write Protect Register is programmed by sending a write command with the
device address of ‘0110’(6h) instead of ‘1010’ (Ah) with the address and data bit(s) being don’t cares (see Figure 7-1
on page 12). The write cycle time must be observed. Once the permanent software write protection has been enabled,
the device will no longer acknowledge the ‘0110’ (6h) control byte and cannot be reversed even if the device is
powered down. The Permanent Software Write Protection can only be invoked on a SOT23 packaged device with the
A2, A1, and A0 bits set to zero.
Reversible Software Write Protection (RSWP): The Reversible Software Write Protection is enabled by sending a
command to the device, similar to a normal write command, which programs the Reversible Write Protect Register. This
must be done with the WP pin low. The Reversible Write Protect Register is programmed by sending a write command
‘01100010’(62h) with pins A2 and A1 tied to ground or not connected and the A0 pin connected to VHV (see Figure 7-2
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
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on page 12 and Table 7-2 on page 13). The Reversible Write Protection Register or Write Protection can be reversed by
sending a command ‘01100110’(66h) with the A2 pin tied to ground or no connect, the A1 pin tied to VCC and the A0 pin
tied to VHV (see Figure 7-3 on page 12 and Table 7-2 on page 13). Due to the unavailability of the A2, A1, and A0 pins, the
Reversible Software Write Protection function is not available on the SOT23 package.
Hardware Write Protection: The WP pin can be connected to VCC, GND, or left floating. Connecting the WP pin to VCC
will write protect the entire array regardless of whether or not the Software Write Protection has been enabled or invoked
(see Table 7-3 on page 13 and Table 7-4 on page 14). The Software Write Protection Register cannot be programmed
when the WP pin is connected to VCC. If the WP pin is connected to GND or left floating, the write protection mode is
determined by the status of the Software Write Protect Register.
Figure 7-1. Setting Permanent Write Protect Register (PSWP)
S
T
A
R
T
SDA LINE
Control Byte
Word Address
S
T
O
P
Data
0 1 1 0 A2 A1 A0 0
A
C
K
A
C
K
A
C
K
= Don’t Care
Figure 7-2. Setting Reversible Write Protect Register (RSWP)
S
T
A
R
T
SDA LINE
Control Byte
Word Address
S
T
O
P
Data
0 1 1 0 0 0 1 0
A
C
K
A
C
K
A
C
K
= Don’t Care
Figure 7-3. Clearing Reversible Write Protect Register (RSWP)
S
T
A
R
T
SDA LINE
Control Byte
Word Address
S
T
O
P
Data
0 1 1 0 0 1 1 0
A
C
K
A
C
K
A
C
K
= Don’t Care
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
12
Table 7-1.
Write Protection
Pin
Preamble
R/W
Command
A2
A1
A0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Set PSWP
A2
A1
A0
0
1
1
0
A2
A1
A0
0
Set RSWP
0
0
VHV
0
1
1
0
0
0
1
0
Clear RSWP
0
VCC
VHV
0
1
1
0
0
1
1
0
Table 7-2.
VHV
VHV
Note:
Min
Max
Units
7
10
V
VHV – VCC > 4.8V
Table 7-3.
WP Connected to GND or Floating
WP Connected to GND or Floating
Command
R/W
Bit
Permanent
Write Protect
Register PSWP
Reversible
Write Protect
Register
RSWP
Response
from
Device
1010
R
X
X
ACK
Read Array.
1010
W
Programmed
X
ACK
Can write to second-half (80h - FFh) only.
1010
W
X
Programmed
ACK
Can write to second-half (80h - FFh) only.
1010
W
Not Programmed
Not Programmed
ACK
Can write to full array.
Read PSWP
R
Programmed
X
No ACK
STOP – Indicates Permanent Write Protect Register is
programmed.
Read PSWP
R
Not Programmed
X
ACK
Data read out is undefined. Indicates PSWP Register is
not programmed.
Set PSWP
W
Programmed
X
No ACK
STOP – Indicates Permanent Write Protect Register is
programmed.
Set PSWP
W
Not Programmed
X
ACK
Read RSWP
R
X
Programmed
No ACK
STOP – Indicates Reversible Write Protect Register is
programmed.
Read RSWP
R
X
Not Programmed
ACK
Data read out is undefined. Indicates RSWP Register is
not programmed.
Set RSWP
W
X
Programmed
No ACK
STOP – Indicates Reversible Write Protect Register is
programmed.
Set RSWP
W
X
Not Programmed
ACK
Program Reversible Write Protect Register (reversible).
Clear RSWP
W
Programmed
X
No ACK
STOP – Indicates Permanent Write Protect Register is
programmed.
Clear RSWP
W
Not Programmed
X
ACK
Action from Device
Program Permanent Write Protect Register
(irreversible).
Clear (unprogram) Reversible Write Protect Register
(reversible).
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
13
Table 7-4.
WP Connected to VCC
WP Connected to VCC
Command
R/W
Bit
Permanent
Write Protect
Register PSWP
Reversible
Write Protect
Register
RSWP
Response
from
Device
1010
R
X
X
ACK
Read array.
1010
W
X
X
ACK
Device is write protected.
Read PSWP
R
Programmed
X
No ACK
STOP – Indicates pErmanent Write Protect Register is
programmed.
Read PSWP
R
Not Programmed
X
ACK
Data read out is undefined. Indicates PSWP Register is
not programmed.
Set PSWP
W
Programmed
X
No ACK
STOP – Indicates Permanent Write Protect Register is
programmed.
Set PSWP
W
Not Programmed
X
ACK
Read RSWP
R
X
Programmed
No ACK
STOP – Indicates Reversible Write Protect Register is
programmed.
Read RSWP
R
X
Not Programmed
ACK
Data read out is undefined. Indicates RSWP Register is
not programmed.
Set RSWP
W
X
Programmed
No ACK
STOP – Indicates Reversible Write Protect Register is
programmed.
Set RSWP
W
X
Not Programmed
ACK
Clear RSWP
W
Programmed
X
No ACK
Clear RSWP
W
Not Programmed
X
ACK
Action from Device
Cannot program write protect registers.
Cannot program write protect registers.
STOP – Indicates Permanent Write Protect Register is
programmed.
Cannot write to write protect registers.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
14
8.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are three types of read operations:

Current Address Read

Random Address Read

Sequential Read
Current Address Read: The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as long as VCC to the chip is
maintained. The address roll-over during read is from the last byte of the last memory page to the first byte of the first
page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. To end the command, the microcontroller does not respond with a zero
but does generate a Stop condition in the subsequent clock cycle (see Figure 8-3 on page 17).
Random Read: A random read requires a dummy byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another Start condition. The microcontroller now initiates a current address read by sending a device address
with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word.
To end the random read sequence, the microcontroller does not respond with a zero but does generate a Stop condition
in the subsequent clock cycle (see Figure 8-4 on page 17).
Sequential Read: Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the Serial EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a
following Stop condition in the subsequent clock cycle (see Figure 8-5 on page 17).
Serial Number Read: Reading the serial number is similar to the sequential read sequence but requires use of a
different device address value as shown in Figure 8-6 on page 18, followed by a dummy write, and the use of a specific
word address.
Note:
The entire 128-bit value must be read from the starting address of the serial number block to guarantee a
unique number.
Since the address pointer of the device is shared between the regular EEPROM array and the serial number block, a
dummy write sequence should be performed to ensure the address pointer is set to zero. Random reads of the serial
number block are supported but if the previous operation was to the EEPROM array, the address pointer will retain the
last location accessed, incremented by one. Reading the serial number from a location other than the first address of the
block will not result in a unique serial number.
Additionally, the most-significant four bits of the word address must be ‘1000’(8h). Thus, if the application desires to
read the pre-programmed serial number, then the corresponding word address input would be 80h. If a word address
other than 80h is used, then the device will output undefined data.
EUI Address Read: Reading the EUI address is very similar to the Serial Number read sequence with the exceptions of
the starting word address and the amount of data bytes clocked out (see Figure 8-7 on page 18). The EUI read sequence
requires use of the device address values as shown in Table 8-1 on page 16, followed by a dummy write, and the use of
a specific word address from Figure 3-1 on page 7 for EUI-48 standard or Figure 3-2 on page 7 for EUI-64 standard.
Note:
The entire six byte (EUI-48) or eight byte (EUI-64) values must be read from the respective starting address
of either 9Ah (for EUI-48) or 98h (for EUI-64) to guarantee a unique EUI data value.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
15
Since the address pointer of the device is shared between the regular EEPROM array, the serial number block, and the
EUI block, a dummy write sequence should be performed to ensure the address pointer is set to the correct starting EUI48 or EUI-64 address. Random reads of the EUI block are supported, but if the previous operation was to the EEPROM
array or to the serial number block, the address pointer will retain the last location accessed, incremented by one.
Reading the EUI data from a location other than the correct starting EUI address of the block will not result in a unique
EUI data value.
Additionally, the most-significant four bits of the word address must be ‘1001’(9h). Therefore, if the application desires
to read the pre-programmed EUI value, then the corresponding word address input would be 9Ah in the AT24MAC402
and 98h for the AT24MAC602. If a word address other than 9Ah or 98h respectively is used, the device will output
undefined data.
Once the EUI block of six or eight bytes of data have been clocked out of the device, the EUI read operation will end
when the microcontroller does not respond with a zero or acknowledge, but then creates a Stop condition. It is important
to note that the data word address will not roll-over back to the beginning of the respective EUI starting address. If the
read operation continues past the last EUI data value, the data word address will roll-over back to the beginning of the
extended memory block where the 128-bit serial number will begin to read out. Therefore, every EUI read sequence
attempt requires a valid starting address in the dummy write sequence as shown in Figure 8-7 on page 18.
Checking the Permanent Write Protect Register (PSWP) Status: Determining the status of the Permanent Write
Protect Register can be accomplished by sending a similar command to the device as was used when programming the
register, except the R/W bit must be set to one. If the device responds with an acknowledge, the Permanent Write Protect
Register has not been programmed; otherwise, it has been programmed and the first-half of the array is permanently
write protected.
Checking the Reversible Write Protect Register (RSWP) Status: Determining the status of the Reversible Write
Protect Register can be accomplished by sending a similar command to the device as was used when programming the
register, except the R/W bit must be set to one. If the device returns an acknowledge, the Reversible Write Protect
Register has not been programmed; otherwise, it has been programmed and the first-half of the array is write protected,
but remains reversible.
Table 8-1.
PSWP and RSWP Status
Pin
Preamble
R/W
Command
A2
A1
A0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read PSWP
A2
A1
A0
0
1
1
0
A2
A1
A0
1
Read RSWP
0
0
A0
0
1
1
0
0
0
1
1
Figure 8-1. Byte Write
S
T
A
R
T
Device
Address
W
R
I
T
E
Word
Address
S
T
O
P
Data
SDA LINE
M
S
B
L R A
S / C
BW K
A
C
K
A
C
K
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
16
Figure 8-2. Page Write
S
T
A
R
T
W
R
I
T
E
Device
Address
Word
Address
Data (n)
Data (n + 1)
S
T
O
P
Data (n + x)
SDA LINE
L R A
S / C
BW K
M
S
B
A
C
K
A
C
K
A
C
K
A
C
K
Figure 8-3. Current Address Read
S
T
A
R
T
R
E
A
D
Device
Address
S
T
O
P
Data
SDA LINE
L R A
S / C
BW K
M
S
B
N
O
A
C
K
Figure 8-4. Random Read
S
T
A
R
T
Device
Address
W
R
I
T
E
S
T
A
R
T
Word
Address (n)
Device
Address
R
E
A
D
S
T
O
P
Data (n)
SDA LINE
M
S
B
R A
/ C
W K
A
C
K
N
O
A
C
K
A
C
K
Dummy Write
Figure 8-5. Sequential Read
Device
Address
R
E
A
D
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
SDA LINE
R A
/ C
W K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
17
Figure 8-6. Serial Number Read
S
T
A
R
T
Device
Address
SDA LINE
W
R
I
T
E
1 0 1 1
S
T
A
R
T
Word
Address (n)
1 0 0 0 0 0 0 0
R A
/ C
W K
M
S
B
R
E
A
D
Device
Address
1 0 1 1
A
C
K
A
C
K
Serial Number
Data Byte 0h
A
C
K
Dummy Write
S
T
O
P
Serial Number
Data Byte 1h
Serial Number
Data Byte 2h
Serial Number
Data Byte 3h
Serial Number
Data Byte Fh
N
O
A
C
K
Figure 8-7. EUI Address Read
S
T
A
R
T
SDA LINE
Device
Address
1 0 1
M
S
B
W
R
I
T
E
1
S
T
A
R
T
Word
Address (n)
1 0
R A
/ C
W K
0
1
*
*
*
*
Device
Address
1
0
R
E
A
D
1 1
A
C
K
A
C
K
EUI Address
Data Byte (n)
A
C
K
Dummy Write
S
T
O
P
EUI Address
Data Byte (n + 1)
A
C
K
EUI Address
Data Byte (n + 2)
A
C
K
EUI Address
Data Byte (n + 3)
EUI Address
Data Byte (n + x)
N
O
A
C
K
* = 1010 (Ah) for 48-Bit EUI and 1000 (8h) for 64-Bit EUI.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
18
9.
Ordering Information
9.1
Ordering Code Detail
A T 2 4 M A C 4 0 2 – S S HM – T
Atmel Designator
Shipping Carrier Option
T = Tape and reel
Product Family
24MAC = I2C-compatible Serial EEPROM
with EUI address feature
with 128-bit serial number feature
EUI Option
4 = EUI-48 standard
6 = EUI-64 standard
Device Density
02 = 2-Kbit density
Operating Voltage
M = 1.7V to 5.5V
Package Device Grade or
Wafer/Die Thickness
H = Green, NiPdAu lead finish,
Industrial temperature range,
(–40°C to +85°C)
U = Green, matte Sn lead finish,
Industrial temperature range,
(–40°C to +85°C)
11 = 11 mil wafer thickness
Package Option
SS
X
MA
ST
WWU
=
=
=
=
=
JEDEC SOIC
TSSOP
UDFN
SOT23
Wafer unsawn
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
19
9.2
Atmel AT24MAC402 Ordering Codes
Programming of IEEE assigned customer OUIs (non-Atmel OUIs) in conjunction with specific blocks of EUI-48 values is
available. Please contact Atmel for more details.
Additional package types that are not listed may be available. Please contact Atmel for more details.
Atmel Ordering Codes
Package
AT24MAC402-SSHM-T(1) (NiPdAu lead finish)
8S1
AT24MAC402-XHM-T(1)
8X
(NiPdAu lead finish)
AT24MAC402-MAHM-T(1) (NiPdAu lead finish)
AT24MAC402-STUM-T
(1)
AT24MAC402-WWU11M(2)
Notes: 1.
2.
8MA2
Voltage
Operation Range
1.7V to 5.5V
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
5TS1
Industrial Temperature
(–40°C to 85°C)
Wafer Sale
T = Tape and reel

SOIC = 4K per reel

TSSOP, UDFN, and SOT23 = 5K per reel
For wafer sales, please contact Atmel Sales.
Package Type
8S1
8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 0.170" wide, Thin Shrink Small Outline (TSSOP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN)
5TS1
5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23)
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
20
9.3
Atmel AT24MAC602 Ordering Codes
Programming of IEEE assigned customer OUIs (non-Atmel OUIs) in conjunction with specific blocks of EUI-64 values is
available. Please contact Atmel for more details.
Additional package types that are not listed may be available. Please contact Atmel for more details.
Atmel Ordering Codes
Package
AT24MAC602-SSHM-T(1) (NiPdAu lead finish)
8S1
AT24MAC602-XHM-T(1)
8X
(NiPdAu lead finish)
AT24MAC602-MAHM-T(1) (NiPdAu lead finish)
AT24MAC602-STUM-T
(1)
AT24MAC602-WWU11M(2)
Notes: 1.
2.
8MA2
Voltage
Operation Range
1.7V to 5.5V
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
5TS1
Industrial Temperature
(–40°C to 85°C)
Wafer Sale
T = Tape and reel

SOIC = 4K per reel

TSSOP, UDFN and SOT23 = 5K per reel
For wafer sales, please contact Atmel Sales.
Package Type
8S1
8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 0.170" wide, Thin Shrink Small Outline (TSSOP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN)
5TS1
5-lead, 2.90mm x 1.60mm body, Plastic Thin Shrink Small Outline (SOT23)
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
21
10.
Part Markings
AT24MAC402 and AT24MAC602: Package Marking Information
8-lead SOIC
8-lead TSSOP
ATMLHYWW
## M
@
AAAAAAAA
8-lead UDFN
ATHYWW
## M @
AAAAAAA
5-lead SOT-23
2.0 x 3.0 mm Body
## MU
##
HM@
YXX
Note 1:
YMXX
Top Mark
Bottom Mark
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24MAC402
Truncation Code ##: P4
AT24MAC602
Truncation Code ##: P6
Date Codes
Y = Year
2: 2012
3: 2013
4: 2014
5: 2015
Voltages
6: 2016
7: 2017
8: 2018
9: 2019
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
M: 1.7V min
Grade/Lead Finish Material
Trace Code
H: Industrial/NiPdAu
U: Industrial/Matte Tin
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
4/3/12
TITLE
Package Mark Contact:
[email protected]
24MAC402-602SM, AT24MAC402 and AT24MAC602
Package Marking Information
DRAWING NO.
REV.
24MAC402-602CSM
C
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
22
11.
Packaging Information
11.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC)
GPC
SWB
DRAWING NO.
REV.
8S1
G
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
23
11.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
H
N
L
Top View
End View
A
b
A1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
Side View
Notes:
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
SYMBOL
D
1. This drawing is for general information only. Refer to JEDEC
Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
E
NOTE
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
–
0.30
4
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
12/8/11
TITLE
Package Drawing Contact:
[email protected]
GPC
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
TNR
DRAWING NO.
8X
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
REV.
E
24
11.3
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
A2
A
A1
E2
COMMON DIMENSIONS
(Unit of Measure = mm)
b (8x)
SYMBOL
8
1
7
2
MIN
D
Pin#1 ID
D2
6
3
5
4
e (6x)
1. This drawing is for general information only. Refer to JEDEC Drawing
MO-229, for proper dimensions, tolerances, datums, etc.
2. The terminal #1 ID is a laser-marked feature.
3. Dimension b applies to metallized terminal and is measured between
0.15 mm and 0.30 mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension should
not be measured in that radius area.
1.60
E2
1.20
1.30
1.40
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
–
–
0.55
0.152 REF
0.30
e
0.35
0.40
0.50 BSC
b
0.18
0.25
0.30
K
0.20
–
–
TITLE
Package Drawing Contact:
[email protected]
1.50
A
L
Notes:
3.00 BSC
1.40
C
K
L (8x)
3
7/15/11
GPC
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
NOTE
2.00 BSC
E
D2
MAX
NOM
YNZ
DRAWING NO.
8MA2
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
REV.
B
25
11.4
5TS1 — 5-lead SOT23
e1
C
4
5
E1
C
L
E
L1
1
3
2
END VIEW
TOP VIEW
b
A2
SEATING
PLANE
e
A
A1
D
SIDE VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash,
protrusions or gate burrs shall not exceed 0.15 mm per end. Dimension E1 does
not include interlead flash or protrusion. Interlead flash or protrusion shall not
exceed 0.15 mm per side.
2. The package top may be smaller than the package bottom. Dimensions D and E1
are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch
between the top and bottom of the plastic body.
3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15
mm from the lead tip.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion
shall be 0.08 mm total in excess of the "b" dimension at maximum material
condition. The dambar cannot be located on the lower radius of the foot. Minimum
space between protrusion and an adjacent lead shall not be less than 0.07 mm.
This drawing is for general information only. Refer to JEDEC
Drawing MO-193, Variation AB for additional information.
SYMBOL
MIN
A
A1
A2
c
D
E
E1
L1
e
e1
b
0.00
0.70
0.08
MAX
NOM
0.90
2.90 BSC
2.80 BSC
1.60 BSC
0.60 REF
0.95 BSC
1.90 BSC
0.30
-
1.00
0.10
1.00
0.20
0.50
NOTE
3
1,2
1,2
1,2
3,4
5/31/12
Package Drawing Contact:
[email protected]
TITLE
GPC
5TS1, 5-lead 1.60mm Body, Plastic Thin
Shrink Small Outline Package (Shrink SOT)
TSZ
DRAWING NO.
5TS1
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
REV.
D
26
12.
Revision History
Doc.rev.
Date
8807A
06/2012
Description
Initial document release.
Atmel AT24MAC402/602 [DATASHEET]
8807A–SEEPR–6/12
27
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© 2012 Atmel Corporation. All rights reserved. / Rev.: 8807A–SEEPR–6/12
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