Cypress CY6116A-20PC 2k x 8 static ram Datasheet

6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
Features
Pin Configurations
DIP/SOJ
Top View
A6
2
23
A8
A5
3
22
A9
A4
4
21
WE
A3
5
25
WE
OE
A2
6
24
OE
19
A10
NC
7
23
A10
18
CE
NC
8
22
NC
21
NC
8
17
I/O7
9
16
I/O6
10
I/O2
11
14
I/O4
GND
12
13
I/O3
15
27
NC
A0
A0
I/O0
8
6117A
9
Commercial
Military
Commercial
Military
Cypress Semiconductor Corporation
D
20
100
40/20
3901 North First Street
1
OE
24
A10
11
23
CE
12
22
I/O7
13
21
I/O6
10
I/O
1
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
6116A-20
6117A-20
WE
25
14 15 16 17 1819 20
6116A-1
Selection Guide
26
6116A-25
6117A-25
25
100
125
20
40
D
6116A-35
6117A-35
San Jose
35
100
100
20
20
I/O
4
I/O
5
A1
V
CC
A9
7
NC
A2
NC
A8
28
NC
A3
NC
29
A1
I/O7
1 32 31 30
6
A2
OE
2
A5
A3
DOWN
DECODER
3
5
I/O
3
COLUMN
4
A6
A4
I/O6
POWER
NC
I/O5
WE
6116A-3
LCC
Top View
I/O4
CE
I/O7
6116A-2
I/O3
A4
CE
19
1213 14 151617 18
GND
A5
20
11
A7
ARRAY
10
NC
128 x 16 x 8
9
A0
I/O0
I/O5
I/O1
6116A
I/O
6
A0
I/O0
2 1 28 27 26
A1
NC
A6
6116A
I/O
2
A7
7
I/O2
SENSE AMPS
A8
ROW DECODER
A9
A1
3
1
I/O
2
I/O1
A10
6
20
4
I/O
I/O0
5
A2
A9
VCC
A6
24
A5
1
A4
A7
A3
INPUT BUFFER
LCC
Top View
V
CC
Logic Block Diagram
A8
D
D
I/O
5
D
A7
D
The CY6116A and CY6117A are highĆ
performance CMOS static RAMs orgaĆ
nized as 2048 words by 8 bits. Easy
memoryexpansionisprovidedbyanactive
LOW chip enable (CE) and active LOW
output enable (OE), and threeĆstate drivĆ
ers. The CY6116A and CY6117A have an
automatic powerĆdown feature, reducing
the power consumption by 83% when deĆ
selected.
Writingtothedeviceisaccomplishedwhen
the chip enable (CE) and write enable
(WE) inputs are both LOW. Data on the
I/Opins(I/O0 throughI/O7)iswritteninto
Automatic powerĆdown when
deselected
CMOS for optimum speed/power
High speed
Ċ 20 ns
Low active power
Ċ 550 mW
Low standby power
Ċ 110 mW
TTLĆcompatible inputs and outputs
Capable of withstanding greater
than 2001V electrostatic discharge
I/O
3
I/O
4
D
D
the memory location specified on the adĆ
dress pins (A0 through A10).
ReadingthedeviceisaccomplishedbytakĆ
ing chip enable (CE) and output enable
(OE) LOW while write enable (WE) reĆ
mainsHIGH.Undertheseconditions,the
contents of the memory location specified
on the address pins will appear on the I/O
pins.
The I/O pins remain in highĆimpedance
state when chip enable (CE) is HIGH or
write enable (WE) is LOW.
The CY6116A and CY6117A utilize a die
coat to insure alpha immunity.
Functional Description
GND
D
2K x 8 Static RAM
6116A-45
6117A-45
45
100
100
20
20
6116A-4
6116A-55
6117A-55
55
80
100
20
20
D CA 95134 D 408-943-2600
February 1988 - Revised December 1992
6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . >2001V
(per MILĆSTDĆ883, Method 3015)
Storage Temperature . . . . . . . . . . . . . . . . . . -65_C to +150_C
LatchĆUp Current . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C
Operating Range
Ambient
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Range
Commercial
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Military[1]
Temperature
VCC
0_C to +70_C
5V ± 10%
-55_C to +125_C
5V ± 10%
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -3.0V to +7.0V
Output Current into Outputs (LOW) . . . . . . . . . . . . . . 20 mA
Electrical Characteristics
Parameter
VOH
Over the Operating Range[2]
Description
Test Conditions
6116A-20
6116A-25, 35, 45
6116A-55
6117A-20
6117A-25, 35, 45
6117A-55
Min.
Max.
Min.
Max.
Max.
2.4
VOL
0.4
V
VIH
Input HIGH Voltage
2.2
VCC
2.2
VCC
2.2
VCC
V
VIL
Input LOW Voltage[3]
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
IIX
Input Load Current
GND < VI < VCC
-10
+10
-10
+10
-10
+10
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
-10
+10
-10
+10
-10
+10
mA
mA
IOS
Output Short
Circuit Current[4]
VCC = Max., VOUT = GND
-300
mA
ICC
VCC Operating
p
g
S
l Current
C
Supply
VCC = Max.
A
IOUT = 0 mA
f = fMAX = 1/tRC
Com'l
mA
Automatic CE
P
PowerĆDown
D
Current
C
- TTL Inputs
Max. VCC,
CE > VIH
f = fMAX
Com'l
Automatic CE
PowerĆDown Current
- CMOS Inputs
Max. VCC,
Com'l
CE > VIH - 0.3V,
VIN > VCC - 0.3V
or VIN < 0.3V,
Mil
f=0
ISB2
0.4
2.4
Unit
OutputHIGHVoltage VCC = Min., IOH = -4.0 mA
Output LOW Voltage VCC = Min., IOL = 8.0 mA
ISB1
2.4
Min.
0.4
V
-300
-300
100
100
80
125
100
Mil 25
35, 45
100
40
Mil 25
35, 45, 55
20
20
40
20
mA
20
20
20
20
20
20
mA
[5]
Capacitance
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25_C, f = 1 MHz,
VCC = 5.0V
5 0V
Notes:
1.
2.
3.
TA is the instant on" case temperature.
See the last page of this specification for Group A subgroup testing inĆ
formation.
VIL (min.) = -3.0V for pulse durations less than 30 ns.
4.
5.
2
Max.
Unit
10
pF
10
pF
Not more than 1 output should be shorted at one time. Duration of the
short circuit should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect
these parameters.
6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
AC Test Loads and Waveforms
R1 481W
5V
OUTPUT
5V
OUTPUT
R2
255W
30 pF
INCLUDING
JIG AND
SCOPE
5 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 481W
3.0V
R2
255W
GND
10%
5 ns
ALL INPUT PULSES
90%
90%
10%
5 ns
6116A-5
(b)
6116A-6
Equivalent to:
THÉVENIN EQUIVALENT
167W
OUTPUT
1.73V
Switching Characteristics Over the Operating Range[2, 6]
6116A-20
6117A-20
Parameter
Description
Min.
6116A-25
6117A-25
Max.
Min.
Max.
6116A-35
6117A-35
Min.
Max.
6116A-45
6117A-45
Min.
Max.
6116A-55
6117A-55
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
20
25
35
45
55
ns
tDOE
OE LOW to Data Valid
10
12
15
20
25
ns
tLZOE
OE LOW to Low Z
tHZOE
20
OE HIGH to High Z
20
5
3
[8]
CE LOW to Low Z
tHZCE
CE HIGH to High Z[7, 8 ]
tPU
CE LOW to PowerĆUp
tPD
CE HIGH to PowerĆDown
35
25
5
[7]
tLZCE
WRITE CYCLE
25
35
5
3
8
5
8
0
20
20
5
0
20
ns
20
15
ns
ns
20
0
25
ns
ns
3
5
0
55
15
15
ns
5
3
5
0
45
12
10
55
5
3
10
5
45
ns
ns
25
ns
[9]
tWC
Write Cycle Time
20
20
25
40
50
ns
tSCE
CE LOW to Write End
15
20
25
30
40
ns
tAW
Address SetĆUp to Write End
15
20
25
30
40
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address SetĆUp to Write Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
15
15
20
20
25
ns
tSD
Data SetĆUp to Write End
10
10
15
15
25
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z
7
7
5
5
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing refĆ
erence levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading
of the specified IOL/IOH and 30ĆpF load capacitance.
7.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b)
of AC Test Loads. Transition is measured ±500 mV from steady state
voltage.
8.
At any given temperature and voltage condition, tHZCE is less than
tLZCE for any given device.
9.
3
10
5
15
5
20
5
ns
ns
The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input setĆ
up and hold timing should be referenced to the rising edge of the signal
that terminates the write.
6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
DATA VALID
6116A-7
Read Cycle No. 2[10, 12]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
VCC
SUPPLY
CURRENT
tLZOE
HIGH IMPEDANCE
tLZCE
tPU
50%
HIGH
IMPEDANCE
DATA VALID
tPD
50%
ICC
ISB
6116A-8
Write Cycle No. 1 (WE Controlled)[9, 13]
tWC
ADDRESS
tSCE
CE
tSA
tAW
WE
tSD
DATA VALID
DATA IN
tHZWE
DATA I/O
tHA
tPWE
DATA UNDEFINED
tHD
tLZWE
HIGH IMPEDANCE
6116A-9
Notes:
10.
WE is HIGH for read cycle.
11.
Device is continuously selected. OE, CE = VIL.
12.
Address valid prior to or coincident with CE transition LOW.
13.
Data I/O pins enter highĆimpedance state, as shown, when OE is held
LOW during write.
4
6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[9, 13, 14]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tHD
tSD
DATAIN VALID
DATA IN
tHZWE
HIGH IMPEDANCE
DATA I/O
DATA UNDEFINED
6116A-10
Note:
14. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a highĆimpedance state.
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
SB
1.2
NORMALIZED I CC, I
ICC
1.0
0.8
0.6
0.4
0.0
4.0
4.5
5.0
ICC
0.8
0.6
0.4
VCC = 5.0V
VIN = 5.0V
0.2
ISB
0.2
1.0
5.5
ISB
0.0
-55
6.0
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
1.4
1.2
TA = 25_C
1.0
0.9
5.0
5.5
SUPPLY VOLTAGE (V)
100
80
VCC = 5.0V
60
TA = 25_C
40
20
0
0.0
6.0
1.2
1.0
VCC = 5.0V
0.6
-55
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.8
4.5
120
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
0.8
4.0
125
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE (_C)
SUPPLY VOLTAGE (V)
1.1
25
OUTPUT SINK CURRENT (mA)
NORMALIZED I CC, I
SB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
140
120
100
VCC = 5.0V
TA = 25_C
80
60
40
20
0
25
125
AMBIENT TEMPERATURE (_C)
5
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
Typical DC and AC Characteristics (continued)
TYPICAL POWERĆON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
30.0
2.5
25.0
NORMALIZED ICC vs. CYCLE TIME
1.4
2.0
1.5
1.0
20.0
15.0
10.0
0.5
0.0
VCC = 4.5V
TA = 25_C
5.0
0.0
1.0
2.0
3.0
4.0
5.0
NORMALIZED I CC
DELTA t AA (ns)
NORMALIZED I PO
VCC = 5.0V
0.0
SUPPLY VOLTAGE (V)
TA = 25_C
1.3
VIN = 0.5V
1.2
1.1
1.0
0.9
0.8
0
200
400
600
800
1000
0
CAPACITANCE (pF)
10
20
CYCLE FREQUENCY (MHz)
Ordering Information
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY6116A-20PC
P11
28ĆLead (300ĆMil) Molded DIP
Commercial
25
CY6116A-25PC
P11
28ĆLead (300ĆMil) Molded DIP
Commercial
CY6116A-25DMB
D12
24ĆLead (600ĆMil) CerDIP
Military
CY6116A-25LMB
L64
28ĆSquare Leadless Chip Carrier
CY6116A-35PC
P11
28ĆLead (300ĆMil) Molded DIP
Commercial
CY6116A-35DMB
D12
24ĆLead (600ĆMil) CerDIP
Military
CY6116A-35LMB
L64
28ĆSquare Leadless Chip Carrier
CY6116A-45PC
P11
28ĆLead (300ĆMil) Molded DIP
Commercial
CY6116A-45DMB
D12
24ĆLead (600ĆMil) CerDIP
Military
CY6116A-45LMB
L64
28ĆSquare Leadless Chip Carrier
CY6116A-55PC
P11
28ĆLead (300ĆMil) Molded DIP
Commercial
CY6116A-55DMB
D12
24ĆLead (600ĆMil) CerDIP
Military
CY6116A-55LMB
L64
28ĆSquare Leadless Chip Carrier
35
45
55
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
35
CY6117AĆ35LMB
L55
32ĆPin Rectangular Leadless Chip Carrier
Military
45
CY6117AĆ45LMB
L55
32ĆPin Rectangular Leadless Chip Carrier
Military
55
CY6117AĆ55LMB
L55
32ĆPin Rectangular Leadless Chip Carrier
Military
6
30
40
6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VIL Max.
IIX
IOZ
ICC
ISB
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Switching Characteristics
Parameter
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
WRITE CYCLE
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Document #: 38-00105-B
7
6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
Package Diagrams
24ĆLead (600ĆMil) CerDIP D12
32ĆPin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 D-3 Config. A
MIL-STD-1835 C-12
28ĆSquare Leadless Chip Carrier L64
MIL-STD-1835 C-4
8
6116A: 11/8/89
Revision: Monday, November 8, 1993
CY6116A
CY6117A
Package Diagrams (continued)
24ĆLead (600ĆMil) Molded DIP P11
E
Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice.
Cypress Semiconductor Corporatio n assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under pa tent or other rights. Cypress SemiconĆ
ductor does not authorize its products for use as critical components in lifeĆsupport systems where a malfunction or failure of the product may reason ably be expected to result in significant
9
injury to the user. The inclusion of Cypress Semiconductor products in lifeĆsupport systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies
Cypress Semiconductor against all damages.
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