STMicroelectronics ESDA18-1F2 Transient voltage suppressor Datasheet

ESDA18-1F2
®
ASD
(Application Specific Devices)
TRANSIL™: Transient Voltage Suppressor
FEATURES AND BENEFITS:
■
■
■
■
■
Stand-off voltage 16V
Unidirectional device
Low clamping factor VCL/VBR
Fast response time
Very thin package: 0.65 mm
DESCRIPTION
The ESDA18-1F2 is a single line Transil diode
designed specifically for the protection of
integrated circuits into portable equipment and
miniaturized electronics devices subject to ESD &
EOS transient overvoltages.
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
Level 4
15kV (air discharge)
8kV (contact discharge)
Flip-Chip
(4 Bumps)
Table 1: Order Code
Part Number
Marking
ESDA18-1F2
EE
Figure 1: Pin Configuration (ball side)
A
B
1
K
A
2
K
K
A
A
TM: TRANSIL is a trademark of STMicroelectronics.
May 2005
REV. 1
1/7
ESDA18-1F2
Table 2: Absolute Ratings (limiting value, per diode)
Symbol
PPP
Parameter and test conditions
Value
Peak pulse power dissipation
10 / 1000 µs pulse
100
Tj initial = Tamb
Peak pulse power dissipation
8 / 20 µs pulse
W
700
IFSM
Non repetitive surge peak forward current
Tj
Maximum operating junction temperature
Tstg
Unit
tp=10 ms
Tj initial = Tamb
Storage temperature range
8
A
125
°C
- 65 to + 175
°C
Table 3: Electrical Characteristics (Tamb = 25°C)
Symbol
Parameter
VBR
Breakdown voltage
IRM
Leakage current
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic impedance
IPP
Peak pulse current
C
I
IF
VF
VCL VBR
VRM
V
IRM
Slope: 1/Rd
IPP
Capacitance
IR
VBR
Part Number
ESDA18-1F2
min.
max.
IRM
VRM
max.
VCL
IPP (1)
max.
VF (2)
αT
C
max.
max.
typ.
IF = 850mA
VR=0V
V
V
mA
µA
V
V
A
V
10-4/°C
16
18
1
0.5
10
20
1
1.3
8.5
pF
230
(1) 8 / 20 µs pulse waveform.
(2) DC current not recommended for more than 5 sec. Even if Transil failure mode is short circuit the bumps could exceed melting temperature and the component disassembled from the board.
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ESDA18-1F2
Figure 2: Relative variation of peak pulse
power versus initial junction temperature
Figure 3: Peak pulse power versus exponential pulse duration
PPP[Tj initial] / PPP[Tj initial=25°C)
PPP(W)
10000
1.1
1.0
Tj initial=25°C
0.9
0.8
1000
0.7
0.6
0.5
0.4
100
0.3
0.2
0.1
Tj(°C)
tp(µs)
0.0
10
0
25
50
75
100
125
150
Figure 4: Clamping voltage versus peak pulse
current (typical values, exponential waveform)
1
10
100
1000
Figure 5: Forward voltage drop versus peak
forward current (typical values)
IFM(A)
IPP(A)
100.0
1.E+01
8/20µs
Tj initial=25°C
1.E+00
Tj=125°C
10.0
Tj=25°C
1.E-01
1.0
1.E-02
VFM(V)
VCL(V)
0.1
1.E-03
10
12
14
16
18
20
22
24
26
28
30
Figure 6: Junction capacitance versus reverse
voltage applied (typical values)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Figure 7: Relative variation of leakage current
versus junction temperature (typical values)
IR[Tj] / IR[Tj=25°C]
C(pF)
300
100
VR=10V
F=1MHz
VOSC=30mVRMS
Tj=25°C
250
200
150
10
100
50
VR(V)
Tj(°C)
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
25
50
75
100
125
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ESDA18-1F2
One major point is that the ESDA18-1F2 has to ensure the safety during reverse battery operation. Indeed,
during this operation the device must clamp the DC reverse voltage below 1.3V @ 0.85A (max current).
Thus reverse battery operation has been simulated by inverting the polatrity of the TRANSIL (please see
figures 8 and 9)
Figure 8: Reverse battery operation setup
Equivalent
mobile phone
impedance
PTC
Vmains
I
V
4.7kΩ
1nF
ESDA18-1F2
Figure 9: Reverse battery operation results
A short calculation based on Reverse battery operation results figures clearly show that in such real phone
application the ESDA18-1F2 clamp the DC voltage below 1.3V.
Typically the ESDA18-1F2 can clamp the DC voltage @ 0.9V @0.76A DC current:
2 × V max 2 × 1.4
V DC = ----------------------- ≈ ----------------- ≈ 0.9V
Π
3.14
2 × I max 2 × 1.2
I DC = --------------------- ≈ ----------------- ≈ 0.76A
Π
3.14
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ESDA18-1F2
Figure 10: Ordering Information Scheme
ESDA
18 - 1
Fx
ESD Array
Breakdown Voltage
18 = 18 Volts max.
Number of line
1 = signle line
Package
F = Flip-Chip
x = 2: Leadfree Pitch = 500µm, Bump = 315µm
Figure 11: FLIP-CHIP Package Mechanical Data
650µm ± 65
500µm ± 50
500µm ± 50
0.95mm ± 50µm
315µm ± 50
0.95mm ± 50µm
Figure 12: Foot Print Recommendations
Dot, ST logo
xx = marking
z = packaging location
yww = datecode
(y = year
ww = week)
365
E
Solder stencil opening : 330µm
x x z
y ww
40
220
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
240
365
Copper pad Diameter :
250µm recommended , 300µm max
Figure 13: Marking
All dimensions in µm
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ESDA18-1F2
Figure 14: FLIP-CHIP Tape and Reel Specification
Dot identifying Pin A1 location
1.75 +/- 0.1
Ø 1.5 +/- 0.1
4 +/- 0.1
3.5 +/- 0.1
STE
xxx
yww
STE
xxx
yww
STE
xxx
yww
8 +/- 0.3
0.73 +/- 0.05
4 +/- 0.1
User direction of unreeling
All dimensions in mm
Table 4: Ordering Information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
ESDA18-1F2
EE
Flip-Chip
1.25 mg
5000
Tape & reel 7”
Note: More packing informations are available in the application note
AN1235: “Flip-Chip: Package description and recommendations for use”
Table 5: Revision History
6/7
Date
Revision
09-May-2005
1
Description of Changes
First issue.
ESDA18-1F2
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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