TH58NVG1S3AFT05 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2GBIT (256M u 8BITS) CMOS NAND E2PROM DESCRIPTION The TH58NVG1S3A is a single 3.3-V 2G-bit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 2048 blocks. The device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages). The TH58NVG1S3A is a serial-type memory device which utilizes the I/O pins for both address and data input / output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density nonvolatile memory data storage. FEATURES x Organization Memory cell allay 2112 u 64K u 8 u 2 Register 2112 u 8 Page size 2112bytes Block size (128K 4K) bytes x Modes Read㧘Reset㧘Auto Page Program Auto Block Erase㧘Status Read x Mode control Serial input㧛output Command control PIN ASSIGNMENT (TOP VIEW) NC NC NC NC NC GND RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 x Powersupply x Program/Erase Cycles x Access time Cell array to register Serial Read Cycle x Operating current Read (50 ns cycle) Program (avg.) Erase (avg.) Standby x Package TSOP I 48-P-1220-0.50 (Weight : 0.53 g typ.) VCC 2.7 V to 3.6 V 1E5 Cycles(With ECC) 25 Psmax 50 ns min 10 mA typ. 10 mA typ. 10 mA typ. 50 PA max PIN NAMES NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect RY / BY Ready / Busy GND Ground Input VCC Power supply VSS Ground 000707EBA1 xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 2003-05-19A 1/32 TH58NVG1S3AFT05 BLOCK DIAGRAM VCC VSS Status register Address register I/O1 I/O Control circuit to I/O8 Column buffer Column decoder Command register Data register Sense amp Row address buffer decoder CLE Logic control ALE Control circuit WE RE WP Row address decorder CE Memory cell array RY / BY RY / BY HV generator ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VCC Power Supply Voltage 0.6 to 4.6 V VIN Input Voltage 0.6 to 4.6 V VI/O Input /Output Voltage 0.6 V to VCC 0.3 V (≦ 4.6 V) V PD Power Dissipation 0.3 W TSOLDER Soldering Temperature (10s) 260 °C TSTG Storage Temperature -55 to 150 °C TOPR Operating Temperature 0 to 70 °C CAPACITANCE *(Ta 25°C, f 1 MHz) SYMB0L PARAMETER CONDITION CIN Input VIN COUT Output VOUT 0V 0V MIN MAX UNIT 20 pF 20 pF * * This parameter is periodically sampled and is not tested for every device. xThe products described in this document are subject to the foreign exchange and foreign trade laws. xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. xThe information contained herein is subject to change without notice. 2003-05-19A 2/32 TH58NVG1S3AFT05 VALID BLOCKS (1) SYMBOL NVB PARAMETER Number of Valid Blocks MIN. TYP. MAX UNIT 2008 - 2048 Blocks (1) The TH58NVG1S3A occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. (2) The first block (block address #00) is guaranteed to be a valid block at the time of shipment. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7 3.3 3.6 V VIH High Level input Voltage 2.0 VCC 0.3 V VIL Low Level Input Voltage 0.3* 0.8 V 2 V (pulse width lower than 20 ns) * DC CHARACTERISTICS (Ta 0 to 70℃, VCC 2.7V ~ 3.3 V) SYMBOL PARAMETER CONDITION TYP. MAX UNIT r10 PA r10 PA 10 30 mA IIL Input Leakage Current VIN ILO Output Leakage Current VOUT ICCO1 Reading CE ICCO7 Programming Current 10 30 mA ICCO8 Erasing Current 10 30 mA ICCS1 Standby Current CE VIH , WP 0V/VCC 1 mA ICCS2 Standby Current CE VCC 0.2 V, WP 0V/VCC 50 PA VOH High Level Output Voltage Vcc, IOH 400 PA 2.4 V VOL Low Level Output Voltage Vcc, IOL 2.1 mA 0.4 V 8 mA IOL ( RY / BY ) Output current of RY / BY pin VOL 0 V to VCC MIN 0 V to VCC VIL, IOUT 0.4 V 0 mA, tcycle 50 ns 2003-05-19A 3/32 TH58NVG1S3AFT05 AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta 0 to 70℃, VCC 2.7V ~ 3.6V) SYMBOL PARAMETER MIN MAX UNIT tCLS CLE Setup Time 0 ns tCLH CLE Hold Time 10 ns tCS CE Setup Time 0 ns tCH CE Hold Time 10 ns tWP Write Pulse Width 25 ns tALS ALE Setup Time 0 ns tALH ALE Hold Time 10 ns tDS Data Setup Time 20 ns tDH Data Hold Time 10 ns tWC Write Cycle Time 50 ns tWH WE High Hold Time 15 ns tWW WP High to WE Low 100 ns tRR Ready to RE Falling Edge 20 ns tRW Ready to WE Falling Edge 20 ns tRP Read Pulse Width 35 ns tRC Read Cycle Time 50 ns tREA RE Access Time (Serial Data Access) 35 ns tCEA CE Access Time 45 ns tCLEA CLE Access Time 45 ns tALEA ALE Access Time 45 ns tREAID RE Access Time (ID Read) 35 ns tOH Data Output Hold Time 10 ns tRHZ RE High to Output High Impedance 30 ns tCHZ CE High to Output High Impedance 20 ns tREH RE High Hold Time 15 ns tIR Output-High-impedance-to- RE Falling Edge 0 ns tRSTO RE Access Time (Status Read) 35 ns tCSTO CE Access Time (Status Read) 45 ns tCLSTO CLE Access Time (Status Read) 45 ns tRHW RE High to WE Low 30 ns tWHC WE High to CE Low 30 ns tWHR WE High to RE Low 30 ns tR Memory Cell Array to Starting Address 25 Ps tWB WE High to Busy 200 ns tRST Device Reset Time (Read/Program/Erase) 6/10/500 Ps NOTES 2003-05-19A 4/32 TH58NVG1S3AFT05 AC TEST CONDITIONS PARAMETER CONDITION Input level 2.4 V, 0.4 V Input pulse rise and fall time 3ns Input comparison level 1.5 V, 1.5 V Output data comparison level 1.5 V, 1.5 V CL (100 pF) 1 TTL Output load PROGRAMMING AND ERASING CHARACTERISTICS (Ta 0 to 70℃, VCC 2.7V ~ 3.6V) SYMBOL tPROG PARAMETER Average Programming Time MIN TYP. MAX UNIT 200 700 Ps 2 2 4 NOTES Number of Programming Cycles on Same Page N (1) (per 512+16 bytes) tBERASE Block Erasing Time ms (1) Refer to Application Note (12) toward the end of this document. 2003-05-19A 5/32 TH58NVG1S3AFT05 TIMING DIAGRAMS Latch Timing Diagram for Command/Address /Data CLE ALE CE RE Setup Time Hold Time WE tDS tDH I/O : VIH or VIL Command Input Cycle Timing Diagram CLE tCLS tCLH tCS tCH CE tWP WE tALS tALH ALE tDS tDH I/O : VIH or VIL 2003-05-19A 6/32 TH58NVG1S3AFT05 Address Input Cycle Timing Diagram tCLS CLE tCS tWC tWC tWC tWC CE tWP tWH tWP tWH tWP tWH tWP tWH tWP WE tALS tALH ALE tDS I/O tDH tDS CA0 to7 tDH tDS CA8 to11 tDH PA0 to 7 tDS tDH tDS PA8 to 15 tDH PA16 : VIH or VIL Data Input Cycle Timing Diagram tCLH CLE tCH CE tALS tWC ALE tWP tWH tWP tWP WE tDS I/O tDH DIN0 tDS tDH DIN1 tDS tDH DIN2111 : VIH or VIL 2003-05-19A 7/32 TH58NVG1S3AFT05 Serial Read Cycle Timing Diagram tRC tCEA CE tRP tREH RE tRP tOH tREA tRHZ tRP tCHZ tOH tREA tOH tRHZ tREA tRHZ I/O tRR RY / BY Status Read Cycle Timing Diagram tCLSTO CLE tCLS tCLH tCS CE tWP tCH WE tWHC tCSTO tCHZ tWHR RE tOH tDS I/O tDH 70H* tIR tRSTO tRHZ Status output RY / BY * 70H represents the hexadecimal number : VIH or VIL 2003-05-19A 8/32 TH58NVG1S3AFT05 Read Cycle Timing Diagram tCLEA CLE tCLS tCLH tCLS tCLH tCS tCH tCS tCH tCEA CE tWC WE tALH tALS tALH tALS ALE tR tRC tWB RE tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tREA tRR I/O 00H CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15 DOUT DOUT N N1 30H PA16 Data out from Col. Add. N Col. Add. N RY / BY Read Cycle Timing Diagram : When Interrupted by /CE tCLEA CLE tCLS tCLH tCLS tCLH tCS tCH tCS tCH tCEA CE tWC WE tALH tALS tALH tALS tCHZ ALE tR tRC tWB RE tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tOH tREA tRR I/O tRHZ 00H CA0 to 7 CA8 to 11 PA0 to 7 PA8 to 15 PA16 DOUT DOUT N N1 30H Col. Add. N Col. Add. N RY / BY 2003-05-19A 9/32 TH58NVG1S3AFT05 Column Address Change in Read Cycle Timing Diagram (1/2) tCLEA CLE tCLS tCLH tCS tCH tCLS tCS tCLH tCH CE tWC tCEA WE tALH tALS tALS tALH ALE tRC tR tWB RE tDS tDH tDS tDH tDS tDH tDH tDS tDH tDS tDH tDS tDH tDS tDH tREA I/O 00H CA0 to CA8 to PA0 to PA8 to 7 11 7 15 Column address A tRR PA16 30H DOUT DOUT A A1 DOUT AN Page address P Page address P RY / BY Column address A 1 Continues to 2003-05-19A 1 of next page 10/32 TH58NVG1S3AFT05 Column Address Change in Read Cycle Timing Diagram (2/2) tCLEA CLE tCLS tCS tCLS tCLH tCH tCS tCLH tCH CE tWC tCEA WE tRHW tALH tALS tALH tALS ALE tRC RE tDS tDH tDS tDH tDS tDH tDS tDH tIR I/O DOUT AN 05H CA0 to CA8 to 7 11 Column address B E0H tREA DOUT DOUT B B1 DOUT B N’ Page address P RY / BY Column address B 1 Continued from 1 of last page 2003-05-19A 11/32 TH58NVG1S3AFT05 Auto-Program Operation Timing Diagram tCLS CLE tCLS tCLH tCS tCS CE tCH WE tALH tALH tProg tALS tWB tALS ALE RE tDS tDS tDH I/O 80H tDS tDH tDS tDH CA0 to CA8 to PA0 to PA8 to PA16 7 11 7 15 DIN0 tDH DIN1 10H 70H Status output DIN2111* RY / BY : Do not input data while data is being output. : VIH or VIL 2003-05-19A 12/32 TH58NVG1S3AFT05 Auto Block Erase Timing Diagram CLE tCLS tCLH tCS tCLS CE WE tALH tALS tWB tBERASE ALE RE tDS tDH I/O RY / BY 60H PA0 to 7 Auto Block Erase Setup command : VIH or VIL PA8 to 15 PA16 D0H Erase Start command 70H Busy Status output Status Read command : Do not input data while data is being output. 2003-05-19A 13/32 TH58NVG1S3AFT05 ID Read Operation Timing Diagram tCLS CLE tCLS tCS tCH tCEA CE tCS tCH WE tALH tALH tALS tALEA ALE RE tDH I/O tDH 90H ID Read command tREAID 00H Address 00 tREAID 98H Maker code tREAID DAH tREAID Note1 tREAID Note2 Note3 Device code Note1 : 81H or 01H Note2 : 95H or 15H Note3 : 44H or C4H : VIH or VIL 2003-05-19A 14/32 TH58NVG1S3AFT05 PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. Address Latch Enable: ALE The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is latched if ALE is Low. NC NC NC NC NC GND RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Chip Enable: CE 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC Figure 1. Pinout The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The CE signal is ignored when device is in Busy state ( RY / BY L ), such as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE input goes High. Write Enable: WE The WE signal is used to control the acquisition of data from the I/O port. Read Enable: RE The RE signal controls serial data output. Data is available tREA after the falling edge of RE . The internal column address counter is also incremented (Address = Address + l) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: RY / BY The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state ( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled-up to Vccq with appropriate resister.. 2003-05-19A 15/32 TH58NVG1S3AFT05 Schematic Cell Layout and Address Assignment The Program operation works on page units while the Erase operation works on block units. I/O1 2048 A page consists of 2112 bytes in which 2048 bytes are used for main memory storage and 64 bytes are for redundancy or for other uses. 1 page = 2112bytes 1 block = 2112 bytes x 64 pages = (128K + 4K) bytes Capacity = 2112bytes x 64pages x 2048blocks I/O8 64 64Pages = 1block An address is read in via the I/0 port over four consecutive clock cycles, as shown in Table 1. 8I/O 2112 Figure 2. Schematic Cell Layout Table 1. Addressing CA0 to CA11 : Column address PA0 to PA16 : Page address I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 L L L L CA11 CA10 CA9 CA8 PA6 to PA16 Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PA0 to PA5 Fourth cycle PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 L L L L L L L PA16 First cycle Second cycle Fifth cycle : Block address : NAND address in block Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by the eleven different command operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2. Table 2. Logic Table CLE ALE CE Command Input H L Data Input L Address input *1 RE WP L H * L L H H L H L H * Serial Data Output L L L H During Programming (Busy) * * * * * H During Erasing (Busy) * * * * * H During * * * * * * Program, Erase Inhibit * * * * * L Standby * * H * * 0 V/Vcc Reading (Busy) WE * H: VIH, L: VIL, *: VIH or VIL *1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit 2003-05-19A 16/32 TH58NVG1S3AFT05 Table 3. Command table (HEX) First Cycle Second Cycle Serial Data Input 80 Auto Program 10 Read Address Input 00 Column Address Change in Serial Data Output 05 Read Start 30 Acceptable while Busy E0 Auto Block Erase 60 D ID Read 90 Status Read 70 ○ Reset FF ○ Read Column Change HEX data bit assignment (Example) Serial Data Input : 80H 0 0 0 0 0 0 I/O8 7 1 6 5 4 3 2 I/O1 0 Table 4 shows the operation states for Read mode. Table 4. Read mode operation states CLE ALE CE WE RE I/O1 to I/O8 Power Output select L L L H L Data output Active Output Deselect L L L H H High impedance Active Standby L L H H * High impedance Standby Read Busy * * * * * High Impedance Active H: VIH, L: VIL, *: VIH or VIL 2003-05-19A 17/32 TH58NVG1S3AFT05 DEVICE OPERATION Read Mode Read mode is set when "00H" and “30H” commands are issued to the Command register. Between the commands, start address for the Read mode need to be issued. Refer to Figure 3 below for sequence and the block diagram (Refer to the detailed timing chart.). CLE CE WE ALE RE RY / BY Column Address M Busy Page Address N 00H I/O 30H M+1 M M+2 Page Address N Start-address input M 2111 Select page N Cell array A data transfer operation from the cell array to the register starts on the rising edge of WE in the 30h command input cycle (after the address information has been latched). The device will be in Busy state during this transfer period. After the transfer period the device returns to Ready state. Serial data can be output synchronously with the RE clock from the start address designated in the address input cycle. Figure 3. Read mode (1) operation Random Column Address Change in Read Cycle CLE CE WE ALE RE Busy RY / BY Col. M I/O 00H 30H Col. M Page N Start-address input M Select page N M M+1 M+2 M+3 Page N Start from Col. M 05H E0H Col. M’ M’ M’+1 M’+2 M’+3 M’+4 Page N Start from Col. M’ M’ Cell array In the serial data out from the register, the column address can be changed by inputting the column address with 05h and E0h commands. The data are read out in serial from the column address which is input to the device by 05h and E0h commands with /RE clock. Figure 4. Random Column Address Change in Serial Read 2003-05-19A 18/32 TH58NVG1S3AFT05 Auto Page Program Operation The device carries out an Automatic Page Program operation when it receives a "10H" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.) CLE /CE /WE ALE RE RY / BY I/O 80H Din Din Din Col. M 10h Status Out 70h Data Page P Data input Program Din Reading & verification Selected page The data is transferred (programmed) from the register to the selected page on the rising edge of WE following input of the “ 10H command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Figure 7. Auto Page Program operation Auto Block Erase The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “DOH” which follows the Erase Setup command "60H". This three-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. 60 D0 Block Address input : 3 cycles RY / BY 70 Status Read command Erase Start command I/O Pass Fail Busy 2003-05-19A 19/32 TH58NVG1S3AFT05 ID Read The device contains ID code which identify the device type, the manufacturer, and some features of the device. The ID codes can be read out under the following timing conditions: CLE tCEA CE WE tALEA ALE RE tREAID 00H 90H I/O ID Read command Address 00 98H Maker code Note1 DAH Note2 Note3 Device code Note1 : 81H or 01H Note2 : 95H or 15H Note3 : 44H or C4H For the specifications of the access times tREAID and tALEA refer to the AC Characteristics. Figure 13. ID Read timing Table 6. Code table Descripton I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data st Maker Code 1 0 0 1 1 0 0 0 98H nd Device Code 1 1 0 1 1 0 1 0 DAH Chip Number, Cell Type, PGM Page, Write Cache 0 or 1 0 0 0 0 0 0 1 81H or 01H Page Size, Block Size, 0 or 1 Redundant Size, Organization 0 0 1 0 1 0 1 95H or 15H 1 0 0 0 1 0 0 44H or C4H I/O8 I/O7 I/O6 I/O5 I/O4 1 Data 2 Data rd 3 Data th 4 Data th 5 Data Plane Number, Plane Size 0 or 1 3rd Data Descripton Internal Chip Number Cell Type Number of simultaneously programmed pages I/O2 I/O1 1 0 0 2 0 1 4 1 0 8 1 1 2 level cell 0 0 4 level cell 0 1 8 level cell 1 0 16 level cell 1 1 1 2 0 0 0 1 4 1 0 1 1 8 Reserved 1 Reserved 2 I/O3 0 0 or 1 2003-05-19A 20/32 TH58NVG1S3AFT05 4th Data Descripton I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 1KB 0 0 Page Size 2KB 0 1 (without redundant area) 4KB 1 0 8KB 1 1 I/O2 I/O1 0 0 Block Size (without redundant area) Redundant area size (byte/512byte) 64KB 0 0 128KB 0 1 256KB 1 0 512KB 1 1 8 16 0 0 1 Reserved 1 0 Reserved 1 1 I/O4 I/O3 X8 Organization 0 0 X16 Reserved 1 0 or 1 5th Data Descripton Plane Number I/O8 I/O6 I/O5 1 0 0 2 0 1 4 1 0 8 1 1 64Mb 0 0 0 128Mb 0 0 1 256Mb 0 1 0 512Mb 0 1 1 1Gb 2Gb 1 0 0 1 0 1 4Gb 1 1 0 1 1 1 Plane Size 8Gb Reserved I/O7 0 or 1 2003-05-19A 21/32 TH58NVG1S3AFT05 Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass /fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the I/O port on the RE clock after a “70H" command input. The resulting information is outlined in Table 5. Table 5. Status output table STATUS OUTPUT I/O1 Chip Status 1 Pass: 0 Fail: 1 I/O2 Chip Status 2 Pass: 0 Fail: 1 I/O3 Not Used 0 I/O4 Not Used 0 I/O5 Not Used 0 I/O6 Ready/Busy Ready: 1 Busy: 0 I/O7 Data Cache Busy Ready: 1 Busy: 0 I/O8 Write Protect Protect: 0 Not Protected: 1 The Pass/Fail status on I/O1 and I/O2 is only valid when the device is in the Ready state. An application example with multiple devices is shown in Figure 6. CE1 CE2 CE3 CEN CEN 1 CLE ALE WE Device 1 Device 2 Device 3 Device N Device N1 RE I/O1 to I/O8 RY / BY Busy RY / BY CLE ALE WE CE1 CEN RE I/O 70H 70H Status on Device 1 Status on Device N Figure 6. Status Read timing application example System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. 2003-05-19A 22/32 TH58NVG1S3AFT05 Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an "FFH" Reset command input during the various device operations is as follows: When a Reset (FFH) command is input during programming 80 10 FF 00 Internal VPP RY / BY tRST (max 10 Ps) Figure 8. When a Reset (FFH) command is input during erasing D0 Internal voltage FF 00 erase RY / BY tRST (max 500 Ps) Figure 9. When a Reset (FFH) command is input during Read operation 00 FF 00 30 RY / BY Figure 10. t RST (max 6 Ps) When a Status Read command (70H) is input after a Reset FF 70 I/O status : Pass/Fail o Pass : Ready/Busy o Ready RY / BY When two or more Reset commands are input in succession 10 (1) (2) (3) FF FF FF RY / BY The second FF command is invalid, but the third FF command is valid. Figure 12. 2003-05-19A 23/32 TH58NVG1S3AFT05 APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence: The timing sequence shown in Figure 15 is necessary for power-on/off sequence. The device internal initialization start after the power supply reaches appropriate level in power on sequence. During the initialization the device Ready/Busy signal outputs Busy state as shown in the Figure-15. In this time period, the acceptable commands are FFh or 70h. The WP signal is useful for protecting against data corruption at power-on/off. 2.7V 2.5V 0V VCC don’t care don’t care CE , WE , RE CLE, ALE WP VIH VIL VIL 1ms max Operation 100µs max invalid don’t care Ready/Busy Figure 15. Power-on/off Sequence (2) Status after power-on The following sequence is necessary because some input signals may not be stable at power-on. Power on FF Reset Figure 16. (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of command while Busy state During Busy state, do not input any command except 70H, and FFH. 2003-05-19A 24/32 TH58NVG1S3AFT05 (5) Acceptable commands after Serial Input command "80H" Once the Serial Input command "80H" has been input, do not input any command other than the Column Address Change in Auto Program command "10H” or the Reset command "FFH". 80 FF WE Address input RY / BY If a command other than "10H" or "FFH" is input, the Program operation is not performed and the device operation is set to the mode which the input command specifies.. 80 XX 10 Mode specified by the command. Programming cannot be executed. Command other than "10H" or “FFH” (6) Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random page address programming is prohibited. From the LSB page to MSB page DATA IN: Data (1) Ex.) Random page program (Prohibition) Data (64) DATA IN: Data (1) Data register Data (64) Data register Page 0 (1) Page 0 (2) Page 1 Page 2 (2) (32) (3) Page 1 Page 2 Page 31 (32) Page 31 (1) Page 63 (64) Page 63 (64) (3) Figure 17. page programming within a block 2003-05-19A 25/32 TH58NVG1S3AFT05 (7) Status Read during a Read operation 00 comma 00 30 [A] 70 CE WE RY/BY RE Address N Status Read command input Status output Status Read Figure 18. The device status can be read out by inputting the Status Read command “70H” in Read mode. Once the device has been set to Status Read mode by a “70H” command, the device will not return to Read mode. Therefore, a Status Read during a Read operation is prohibited. However, when the Read command “00H” is input during [A], Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary (8) Auto programming failure Fail 80 10 Address M I/O 70 80 10 Address N Data input Data input 80 If the programming result for page address M is Fail, do not try to program the page to address N in another block without the data input sequence. Because the previous input data has been lost, the same input sequence of 80H command, address and data is necessary. 10 M N Figure 19. (9) RY / BY : termination for the Ready/Busy pin ( RY / BY ) A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain circuit. VCC VCC Ready 3.0 V VCC R Device 3.0 V 1.0 V 1.0 V Busy RY / BY tf tr 1.5 Ps VCC 3.3 V Ta 25°C CL 100 pF CL VSS tf tr This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. 1.0 Ps 15 ns 10 ns tf tr 0.5 Ps Figure 20. 0 5 ns 1 K: 2 K: 3 K: 4 K: R 2003-05-19A 26/32 TH58NVG1S3AFT05 (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN 80 10 WP RY / BY tWW (100 ns MIN) Disable Programming WE DIN 80 10 WP RY / BY tWW (100 ns MIN) Enable Erasing WE DIN 60 D0 WP RY / BY tWW (100 ns MIN) Disable Erasing WE DIN 60 D0 WP RY / BY tWW (100 ns MIN) 2003-05-19A 27/32 TH58NVG1S3AFT05 (11) When six address cycles are input Although the device may read in sixth address, it is ignored inside the chip. Read operation CLE CE WE ALE I/O 30H 00H ignored Address input RY / BY Figure 22. Program operation CLE CE WE ALE I/O 80H ignored Address input Data input Figure 23. 2003-05-19A 28/32 TH58NVG1S3AFT05 (12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 8 segments as follows :Data area (column address 0 to 2047) : 512 bytes x 4 segments 1st segment: column address 0 to 511 2nd segment: column address 512 to 1023 3rd segment: column address 1024 to 1535 4th segment: column address 1536 to 2047 Redundant area (column address 2048 to 2111) : 16 bytes x 4 segments 1st segment: column address 2048 to 2063 2nd segment: column address 2064 to 2079 3rd segment: column address 2080 to 2095 4th segment: column address 2096 to 2111 . Each segment can be programmed individually as follows: 1st programming 2nd programming Data Pattern 1 All 1s 8th programming Result All 1s All 1s Data Pattern 2 All 1s Data Pattern 1 Data Pattern 2 Data Pattern 8 Data Pattern 8 Figure 24. Note: The input data for unprogrammed or previously programmed page segments must be "1" (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”). 2003-05-19A 29/32 TH58NVG1S3AFT05 (13) Invalid blocks (bad blocks) The device occasionally contains unusable blocks. Therefore, the following issues must be recognized: At the time of shipment, all data bytes in a valid block are FFH. For bad blocks, all bytes are not in the FFH state. Please don’t perform erase operation to bad blocks. Bad Block Bad Block Check if the device has any bad blocks after installation into the system. Figure 27 shows the test flow for bad block detection. Bad blocks which are detected by the test flow must be managed as unusable blocks by the system. A bad block does not affect the performance of good blocks because it is isolated from the bit line by the select gate The number of valid blocks at the time of shipment is as follows: Figure 26. Valid (Good) Block Number MIN TYP. MAX UNIT 2008 - 2048 Block Bad Block Test Flow Start Block No Read Check : Read the 1st page or the 2nd page of each block. If the column address 0 or 2048 of the 1st page or the 2nd page is not FF (Hex), define the block as a bad block. 1 Fail Read Check Pass Block No. Block No. 1 Bad Block *1 No Block No. 2048 Yes End *1 : No erase operation is allowed to detected bad blocks Figure 27. 2003-05-19A 30/32 TH58NVG1S3AFT05 (14) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENIE Block Erase Failure Status Read after Erase o Block Replacement Page Programming Failure Status Read after Program o Block Replacement Programming Failure (1) Block Verify after Program o Retry Single Bit “1 to 0“ (2) ECC x ECC : Error Correction Code . x Block Replacement Program Error occurs Buffer memory Block A When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A ( by creating a bad block table or by using another appropriate scheme). Block B Figure 28. Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. 2003-05-19A 31/32 TH58NVG1S3AFT05 Package Dimensions Weight: 0.53 g (typ.) 2003-05-19A 32/32