Cypress CYDC128B16-55AXI 1.8 v 4 k/8 k/16 k ã 16 and 8 k/16 k ã 8 consumobl dual-port static ram Datasheet

CYDC128B16
1.8 V 4 K/8 K/16 K × 16 and 8 K/16 K × 8
ConsuMoBL Dual-Port Static RAM
Features
■
True dual-ported memory cells which allow simultaneous
access of the same memory location
■
Full asynchronous operation
■
4/8/16 K × 16 and 8/16 K × 8 organization
■
Pin select for master or slave
■
High speed access: 40 ns
■
Expandable data bus to 32 bits with master/slave chip select
when using more than one device
■
Ultra low operating power
❐ Active: ICC = 15 mA (typical) at 55 ns
❐ Active: ICC = 25 mA (typical) at 40 ns
❐ Standby: ISB3 = 2 μA (typical)
■
On-chip arbitration logic
■
On-chip semaphore logic
■
Input read registers (IRR) and output drive registers (ODR)
■
Port-independent 1.8 V, 2.5 V, and 3.0 V I/Os
■
INT flag for port-to-port communication
■
Pb-free 14 × 14 × 1.4 mm 100-pin Thin Quad Flat Pack (TQFP)
Package
■
Separate upper byte and lower byte control
■
Commercial and industrial temperature ranges
Selection Guide for VCC = 1.8 V
Description
Port I/O Voltages (P1-P2)
CYDC128B16
–40
CYDC128B16
–55
1.8 V-1.8 V
1.8 V-1.8 V
Unit
Maximum Access Time
40
55
ns
Typical Operating Current
25
15
mA
Typical Standby Current for ISB1
2
2
μA
Typical Standby Current for ISB3
2
2
μA
CYDC128B16
–40
CYDC128B16
–55
Unit
2.5 V-2.5 V
2.5 V-2.5 V
Selection Guide for VCC = 2.5 V
Description
Port I/O Voltages (P1-P2)
Maximum Access Time
40
55
ns
Typical Operating Current
39
28
mA
Typical Standby Current for ISB1
6
6
μA
Typical Standby Current for ISB3
4
4
μA
CYDC128B16
–40
CYDC128B16
–55
Unit
3.0 V-3.0 V
3.0 V-3.0 V
Selection Guide for VCC = 3.0 V
Description
Port I/O Voltages (P1-P2)
Maximum Access Time
40
55
ns
Typical Operating Current
49
42
mA
Typical Standby Current for ISB1
7
7
μA
Typical Standby Current for ISB3
6
6
μA
Cypress Semiconductor Corporation
Document #: 001-01638 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
408-943-2600
Revised March 1, 2011
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CYDC128B16
Top Level Block Diagram[1, 2]
I/O[15:0]R
I/O[15:0]L
UBR
UBL
LBL
LBR
IO
Control
IO
Control
16K X 16
Dual Ported Array
Address Decode
Address Decode
A[13:0]L
CE L
A [13:0]R
CE R
Interrupt
Arbitration
Semaphore
OE L
R/W L
SEML
BUSY L
INTL
Mailboxes
INTR
CEL
OEL
R/WL
OE R
R/W R
SEMR
BUSY R
M/S
Input Read
Register and
Output Drive
Register
IRR0 ,IRR1
CE R
OE R
R/W R
ODR0 - ODR4
SFEN
Notes
1. A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices.
2. BUSY is an output in master mode and an input in slave mode.
Document #: 001-01638 Rev. *H
Page 2 of 29
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CYDC128B16
Contents
Features ...............................................................................1
Selection Guide for VCC = 1.8 V .........................................1
Selection Guide for VCC = 2.5 V ........................................1
Selection Guide for VCC = 3.0 V 1
Top Level Block Diagram....................................................2
Pin Configurations .............................................................4
Pin Definitions ....................................................................5
Functional Description .......................................................6
Power Supply ................................................................6
Write Operation .............................................................6
Read Operation .............................................................6
Interrupts .......................................................................6
Busy ..............................................................................6
Master/Slave .................................................................6
Input Read Register ......................................................7
Output Drive Register ....................................................7
Semaphore Operation ...................................................7
Architecture ........................................................................8
Maximum Ratings .............................................................10
Operating Range ...............................................................10
Electrical Characteristics for VCC = 1.8 V
Over the Operating Range ...............................................10
Document #: 001-01638 Rev. *H
Electrical Characteristics for VCC = 2.5 V
Over the Operating Range ...............................................12
Electrical Characteristics for 3.0 V
Over the Operating Range ...............................................13
Capacitance ......................................................................13
Switching Characteristics for VCC = 1.8V ......................14
Switching Characteristics for VCC = 2.5 V
Over the Operating Range .................................................16
Switching Characteristics for VCC = 3.0 V
Over the Operating Range .................................................17
Switching Waveforms ......................................................19
CEL Valid First .............................................................23
Left Address Valid First ..............................................23
Ordering Information ........................................................25
8k x16 1.8V Asynchronous Dual-Port SRAM ..............25
Ordering Code Defintions ............................................25
Package Diagram ..............................................................26
Acronyms ..........................................................................27
Document History Page ...................................................28
Sales, Solutions, and Legal Information ........................29
Worldwide Sales and Design Support .........................29
Products ......................................................................29
PSoC Solutions ...........................................................29
Page 3 of 29
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CYDC128B16
Pin Configurations
A3R
A2R
A1R
A0R
UBR
LBR
OER
R/WR
VSS
ODR4
ODR3
ODR2
VSS
ODR1
ODR0
VSS
SFEN
R/WL
OEL
LBL
UBL
A0L
A1L
A2L
A3L
Figure 1. 100-Pin TQFP (Top View) [3]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A4L
1
75
A4R
A5L
2
74
A5R
A6L
3
73
A6R
A7L
4
72
A7R
A8L
5
71
A8R
CEL
6
70
CER
SEML
7
69
SEMR
INTL
8
68
INTR
BUSYL
9
67
BUSYR
A9L
10
66
A9R
A10L
11
65
A10R
VSS
12
64
VSS
VCC
13
63
VCC
A11L
14
62
A11R
A12L[3]
15
61
A12R[3]
IRR0[5]
16
60
IRR1[6]
M/S
17
59
NC[7]
VDDIOL
18
58
VDDIOR
I/O0L
19
57
I/O15R
I/O1L
20
56
I/O14R
I/O2L
21
55
I/O13R
VSS
22
54
VSS
I/O3L
23
53
I/O12R
I/O4L
24
52
I/O11R
I/O5L
25
51
I/O10R
CYDC128B16
I/O9R
I/O8R
VDDIOR
I/O7R
I/O6R
I/O5R
VSS
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
NC[7]
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
VSS
I/O10L
I/O9L
I/O8L
VDDIOL
I/O7L
I/O6L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes
3. Leave this pin unconnected. No trace or power component can be connected to this pin.
Document #: 001-01638 Rev. *H
Page 4 of 29
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CYDC128B16
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip enable
R/WL
R/WR
Read/write enable
OEL
OER
Output enable
A0L–A13L
A0R–A13R
Address (A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices).
I/O0L–I/O15L
I/O0R–I/O15R
Data bus input/output for x16 devices; I/O0–I/O7 for x8 devices.
SEML
SEMR
Semaphore enable
UBL
UBR
Upper byte select (I/O8–I/O15 for x16 devices; Not applicable for x8 devices).
LBL
LBR
Lower byte select (I/O0–I/O7 for x16 devices; Not applicable for x8 devices).
INTL
INTR
Interrupt flag
BUSYR
Busy flag
BUSYL
IRR0, IRR1
ODR0-ODR4
Input read register (IRR) for CYDC128B16.
Output drive register; these outputs are Open Drain.
SFEN
Special function enable
M/S
Master or slave select
VCC
Core power
GND
Ground
VDDIOL
VDDIOR
NC
Document #: 001-01638 Rev. *H
Left port I/O voltage
Right port I/O voltage
No connect. Leave this pin unconnected.
Page 5 of 29
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CYDC128B16
Functional Description
The CYDC128B16 is a low power complementary metal oxide
semiconductor (CMOS) 4k, 8k,16k x 16, and 8/16k x 8 dual-port
static RAM. Arbitration schemes are included on the devices to
handle situations when multiple processors access the same
piece of data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be used as standalone 16-bit dual-port
static RAMs or multiple devices can be combined in order to
function as a 32-bit or wider master/slave dual-port static RAM.
An M/S pin is provided for implementing 32-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Enable (CE) pin.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must
also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (1FFF for the
CYDC128B16) is the mailbox for the right port and the second
highest memory location (1FFE for the CYDC128B16) is the
mailbox for the left port. When one port writes to the other port’s
mailbox, an interrupt is generated to the owner. The interrupt is
reset when the owner reads the contents of the mailbox. The
message is user-defined.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin. On power up, an initialization program should be run
and the interrupts for both ports must be read to reset them.
The operation of the interrupts and their interaction with Busy are
summarized in Table 2.
The CYDC128B16 are available in 100-pin TQFP packages.
Busy
Power Supply
Each port can operate on independent I/O voltages. This is
determined by what is connected to the VDDIOL and VDDIOR pins.
The supported I/O standards are 1.8-V/2.5-V LVCMOS and
3.0-V LVTTL.
The CYDC128B16 provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of
each other, the busy logic determines which port has access. If
tPS is violated, one port will definitely gain permission to the
location, but it is not predictable which port gets that permission.
BUSY will be asserted tBLA after an address match or tBLC after
CE is taken LOW.
Write Operation
Master/Slave
Data must be set up for a duration of tSD before the rising edge
of R/W to guarantee a valid write. A write operation is controlled
by either the R/W pin (see Figure 6 on page 20) or the CE pin
(see Figure 7 on page 20). Required inputs for non-contention
operations are summarized in Table 1.
A M/S pin is provided to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This will
allow the device to interface to a master device with no external
components. Writing to slave devices must be delayed until after
the BUSY input has settled (tBLC or tBLA), otherwise, the slave
chip may begin a write cycle during a contention situation. When
tied HIGH, the M/S pin allows the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
The core voltage (VCC) can be 1.8 V, 2.5 V or 3.0 V, as long as
it is lower than or equal to the I/O voltage.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must occur before the data is read on the output; otherwise the
data read is not deterministic. Data will be valid on the port tDDD
after the data is presented on the other port.
Document #: 001-01638 Rev. *H
Page 6 of 29
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CYDC128B16
Input Read Register
The Input Read Register (IRR) captures the status of two
external input devices that are connected to the Input Read pins.
The contents of the IRR read from address x0000 from either
port. During reads from the IRR, DQ0 and DQ1 are valid bits and
DQ<15:2> are don’t care. Writes to address x0000 are not
allowed from either port.
Address x0000 is not available for standard memory accesses
when SFEN = VIL. When SFEN = VIH, address x0000 is available
for memory accesses.
The inputs will be 1.8-V/2.5-V LVCMOS or 3.0-V LVTTL,
depending on the core voltage supply (VCC). Refer to Table 3 for
Input Read Register operation.
Output Drive Register
The Output Drive Register (ODR) determines the state of up to
five external binary state devices by providing a path to VSS for
the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages
(1.5 V ≤ VDDIO ≤ 3.5 V) but the combined current cannot exceed
40 mA (8 mA max for each external device). The status of the
ODR bits are set using standard write accesses from either port
to address x0001 with a “1” corresponding to on and “0” corresponding to off.
The status of the ODR bits can be read with a standard read
access to address x0001. When SFEN = VIL, the ODR is active
and address x0001 is not available for memory accesses. When
SFEN = VIH, the ODR is inactive and address x0001 can be used
for standard accesses.
During reads and writes to ODR DQ<4:0> are valid and
DQ<15:5> are don’t care. Refer to Table 4 for Output Drive
Register operation.
Semaphore Operation
The CYDC128B16 provides eight semaphore latches that are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two ports.
The state of the semaphore indicates that a resource is in use.
Document #: 001-01638 Rev. *H
For example, if the left port wants to request a given resource, it
sets a latch by writing a zero to a semaphore location. The left
port then verifies its success in setting the latch by reading it.
After writing to the semaphore, SEM or OE must be deasserted
for tSOP before attempting to read the semaphore. The
semaphore value will be available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side
succeeds in gaining control of the semaphore. If the left side no
longer requires the semaphore, a one is written to cancel its
request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore will be set to
one for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
left port released it. Table 5 shows sample semaphore operations.
When reading a semaphore, all 16/8 data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side controls the semaphore. On power up,
both ports should write “1” to all eight semaphores.
Page 7 of 29
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CYDC128B16
Architecture
port-to-port communication. Two Semaphore (SEM) control pins
are used for allocating shared resources. With the M/S pin, the
device can function as a master (BUSY pins are outputs) or as a
slave (BUSY pins are inputs). The device also has an automatic
power down feature controlled by CE. Each port is provided with
its own output enable control (OE), which allows data to be read
from the device.
The CYDC128B16 consists of an array of 4k, 8k, or 16k words
of 16 dual-port RAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. Two Interrupt (INT) pins can be used for
Table 1. Non-Contending Read/Write
Outputs[1]
Inputs
UB
LB
SEM
I/O8–I/O15
Operation
CE
R/W
OE
I/O0–I/O7
H
X
X
X
X
H
High Z
High Z
Deselected: power down
X
X
X
H
H
H
High Z
High Z
Deselected: power down
L
L
X
L
H
H
Data In
High Z
Write to upper byte only
L
L
X
H
L
H
High Z
Data In
Write to lower byte only
L
L
X
L
L
H
Data In
Data In
Write to both bytes
L
H
L
L
H
H
Data Out
High Z
Read upper byte only
L
H
L
H
L
H
High Z
Data Out
Read lower byte only
L
H
L
L
L
H
Data Out
Data Out
Read both bytes
X
X
H
X
X
X
High Z
High Z
Outputs disabled
H
H
L
X
X
L
Data Out
Data Out
Read data in semaphore flag
X
H
L
H
H
L
Data Out
Data Out
Read data in semaphore flag
H
X
X
X
L
Data In
Data In
Write DIN0 into semaphore flag
X
X
H
H
L
Data In
Data In
Write DIN0 into semaphore flag
L
X
X
L
X
L
Not allowed
L
X
X
X
L
L
Not allowed
1. This column applies to x16 devices only.
Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[1]
Function
Set right INTR flag
Left Port
R/WL
L
CEL
L
Right Port
OEL
A0L–13L
INTL
R/WR
CER
OER
A0R–13R
INTR
X
3FFF[2]
X
X
X
X
X
L[3]
[2]
H[4]
Reset right INTR flag
X
X
X
X
X
X
L
L
3FFF
Set left INTL flag
X
X
X
X
L[4]
L
L
X
3FFE[2]
X
[3]
X
X
X
X
X
Reset left INTL flag
1.
2.
3.
4.
X
L
L
[2]
3FFE
H
See Interrupts Functional Description for specific highest memory locations by device.
See Functional Description for specific addresses by device.
If BUSYL = L, then no change.
If BUSYR = L, then no change.
Document #: 001-01638 Rev. *H
Page 8 of 29
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CYDC128B16
Table 3. Input Read Register Operation[1, 2]
SFEN
H
L
1.
2.
3.
4.
CE
L
L
R/W
OE
H
UB
L
H
LB
L
L
ADDR
L
X
I/O0–I/O1 I/O2–I/O15
[3]
VALID[3]
[4]
X
x0000-Max VALID
L
x0000
VALID
Mode
Standard memory access
IRR read
SFEN = VIL for IRR reads.
SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH.
UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid.
LB must be active (LB = VIL) for these bits to be valid.
Table 4. Output Drive Register [1]
SFEN
CE
R/W
OE
UB
LB
[2]
[3]
[3]
H
L
H
L
L
L
L
L
H
X
L
X
X
L
X
ADDR
I/O0–I/O4 I/O5–I/O15
Mode
[3]
[3]
x0000-Max VALID
VALID
Standard memory access
L
L
L
x0001
VALID[4]
X
ODR write[1, 3]
x0001
VALID[4]
X
ODR read[1]
1. SFEN = VIL for ODR reads and writes.
2. Output enable must be low (OE = VIL) during reads for valid data to be output.
3. During ODR writes data will also be written to the memory.
Table 5. Semaphore Operation Example
Function
I/O0–I/O15 Left I/O0–I/O15 Right
Status
No action
1
1
Semaphore-free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore-free
Document #: 001-01638 Rev. *H
Page 9 of 29
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CYDC128B16
Maximum Ratings
Output current into outputs (LOW) .............................. 90 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.[4]
Storage temperature .................................. –65°C to +150°C
Ambient temperature with
power applied ............................................. –55°C to +125°C
Supply voltage to ground potential ...............–0.5 V to +3.3 V
DC voltage applied to
outputs in High-Z State ........................ –0.5 V to VCC + 0.5 V
Static discharge voltage.......................................... > 2000 V
Latch up current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
1.8 V ± 100 mV
2.5 V ± 100 mV
3.0 V ± 300 mV
–40°C to +85°C
1.8 V ± 100 mV
2.5 V ± 100 mV
3.0 V ± 300 mV
Commercial
Industrial
DC input voltage[5] ............................... –0.5 V to VCC + 0.5 V
Electrical Characteristics for VCC = 1.8 V
Parameter
VOL
VOL ODR
CYDC128B16
CYDC128B16
-40
-55
Description
P1 I/O
Voltage
VOH
Over the Operating Range
P2 I/O
Voltage
Min
VIL
IOZ
ICEX ODR
Max
Min
Unit
Typ
Max
Output HIGH voltage
(IOH = –100 μA)
1.8 V (any port)
VDDIO – 0.2
VDDIO – 0.2
V
Output HIGH voltage
(IOH = –2 mA)
2.5 V (any port)
2.0
2.0
V
Output HIGH voltage
(IOH = –2 mA)
3.0 V (any port)
2.1
2.1
V
Output LOW voltage
(IOL = 100 μA)
1.8 V (any port)
0.2
0.2
V
Output HIGH voltage
(IOL = 2 mA)
2.5 V (any port)
0.4
0.4
V
Output HIGH voltage
(IOL = 2 mA)
3.0 V (any port)
0.4
0.4
V
ODR Output LOW voltage|
(IOL = 8 mA)
1.8 V (any port)
0.2
0.2
V
2.5 V (any port)
0.2
0.2
V
3.0 V (any port)
VIH
Typ
Input HIGH voltage
Input LOW voltage
Output leakage current
ODR output leakage current.
VOUT = VDDIO
0.2
V
1.8 V (any port)
1.2
VDDIO + 0.2
1.2
VDDIO + 0.2
V
2.5 V (any port)
1.7
VDDIO + 0.3
1.7
VDDIO + 0.3
V
3.0 V (any port)
2.0
VDDIO + 0.2
2.0
VDDIO + 0.2
V
1.8 V (any port)
–0.2
0.4
–0.2
0.4
V
2.5 V (any port)
–0.3
0.6
–0.3
0.6
V
3.0 V (any port)
–0.2
0.7
–0.2
0.7
V
–1
1
–1
1
μA
1.8 V
1.8 V
0.2
2.5 V
2.5 V
–1
1
–1
1
μA
3.0 V
3.0 V
–1
1
–1
1
μA
1.8 V
1.8 V
–1
1
–1
1
μA
2.5 V
2.5 V
–1
1
–1
1
μA
3.0 V
3.0 V
–1
1
–1
1
μA
Notes
4. The voltage on any input or I/O pin can not exceed the power pin during power-up.
5. Pulse width < 20 ns.
Document #: 001-01638 Rev. *H
Page 10 of 29
[+] Feedback
CYDC128B16
Electrical Characteristics for VCC = 1.8 V (continued) Over the Operating Range
Parameter
IIX
Description
Input leakage current
P1 I/O
Voltage
P2 I/O
Voltage
Min
1.8 V
1.8 V
2.5 V
2.5 V
–1
CYDC128B16
CYDC128B16
-40
-55
Typ
Unit
Max
Min
Typ
Max
–1
1
–1
1
μA
–1
1
–1
1
μA
1
–1
3.0 V
3.0 V
1
μA
ICC
Operating current (VCC Industrial
= Max, IOUT = 0 mA)
Outputs Disabled
1.8 V
1.8 V
25
40
15
25
mA
ISB1
Standby current (both
Ports TTL Level) CEL
and CER ≥ VCC – 0.2,
SEML = SEMR = VCC –
0.2, f = fMAX
Industrial
1.8 V
1.8 V
2
6
2
6
μA
ISB2
Standby current (one
port TTL level) CEL |
CER ≥ VIH, f = fMAX
Industrial
1.8 V
1.8 V
8.5
18
8.5
14
mA
ISB3
Standby current (both
Industrial
ports CMOS level) CEL
and CER ≥ VCC − 0.2V,
SEML and SEMR > VCC
– 0.2V, f = 0
1.8 V
1.8 V
2
6
2
6
μA
ISB4
Standby current (one
Industrial
port CMOS level) CEL |
[1]
CER ≥ VIH, f = fMAX
1.8 V
1.8 V
8.5
18
8.5
14
mA
1. MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
Document #: 001-01638 Rev. *H
Page 11 of 29
[+] Feedback
CYDC128B16
Electrical Characteristics for VCC = 2.5 V Over the Operating Range
Parameter
VOL
VOL ODR
VIH
VIL
IOZ
ICEX ODR
IIX
CYDC128B16
-40
-55
Description
P1 I/O
Voltage
VOH
CYDC128B16
P2 I/O
Voltage
Min
Typ
Max
Min
Typ
Unit
Max
Output HIGH voltage (IOH = –2 mA)
2.5 V (any port)
2.0
2.0
V
Output HIGH voltage (IOH = –2 mA)
3.0 V (any port)
2.1
2.1
V
Output LOW voltage (IOL = 2 mA)
2.5 V (any port)
0.4
0.4
Output LOW voltage (IOL = 2 mA)
3.0 V (any port)
0.4
0.4
V
ODR Output LOW voltage (IOL = 8 mA)
2.5 V (any port)
0.2
0.2
V
3.0 V (any port)
0.2
0.2
V
V
Input HIGH voltage
Input LOW voltage
Output leakage current
ODR output leakage current. VOUT = VCC
Input leakage current
V
2.5 V (any port)
1.7
VDDIO + 0.3
1.7
VDDIO + 0.3
3.0 V (any port)
2.0
VDDIO + 0.2
2.0
VDDIO + 0.2
V
2.5 V (any port)
–0.3
0.6
–0.3
0.6
V
3.0 V (any port)
–0.2
0.7
–0.2
0.7
V
2.5 V
2.5 V
–1
1
–1
1
μA
3.0 V
3.0 V
–1
1
–1
1
μA
2.5 V
2.5 V
–1
1
–1
1
μA
3.0 V
3.0 V
–1
1
–1
1
μA
2.5 V
2.5 V
–1
1
–1
1
μA
3.0 V
3.0 V
–1
1
–1
1
μA
ICC
Operating current (VCC = Max,
IOUT = 0 mA) Outputs disabled
Industrial
2.5 V
2.5 V
39
55
28
40
mA
ISB1
Standby current (both ports TTL Industrial
level) CEL and CER ≥ VCC – 0.2,
SEM L= SEMR = VCC – 0.2,
f=fMAX
2.5 V
2.5 V
6
8
6
8
μA
ISB2
Standby current (one port TTL
level) CEL | CER ≥ VIH, f = fMAX
Industrial
2.5 V
2.5 V
21
30
18
25
mA
ISB3
Standby current (both ports
CMOS level) CEL and CER ≥
VCC − 0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
Industrial
2.5 V
2.5 V
4
6
4
6
μA
ISB4
Standby current (one port CMOS Industrial
level) CEL | CER ≥ VIH, f = fMAX[1]
2.5 V
2.5 V
21
30
18
25
mA
1. MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
ISB3.
Document #: 001-01638 Rev. *H
Page 12 of 29
[+] Feedback
CYDC128B16
]
Electrical Characteristics for 3.0 V Over the Operating Range
Parameter
CYDC128B16
CYDC128B16
-40
-55
Description
VOH
Output HIGH voltage (IOH = –2 mA)
P1 I/O
P2 I/O
Voltage Voltage
Min
3.0 V (any port)
2.1
Typ
Max
Min
Typ
Unit
Max
2.1
V
VOL
Output LOW voltage (IOL = 2 mA)
3.0 V (any port)
0.4
0.4
V
VOL ODR
ODR output LOW voltage (IOL = 8 mA)
3.0 V (any port)
0.2
0.2
V
VIH
Input HIGH voltage
3.0 V (any port)
2.0
VDDIO
+ 0.2
2.0
VDDIO
+ 0.2
V
VIL
Input LOW voltage
3.0 V (any port)
IOZ
Output leakage current
3.0 V
–0.2
0.7
–0.2
0.7
V
3.0 V
–1
1
–1
1
μA
ICEX ODR
ODR output leakage current. VOUT = VCC
3.0 V
3.0 V
–1
1
–1
1
μA
IIX
Input leakage current
3.0V
3.0 V
–1
1
–1
1
μA
ICC
Operating current (VCC = Max, Industrial
IOUT = 0 mA) Outputs disabled
3.0V
3.0 V
49
70
42
60
mA
ISB1
Standby current (both ports TTL Industrial
Level) CEL and CER ≥ VCC –
0.2, SEML = SEMR = VCC – 0.2,
f = fMAX
3.0 V
3.0 V
7
10
7
10
μA
ISB2
Standby current (one port TTL Industrial
Level) CEL | CER ≥ VIH, f = fMAX
3.0 V
3.0 V
28
40
25
35
mA
ISB3
Standby current (both ports
Industrial
CMOS Level) CEL and CER ≥
VCC − 0.2V, SEML and SEMR >
VCC – 0.2V, f = 0
3.0 V
3.0 V
6
8
6
8
μA
ISB4
Standby current (one port
Industrial
CMOS Level) CEL | CER ≥ VIH,
f = fMAX[1]
3.0 V
3.0 V
28
40
25
35
mA
1. MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs
at CMOS level standby ISB3.
Capacitance
Parameter[1]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.0V
Max
Unit
9
pF
10
pF
1. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-01638 Rev. *H
Page 13 of 29
[+] Feedback
CYDC128B16
7
Figure 2. AC Test Loads and Waveforms
3.0 V/2.5 V/1.8 V
3.0V/2.5V/1.8V
R1
RTH = 6 kΩ
OUTPUT
OUTPUT
R1
OUTPUT
C = 30 pF
C = 30 pF
R2
C = 5 pF
R2
VTH = 0.8 V
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
(Used for tLZ, tHZ, tHZWE, and tLZWE
including scope and jig)
ALL INPUT PULSES
3.0V/2.5V
1.8V
R1
1022Ω
13500Ω
1.8V
R2
792Ω
10800Ω
GND
10%
(c) Three-State Delay (Load 2)
90%
10%
90%
≤ 3 ns
≤ 3 ns
Switching Characteristics for VCC = 1.8V
Over the Operating Range[1]
CYDC128B16
Parameter
Description
CYDC128B16
-40
Min
-55
Max
Min
Unit
Max
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
tOHA
Output hold from address change
tACE[2]
CE LOW to data valid
40
55
ns
tDOE
OE LOW to data valid
25
30
ns
tLZOE[3, 4, 5]
OE Low to Low Z
tHZOE[3, 4, 5]
OE HIGH to High Z
25
ns
tLZCE[3, 4, 5]
CE LOW to Low Z
tHZCE[3, 4, 5]
CE HIGH to High Z
tPU
[5]
CE LOW to power up
40
55
40
5
ns
55
5
5
5
15
5
ns
5
15
0
ns
ns
ns
25
0
ns
ns
tPD[5]
CE HIGH to power down
40
55
ns
tABE[2]
Byte enable access time
40
55
ns
Write Cycle
tWC
Write cycle time
40
55
ns
tSCE[2]
CE LOW to write end
30
45
ns
tAW
Address valid to write end
30
45
ns
tHA
Address hold from write end
0
0
ns
tSA[2]
Address setup to write start
0
0
ns
tPWE
Write pulse width
25
40
ns
tSD
Data setup to write end
20
30
ns
tHD
Data hold from write end
0
0
ns
tHZWE[4, 5]
R/W LOW to High Z
Document #: 001-01638 Rev. *H
15
25
ns
Page 14 of 29
[+] Feedback
CYDC128B16
Switching Characteristics for VCC = 1.8V
Over the Operating Range[1] (continued)
Parameter
CYDC128B16
CYDC128B16
-40
-55
Description
Min
Max
Min
Unit
Max
tLZWE[4, 5]
R/W HIGH to Low Z
tWDD[6]
tDDD[6]
Write pulse to data delay
55
80
ns
Write data valid to read data valid
55
80
ns
tBLA
BUSY LOW from address match
30
45
ns
tBHA
BUSY HIGH from address mismatch
30
45
ns
tBLC
BUSY LOW from CE LOW
30
45
ns
tBHC
BUSY HIGH from CE HIGH
tPS[8]
Port setup for priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[9]
BUSY HIGH to data valid
0
0
ns
Busy Timing[7]
30
5
45
ns
5
ns
0
0
ns
20
35
ns
30
40
ns
Interrupt Timing[7]
tINS
INT set time
35
45
ns
tINR
INT reset time
35
45
ns
Semaphore Timing
tSOP
SEM flag update pulse (OE or SEM)
10
15
ns
tSWRD
SEM flag write to read time
10
10
ns
tSPS
SEM flag contention window
10
10
ns
tSAA
SEM address access time
40
55
ns
1. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
2. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
3. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
4. Test conditions used are Load 3.
5. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform.
6. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
7. Test conditions used are Load 2.
8. Add 2ns to this value when the I/O ports are operating at different voltages.
9. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Document #: 001-01638 Rev. *H
Page 15 of 29
[+] Feedback
CYDC128B16
Switching Characteristics for VCC = 2.5 V Over the Operating Range
Parameter
CYDC128B16
CYDC128B16
-40
-55
Description
Min
Max
Min
Unit
Max
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
tOHA
Output hold from address change
tACE[1]
CE LOW to data valid
40
55
ns
tDOE
OE LOW to data valid
25
30
ns
tLZOE[2, 3, 4]
OE LOW to low Z
tHZOE[2, 3, 4]
tLZCE[2, 3, 4]
tHZCE[2, 3, 4]
tPU[4]
tPD[4]
tABE[1]
OE HIGH to high Z
CE LOW to low Z
40
40
5
ns
55
5
2
2
ns
15
2
15
0
ns
ns
2
15
CE HIGH to high Z
CE LOW to power up
55
ns
ns
15
0
ns
ns
CE HIGH to power down
40
55
ns
Byte enable access time
40
55
ns
Write Cycle
tWC
Write cycle time
40
55
ns
tSCE[1]
CE LOW to write end
30
45
ns
tAW
Address valid to write end
30
45
ns
tHA
Address hold from write end
0
0
ns
tSA[1]
Address setup to write start
0
0
ns
tPWE
Write pulse width
25
40
ns
tSD
Data setup to write end
20
30
ns
tHD
Data hold from write end
0
0
ns
tHZWE[3, 4]
tLZWE[3, 4]
tWDD[5]
tDDD[5]
R/W LOW to high Z
R/W HIGH to low Z
15
0
25
0
ns
ns
Write pulse to data delay
55
80
ns
Write data valid to read data valid
55
80
ns
tBLA
BUSY LOW from address match
30
45
ns
tBHA
BUSY HIGH from address mismatch
30
45
ns
tBLC
BUSY LOW from CE LOW
30
45
ns
tBHC
BUSY HIGH from CE HIGH
30
45
ns
tPS[7]
Port set up for priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
Busy Timing[6]
tBDD[8]
BUSY HIGH to data valid
5
5
ns
0
0
ns
20
35
ns
30
40
ns
35
45
ns
[6]
Interrupt Timing
tINS
INT set time
Document #: 001-01638 Rev. *H
Page 16 of 29
[+] Feedback
CYDC128B16
Switching Characteristics for VCC = 2.5 V Over the Operating Range (continued)
Parameter
CYDC128B16
CYDC128B16
-40
-55
Description
Min
Max
INT reset time
tINR
Min
Unit
Max
35
45
ns
Semaphore Timing
tSOP
SEM flag update pulse (OE or SEM)
10
15
ns
tSWRD
SEM flag write to read time
10
10
ns
tSPS
SEM Flag Contention Window
10
tSAA
SEM Address Access Time
1.
2.
3.
4.
5.
6.
7.
8.
10
ns
40
55
ns
To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
Test conditions used are Load 3.
This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform.
For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Test conditions used are Load 2.
Add 2ns to this value when the I/O ports are operating at different voltages.
tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Switching Characteristics for VCC = 3.0 V Over the Operating Range
Parameter
CYDC128B16
CYDC128B16
-40
-55
Description
Min
Max
Min
Unit
Max
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
tOHA
Output hold from address change
tACE[1]
CE LOW to data valid
tDOE
OE LOW to data valid
tLZOE[2, 3, 4]
OE Low to low Z
tHZOE[2, 3, 4]
tLZCE[2, 3, 4]
tHZCE[2, 3, 4]
tPU[4]
tPD[4]
tABE[1]
OE HIGH to high Z
CE LOW to low Z
40
5
ns
55
5
40
25
1
1
55
ns
30
ns
ns
15
1
15
0
ns
ns
1
15
CE HIGH to high Z
CE LOW to power up
55
40
ns
ns
15
0
ns
ns
CE HIGH to power down
40
55
ns
Byte enable access time
40
55
ns
Write Cycle
tWC
Write cycle time
40
55
ns
tSCE[1]
CE LOW to write end
30
45
ns
tAW
Address valid to write end
30
45
ns
tHA
Address hold from write end
0
0
ns
tSA[1]
Address setup to write start
0
0
ns
tPWE
Write pulse width
25
40
ns
tSD
Data setup to write end
20
30
ns
Document #: 001-01638 Rev. *H
Page 17 of 29
[+] Feedback
CYDC128B16
Switching Characteristics for VCC = 3.0 V Over the Operating Range (continued)
Parameter
CYDC128B16
CYDC128B16
-40
-55
Description
Min
Max
0
Min
Unit
Max
tHD
Data hold from write end
tHZWE[3, 4]
R/W LOW to high Z
0
tLZWE[3, 4]
R/W HIGH to low Z
tWDD[5]
tDDD[5]
Write pulse to data delay
55
80
ns
Write data valid to read data valid
55
80
ns
tBLA
BUSY LOW from address match
30
45
ns
tBHA
BUSY HIGH from address mismatch
30
45
ns
tBLC
BUSY LOW from CE LOW
30
45
ns
tBHC
BUSY HIGH from CE HIGH
30
45
ns
tPS[7]
Port set up for priority
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
20
tBDD[8]
BUSY HIGH to data valid
15
0
ns
25
0
ns
ns
Busy Timing[6]
35
ns
30
40
ns
Interrupt Timing[6]
tINS
INT set time
35
45
ns
tINR
INT reset time
35
45
ns
Semaphore Timing
tSOP
SEM flag update pulse (OE or SEM)
10
15
ns
tSWRD
SEM flag write to read time
10
10
ns
tSPS
SEM flag contention window
10
tSAA
SEM address access time
1.
2.
3.
4.
5.
6.
7.
8.
10
40
ns
55
ns
To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
Test conditions used are Load 3.
This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform.
For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Test conditions used are Load 2.
Add 2ns to this value when the I/O ports are operating at different voltages.
tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Document #: 001-01638 Rev. *H
Page 18 of 29
[+] Feedback
CYDC128B16
Switching Waveforms
Figure 3. Read Cycle No.1 (Either Port Address Access)[6, 7, 8]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No.2 (Either Port CE/OE Access)[6, 9, 10]
tACE
CE and
LB or UB
tHZCE
tDOE
OE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Figure 5. Read Cycle No. 3 (Either Port)[6, 8, 11, 12]
tRC
ADDRESS
tAA
tOHA
UB or LB
tHZCE
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes
6. R/W is HIGH for read cycles.
7. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads.
8. OE = VIL.
9. Address valid prior to or coincident with CE transition LOW.
10. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
11. R/W must be HIGH during all address transitions.
12. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
Document #: 001-01638 Rev. *H
Page 19 of 29
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CYDC128B16
Switching Waveforms (continued)
Figure 6. Write Cycle No.1: R/W Controlled Timing[11, 12, 13, 14, 15, 16]
tWC
ADDRESS
tHZOE [17]
OE
tAW
CE
[15, 16]
tPWE[14]
tSA
tHA
R/W
tHZWE[17]
DATA OUT
tLZWE
NOTE 18
NOTE 18
tSD
tHD
DATA IN
Figure 7. Write Cycle No. 2: CE Controlled Timing[11, 12, 13, 18]
tWC
ADDRESS
tAW
CE
[15, 16]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes
13. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
14. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tPWE.
15. To access RAM, CE = VIL, SEM = VIH.
16. To access upper byte, CE = VIL, UB = VIL, SEM = VIH.
To access lower byte, CE = VIL, LB = VIL, SEM = VIH.
17. Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
18. During this period, the I/O pins are in the output state, and input signals must not be applied.
Document #: 001-01638 Rev. *H
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CYDC128B16
Switching Waveforms (continued)
Figure 8. Semaphore Read After Write Timing, Either Side[19, 20]
tSAA
A0–A2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tOHA
tSCE
tSOP
tSD
I/O0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Figure 9. Timing Diagram of Semaphore Contention[21, 22]
A0L–A2L
MATCH
R/WL
SEML
tSPS
A0R–A2R
MATCH
R/WR
SEMR
Notes
19. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
20. CE = HIGH for the duration of the above timing (both write and read cycle).
21. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
22. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 001-01638 Rev. *H
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CYDC128B16
Switching Waveforms (continued)
Figure 10. Timing Diagram of Read with BUSY (M/S=HIGH)[23]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATAOUTL
VALID
tWDD
Figure 11. Write Timing with Busy Input (M/S = LOW)
tPWE
R/W
BUSY
tWB
tWH
Note
23. CEL = CER = LOW.
Document #: 001-01638 Rev. *H
Page 22 of 29
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CYDC128B16
Switching Waveforms (continued)
Figure 12. Busy Timing Diagram No.1 (CE Arbitration)
CEL Valid First[24]
ADDRESSL,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CEL
tBLC
tBHC
BUSYL
Figure 13. Busy Timing Diagram No.2 (Address Arbitration)[24]
Left Address Valid First
tRC or tWC
ADDRESSL
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSYR
Right Address Valid First
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSYL
Note
24. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document #: 001-01638 Rev. *H
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CYDC128B16
Switching Waveforms (continued)
Figure 14. Interrupt Timing Diagrams
Left Side Sets INTR:
ADDRESSL
tWC
WRITE 1FFF (OR 1/3FFF)
tHA[25]
CEL
R/WL
INTR
tINS [26]
Right Side Clears INTR:
tRC
READ 1FFF
(OR 1/3FFF)
ADDRESSR
CER
tINR [26]
R/WR
OER
INTR
Right Side Sets INTL:
tWC
ADDRESSR
WRITE 1FFE (OR 1/3FFE)
tHA[25]
CER
R/WR
INTL
[26]
tINS
Left Side Clears INTL:
tRC
READ 1FFE
OR 1/3FFE)
ADDRESSR
CEL
tINR[26]
R/WL
OEL
INTL
Notes
25. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
26. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 001-01638 Rev. *H
Page 24 of 29
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CYDC128B16
Ordering Information
8k x16 1.8V Asynchronous Dual-Port SRAM
Speed
(ns)
55
Ordering Code
CYDC128B16-55AXI
Package
Name
AZ0AB
Package Type
100-pin Pb-free TQFP
Operating
Range
Industrial
Ordering Code Defintions
Document #: 001-01638 Rev. *H
Page 25 of 29
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CYDC128B16
Package Diagram
Figure 15. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048 *E
Document #: 001-01638 Rev. *H
Page 26 of 29
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CYDC128B16
Acronyms
Acronym
Description
CE
chip enable
CMOS
complementary metal oxide semiconductor
I/O
input/output
IRR
input read registers
ODR
output drive registers
OE
output enable
SEM
semaphore
SRAM
static random access memory
TQDP
thin quad flat pack
WE
write enable
Document #: 001-01638 Rev. *H
Page 27 of 29
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CYDC128B16
Document History Page
Document Title: CYDC128B16 1.8 V 4 K/8 K/16 K × 16 and 8 K/16 K × 8 ConsuMoBL Dual-Port Static RAM
Document Number: 001-01638
Revision
ECN
Submission
Date
Orig. of
Change
Description of Change
**
385185
SEE ECN
YDT
New data sheet
*A
396697
SEE ECN
KGH
Updated ISB2 and ISB4 typo to mA.
Updated tINS and tINR for -55 to 31ns.
*B
404777
SEE ECN
KGH
Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and
VOL
Replaced -35 speed bin with -40
Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V
Included note 34
*C
463014
SEE ECN
HKH
Changed spec title to from “Consumer Dual-Port” to “ConsuMoBL Dual-Port”
Cypress Internet Release
*D
505803
SEE ECN
HKH
Corrected typo in Features and Ordering Info sections.
Cypress external web release.
*E
735537
SEE ECN
HKH
Corrected typo in Pg5 power supply section
Updated tDDD timing value to be consistent with tWDD
*F
2905507
04/06/2010
YDT
Removed parts CYDC064B08-55AXI, CYDC064B16-55AXI. Updated
package diagram.
*G
2930445
05/11/2010
AVF
Updated template.
Removed references to inactive parts from the data sheet.
*H
3183900
02/28/11
ESH
Added ordering code defintions
Document #: 001-01638 Rev. *H
Page 28 of 29
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CYDC128B16
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at Cypress Locations.
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PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
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cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-01638 Rev. *H
Revised March 1, 2011
Page 29 of 29
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