Cypress CY7C9335 Smpte-259m/dvb-asi descrambler/framer-controller Datasheet

CY7C9335
SMPTE-259M/DVB-ASI
Descrambler/Framer-Controller
Features
The inputs of the CY7C9335 are designed to be directly mated
to a CY7B9334 HOTLink receiver, which converts the
SMPTE-259M compatible high-speed serial data stream into
10-bit parallel characters.
• Fully compatible with SMPTE-259M
— SMPTE-125M compliant for 4:2:2 component video
— SMPTE-244M compliant for 4fsc composite video
• Fully compatible with DVB-ASI
• Operates from a single +5V or −5V supply
• 100-pin TQFP package
• Decodes 10-bit parallel digital streams for any rate from
16−40 M characters/sec (160−400 Mbits/sec serial)
• Operates with CY7B9334 SMPTE HOTLink™ deserializer/receiver
• X9 + X4 + 1 descrambler and NRZI-to-NRZ decoder may
be bypassed for raw data output
This device performs both TRS (sync) detection and framing,
data descrambling with the SMPTE-259M X9 + X4 + 1 algorithm, and NRZI-to-NRZ decoding. These functions operate at
any character rate from 16 to 40 MHz. For those systems operating with non-SMPTE-259M compliant video streams (or for
diagnostic purposes), the descrambler and NRZI decoding
functions can be disabled.
DVB-ASI Operation
The CY7C9335 also contains the necessary multiplexers, control inputs and outputs, to control a DVB-ASI compliant video
stream. DVB-ASI operation is enabled through activation of a
single input signal. This allows a single serial-to-parallel input
port to support both SMPTE and DVB data streams under software or hardware control.
Functional Description
SMPTE-259M Operation
The CY7C9335 is a CMOS integrated circuit designed to decode SMPTE-125M and SMPTE-244M bit-parallel digital characters (or other data formats) using the SMPTE-259M decoding rules. Following decoding, the characters are framed by
locating the 30-bit TRS pattern in the parallel character
stream. The framed characters are then output.
In DVB-ASI mode the CY7C9335 automatically enables both
the 8B/10B decoder and multi-byte framer present in the
CY7B9334 receiver/deserializer. All error detection, fill, and
command codes are detected and output by the CY7C9335.
The CY7C9335 operates from a single +5V or −5V supply. It is
available in a 100-pin TQFP space saving package.
D2
D1
D 0( S C / D )
INPUT REGISTER
D3
10
4
P D 9( S V S )
10
PD8
P D7
10
OUTPUT REGISTER
11
D4
10
A/B
MODE MULTIPLEXOR
D5
19
RF
OFFSET
D6
TRS DETECTOR/FRAMER
D7
SMPTE DESCRAMBLER
D8
NRZI-TO-NRZ DECODER
D 9( R V S )
BARREL SHIFTER
Logic Block Diagram
P D6
P D5
P D4
P D3
P D2
PD1
PD0(SC/D)
SYNC_EN
BYPASS
H_SYNC
DVB_EN
SYNC_ERR
CKR
OE
HOTLink is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 19, 1999
CY7C9335
Pin Configuration
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NC
V CC
A/B
RF
NC
D 9( R V S )
D8
D7
D6
D5
VCC
VSS
V SS
VCC
V SS
D4
D3
D2
D1
D 0 (SC/D)
NC
NC
NC
VSS
NC
TQFP
Top View
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V SS
V CC
NC
NC
NC
NC
NC
NC
NC
NC
CKR
V SS
NC
V CC
V SS
NC
NC
SYNC_ERR
NC
H_SYNC
NC
NC
NC
V SS
NC
NC
V SS
NC
P D 9( R V S )
NC
PD8
PD7
NC
PD6
PD5
V SS
V CC
NC
V SS
V CC
PD4
PD3
NC
PD2
NC
PD1
NC
PD0(SC/D)
V CC
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V SS
V SS
NC
NC
NC
NC
NC
NC
NC
OE
V SS
V CC
NC
V SS
V SS
BYPASS
NC
NC
SYNC_EN
NC
NC
DVB_EN
NC
V CC
NC
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage................................................>2001 V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −40°C to +125°C
Latch-Up Current............................................................>200 mA
Supply Voltage to Ground Potential..................−0.5V to +7.0V
Operating Range
DC Voltage Applied to Outputs
in High-Z State.....................................................−0.5V to +7.0V
Range
Output Current Into Outputs ........................................ 16 mA
Commercial
DC Input Voltage .................................................−0.5V to +7.0V
Industrial
2
Ambient
Temperature
VCC
0°C to +70°C
5V ± 5%
−40°C to +85°C
5V ± 10%
CY7C9335
Pin Descriptions
CY7C9335 SMPTE-259M Decoder
Name
I/O
Description
BYPASS
Input
Bypass SMPTE decoding. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at the
rising edge of CKR (and DVB_EN is HIGH), the data latched into the input register is routed around both
the NRZI decoder and the SMPTE descrambler and presented to the output register. If BYPASS is LOW
at the rising edge of the CKR clock (and DVB_EN is HIGH), the data present in the input register is routed
through the NRZI decoder and SMPTE scrambler.
RF
Output
Reframe. This output is the inverted DVB-EN signal.
A/B
Output
CY7B9334 Port Select. When in DVB-ASI mode, this output will alternately select either the INA± or INB±
receiver port based on errors detected in the data stream. This allows CY7C9335 to operate with normal
and inverted DVB-ASI data streams (as would be commonly found on DVB-ASI streams routed through
SMPTE switches). This requires the CY7B9334 INA± and INB± inputs to be connected to the same
signal, but with INB± connected to invert the signal.
H_SYNC
Output
Horizontal Sync. This output toggles once every time that the TRS field is recognized. It changes state
one clock cycle prior to the first character of the TRS field (3FF in 10-bit hex) appearing at the PD0−9
outputs. This output also toggles to indicate detection of a TRS sequence, even when the TRS characters
are at a different offset from the present offset and SYNC_EN is active (HIGH). This toggling action is
disabled when DVB_EN is active (LOW).
SYNC_EN
Input
Sync Filtering Enabled. This input controls the operation of the SMPTE framer. When this signal is active
(HIGH) and a TRS sequence is detected, if the 10-bit character boundary is different from the previously
received TRS, the H_SYNC output is toggled, but the character offset is not updated. If the immediately
following TRS also has a different offset, the H_SYNC output is again toggled and the character offset
is updated to match that of the detected TRS sequence. When this signal is inactive (LOW), the framer
will update the character offset and toggle H_SYNC on every detected TRS sequence.
SYNC_ERR Output
Sync Error. This output pulses HIGH for one CKR clock period when a TRS sequence is detected that
is offset from its previous 10-bit character offset. This pulse starts at the same time as the H_SYNC signal
toggles, but only occurs when SYNC_EN is active (HIGH) and the character offset is not updated.
PD9(RVS)
Output
Parallel Data 9 or Received Violation Symbol. This is the MSB of the framed output data bus. It is latched
in the output register at the rising edge of CKR. When DVB_EN is active (LOW), this output indicates
that the character present on PD 8−0 identifies the type of error detected in the character stream. When
DVB_EN is disabled (HIGH), the character in the output register bits PD9−0 is a descrambled and framed
character of the SMPTE data stream.
PD8−1
Output
Parallel Data 8 through 1. The signals present at the PD8−1 outputs are latched in the output register at
the rising edge of CKR. When DVB_EN is disabled (HIGH), these signals are the middle eight bits of the
descrambled and framed SMPTE 10-bit data character. When DVB_EN is active (LOW), these signals
are full DVB-ASI data bus.
PD0(SC/D)
Output
Parallel Data 0 or Special Code/Data Select. This is the LSB of the output data field. It is latched in the
output register at the rising edge of CKR. When DVB_EN is active (LOW), this output identifies that the
character present in PD8−1 is either a command (HIGH) or data (LOW) character). When DVB_EN is
inactive (HIGH), this output data bit is the LSB of the descrambled and framed SMPTE data character.
D9(RVS)
Input
Input Bit 9. This is the MSB of the input register. It should be connected directly to the CY7B9334
deserializer output signal RVS(Qj).
D8−1
Input
Input Bits 8 through 1. These signals should be connected directly to the CY7B9334 deserializer output
signals Q7−0 respectively.
D0(SC/D)
Input
Input Bit 0. This is the LSB of the input register. It should be connected directly to the CY7B9334 deserializer output signal SC/D(Qa).
DVB_EN
Input
DVB Mode Enable. This signal is sampled by the rising edge of the CKR clock. If DVB_EN is active (LOW),
the data present on the D 0−9 inputs are latched and routed to the PD0−9 outputs.
CKR
Input
Recovered Clock Read. This clock controls all synchronous operations of the CY7C9335. It operates at
the character rate which is equivalent to one tenth the deserialized bit-rate. This clock is driven directly
by the CKR output of the CY7B9334 deserializer.
OE
Input
Output Enable. When this signal is HIGH all outputs are driven to their normal logic levels. When LOW,
all outputs are placed in a High-Z state.
3
CY7C9335
Pin Descriptions (continued)
CY7C9335 SMPTE-259M Decoder
Name
I/O
Description
VCC
Power.
VSS
Ground.
DVB-ASI Operation
CY7C9335 Description
The CY7C9335 is designed to operate in both SMPTE-259M
and DVB-ASI environments. When operated in SMPTE-only
environments, the DVB_EN inputs must be tied to V CC or driven HIGH.
Input Register
The input register is clocked by the rising edge of CKR. This
register captures the data present at the D 0−9 inputs on every
clock cycle. In addition to the data inputs, all control inputs
except OE are also captured at each rising edge of CKR. This
includes BYPASS, DVB_EN, and SYNC_EN.
DVB-ASI operation is enabled by asserting DVB_EN LOW.
This signal is latched by the rising edge of the CKR clock.
When the CY7C9335 is placed in DVB mode, the SMPTE and
NRZI decoders are bypassed, and the data latched into the
input register is routed directly to the output register.
NRZI-to-NRZ Decoder
The data in the input register is routed through
NRZI-to-NRZ decoder prior to being fed to the SMPTE
scrambler. This removes the extra transitions added to
data stream by the NRZI encoder at the transmit end of
interface.
Error Detected
an
dethe
the
Errors detected in the DVB-ASI data stream are indicated by
the Q 9 bit being HIGH. The specific type of error is identified
by the remaining Q8−0 bits in the output register.
Command Code Reception
SMPTE Descrambler
The DVB-ASI interface does not normally transmit any command characters other than the K28.5 code that is used both
for synchronization and as a fill character when data is not
being transmitted. These K28.5 characters are normally received as C5.0 characters. If other command characters are
also transmitted, these characters are identified by Q0 being
HIGH, and by the bits present on Q8−1.
Once the data has been converted back to NRZ, it is then
routed through a linear feed-forward descrambler. It decodes
the data present in the NRZ decode register using the
X9 + X4 + 1 polynomial to remove the extra transitions added
to the data stream at the transmit end of the interface.
TRS Framer
DVB Invert Controller
The TRS Framer is used to detect all 30-bit TRS sequences
(3FF, 000, 000 in 10-bit hex) in the character stream. Anytime
this sequence is detected, the H_SYNC output toggles.
DVB-ASI data streams are use 8B/10B encoded characters. If
these characters are routed through SMPTE switches or repeaters, the signals may be inverted causing them to decode
into incorrect or illegal characters. The CY7C9335 contains a
state machine that, in conjunction with the CY7B9334 SMPTE
HOTLink receiver, allows inverted DVB-ASI data streams to be
decoded into their correct characters.
This sequence is also used to frame the received characters
so that the characters delivered to the output register are on
their correct 10-bit boundaries. If SYNC_EN is disabled (LOW)
and the TRS sequence is detected in the decoded data
stream, the character offset register is set to match the offset
of the TRS sequence, and both the TRS sequence and the
following characters are output on their proper 10-bit boundaries.
This state machine is only enabled when in DVB mode. It monitors the data stream for errors, and inverts the data stream at
the CY7B9334 if it exceeds a preset statistical error rate. For
this to operate the A/B output of the CY7C9335 needs to be
connected to the A/B input of the CY7B9334 SMPTE HOTLink
receiver (through the appropriate resistive divider).
If SYNC_EN is enabled, and a TRS sequence is detected
whose character offset does not match that in the offset register, an internal flag is set but the offset register is not updated.
On the next consecutive TRS sequence this flag is cleared and
the offset register is updated.
If the CY7C9335 is not used for DVB-ASI operation, the A/B
output may be left open.
4
CY7C9335
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
IOH = −3.2 mA, VCC = Min.
VOL
Output LOW Voltage
IOL = 16.0 mA, VCC = Min
VIH
Input HIGH Voltage
Note 1
VIL
Input LOW Voltage
IIX
Input Load Current
IOZ
Output Leakage Current
IOS
Output Short Circuit Current
[2, 3]
Min.
Max.
Unit
2.4
V
0.5
V
2.0
7.0
V
Note 1
−0.5
0.8
V
GND ≤ VI ≤ VCC
−10
+10
µA
GND ≤ VO ≤ VCC, Output Disabled
−50
+50
µA
VCC = Max., VOUT = 0.5V
−30
−160
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
f = 1 MHz, VCC = 5.0V
Max.
Unit
10
pF
12
pF
AC Test Loads and Waveforms
TTL OUTPUTS
ALL INPUT PULSES
238Ω
238Ω
3.0V
5V
5V
90%
OUTPUT
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
170Ω
35 pF
(a)
170
90%
10%
GND
10%
< 2 ns
INCLUDING
JIG AND
(b)
SCOPE
Equivalent to: THÉVENIN
99 Ω
OUTPUT
< 2 ns
7C9335–9
EQUIVALENT
2.08V
Switching Characteristics Over the Operating Range[4]
Parameter
Description
CY7C9335-27
CY7C9335-40
Min.
Min.
Max.
Max.
Unit
15
ns
tPD
Input to Output (DVB_EN to RF only)
tSD
Input Data Set-Up Time to CKR
10
8
ns
tHD
Input Data Hold Time to CKR
0
0
ns
tCPRH
CKR Pulse Width HIGH
6.5
6.5
ns
tCPRL
CKR Pulse Width LOW
6.5
6.5
ns
tCKR
Read Clock Cycle[5]
30
tA
Output Access Time from CKR
tH
Output Hold Time from CKR
tEA
Input to Output Enable
20
62.5
25
10
4
ns
8
ns
3
24
[6]
62.5
ns
20
ns
Input to Output Disable
24
20
ns
tER
Notes:
1. These are absolute values with respect to device ground. All overshoots with respect to system or tester noise are included.
2. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
3. Tested initially and after any design or process changes that may effect these parameters.
4. All AC parameters are with all outputs switching.
5. The clock period may be extended by up to 90% for a single clock cycle when framing occurs in DVB-ASI mode.
6. Test load (b) used for this parameter. Test load (a) used for all other AC parameters.
5
CY7C9335
Switching Waveform
tCKR
tSD
tHD
D0−9, DVB_EN,
BYPASS,
SYNC_EN,
CKR
tCPRL
tCPRH
tA
PD0−9, SYNC_ER
H_SYNC, RF, A/B
tPD
tH
tEA
tER
DVB_EN
OE
RF
Ordering Information
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C9335-270AC
A100
100-pin Thin Quad Flat Pack
Commercial
CY7C9335-400AC
A100
100-pin Thin Quad Flat Pack
Commercial
Document #: 38-00572-B
6
CY7C9335
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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