ALSC ASM2I9942C-32-ET Low voltage 1:18 clock distribution chip Datasheet

ASM2I9942C
May 2005
rev 0.2
Low Voltage 1:18 Clock Distribution Chip
Features
device ideal for supplying clocks for a high performance
ƒ
LVCMOS/LVTTL Clock Input
ƒ
2.5V
LVCMOS
Outputs
Pentium II TM microprocessor based design.
for
Pentium
IITM*
With a low output impedance (≈12Ω), in both the HIGH and
LOW logic states, the output buffers of the ASM2I9942C
Microprocessor Support
are ideal for driving series terminated transmission lines.
ƒ
150pS Maximum Targeted Output–to–Output Skew
ƒ
Maximum Output Frequency of 250MHz @ 3.3 VCC
ƒ
32–Lead TQFP and LQFP Packaging
output. This capability gives the ASM2I9942C an effective
ƒ
Single 3.3V or 2.5V Supply.
fanout of 1:36. The ASM2I9942C provides enough copies
ƒ
Pin and Function compatible to MPC942C.
Functional Description
With an output impedance of 12Ω, the ASM2I9942C can
drive two series terminated transmission lines from each
of low skew clocks for most high performance synchronous
systems.
The LVCMOS/LVTTL input of the ASM2I9942C provides a
The ASM2I9942C is a 1:18 low voltage clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device is offered in two versions; the ASM2I9942C has an
LVCMOS input clock while the ASM2I9942P has an
LVPECL input clock. The 18 outputs are 2.5V or 3.3V
LVCMOS compatible and feature the drive strength to drive
50Ω series or parallel terminated transmission lines. With
output–to–output skews of 200pS, the ASM2I9942C is
ideal as a clock distribution chip for the most demanding of
more standard LVCMOS interface. The OE pins will place
the outputs into a high impedance state. The OE pin has an
internal pullup resistor.
The ASM2I9942C is a single supply device. The VCC power
pins require either 2.5V or 3.3V. The 32–lead TQFP and
LQFP package is chosen to optimize performance, board
space and cost of the device. The 32–lead TQFP has a
7x7mm2 body size with a conservative 0.8mm pin spacing.
synchronous systems. The 2.5V outputs also make the
*Pentium II is a trademark of Intel Corporation
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM2I9942C
May 2005
rev 0.2
Block Diagram
Table 1. Function Table
Q0
LVCMOS_CLK
Q1:Q16
Q17
OE
Output
0
1
HIGH IMPEDANCE
OUTPUTS ENABLED
OE
(Int. Pullup)
Q6
Q7
Q8
VCC
Q9
Q10
Q11
GND
Pin Diagram
24
23
22
21
20
19
18
17
GND
25
16
VCC
Q5
26
15
Q12
Q4
27
14
Q13
Q3
28
13
Q14
VCC
29
12
GND
Q2
30
11
Q15
Q1
31
10
Q16
Q0
32
9
Q17
1
2
3
4
5
6
7
8
GND
GND
LVCMOS_CLK
NC
OE
NC
VCC
VCC
ASM2I9942C
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
2 of 10
ASM2I9942C
May 2005
rev 0.2
Table 2. Pin Configuration
Pin #
Pin Name
1,2,12,17,25
GND
3
LVCMOS_CLK
I/O
Type
Supply
Ground
Input
LVCMOS
4,6
NC
-
-
5
OE
Input
LVCMOS
VCC
Supply
VCC
7,8,16,21,29
Function
LVCMOS Clock Input
No Connect
Outputs are enabled, when OE is
high and are tri-stated, when OE is
made low.
Positive power supply
9-11
Q17-Q15
Output
LVCMOS
Clock outputs
13-15
Q14-Q12
Output
LVCMOS
Clock outputs
18-20
Q11-Q9
Output
LVCMOS
Clock outputs
22-24
Q8-Q6
Output
LVCMOS
Clock outputs
26-28
Q5-Q3
Output
LVCMOS
Clock outputs
30-32
Q2-Q0
Output
LVCMOS
Clock outputs
Table 3. Absolute Maximum Rating1
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.6
V
VI
Input Voltage
–0.3
V
IIN
TStor
Input Current
Storage Temperature Range
–40
VCC + 0.3
±20
125
mA
°C
Note: 1These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Table 4. DC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%)
Symbol
Characteristic
Min
Typ
2.0
Max
Unit
VCCI
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Input Current
CIN
Input Capacitance
4.0
pF
CPD
Power Dissipation Capacitance
14
pF
0.8
2.0
Condition
V
V
IOH = –16 mA
0.5
V
IOL = 16 mA
±200
µA
ZOUT
Output Impedance
12
Ω
ICC
Maximum Quiescent Supply Current
0.5
mA
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
Per Output
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ASM2I9942C
May 2005
rev 0.2
Table 5. AC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%)
Symbol
Characteristic
Fmax
Maximum Frequency
tPLH
Propagation Delay1
Min
Typ
1.5
Output-to-output Skew
Within one bank
Unit
200
MHz
2.8
nS
Condition
150
pS
350
Any output, Any Bank
tsk(o)
Max
tsk(pr)
Part–to–Part Skew1, 2
1.3
nS
tsk(pr)
dt
Part–to–Part Skew1, 3
600
pS
Duty Cycle
45
55
%
tr, tf
Output Rise/Fall Time
0.2
1.0
nS
Max
Unit
VCCI
V
Note: 1.Tested using standard input levels, production tested @ 133 MHz.
2.Across temperature and voltage ranges, includes output skew.
3.For a specific temperature and voltage, includes output skew.
Table 6. DC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%)
Symbol
Characteristic
Min
Typ
VIH
Input HIGH Voltage
2.4
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIN
Input Current
CIN
Input Capacitance
4.0
pF
CPD
Power Dissipation Capacitance
14
pF
ZOUT
Output Impedance
12
Ω
ICC
Maximum Quiescent Supply Current
0.5
mA
0.8
2.4
Condition
V
V
IOH = –20 mA
0.5
V
IOL = 20 mA
±200
µA
Per Output
Table 7. AC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%)
Symbol
Characteristic
Fmax
Maximum Frequency
tPLH
Propagation Delay1
tsk(o)
Min
1.3
Output-to-output Skew
Within one bank
Max
Unit
250
MHz
2.3
nS
Condition
150
pS
350
Any Output, Any Bank
Part–to–Part Skew
1,2
tsk(pr)
dt
Part–to–Part Skew
1,3
Duty Cycle
45
tr, tf
Output Rise/Fall Time
0.2
tsk(pr)
Typ
1.0
nS
500
pS
55
%
1.0
nS
Note: 1.Tested using standard input levels, production tested @ 133 MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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ASM2I9942C
May 2005
rev 0.2
Power Consumption of the ASM2I9942C and
Thermal Management
Where ICCQ is the static current consumption of the
ASM2I9942C, CPD is the power dissipation capacitance
per output, (Μ)ΣCL represents the external capacitive
The ASM2I9942C AC specification is guaranteed for the
output load, N is the number of active outputs (N is
entire operating frequency range up to 250MHz. The
always
ASM2I9942C power consumption and the associated
ASM2I9942C supports driving transmission lines to
long-term
12
in
case
of
the
ASM2I9942C).
The
maximum
maintain high signal integrity and tight timing parameters.
frequency limit, depending on operating conditions such
Any transmission line will hide the lumped capacitive load
as clock frequency, supply voltage, output loading,
at the end of the board trace, therefore, ΣCL is zero for
ambient temperature, vertical convection and thermal
controlled
conductivity
reliability
of
may
This
line
systems
and
can
be
eliminated from equation 1. Using parallel termination
output termination results in equation 2 for power
temperature and gives a guideline to estimate the
dissipation.
junction
board.
transmission
section
die
and
the
describes the impact of these parameters on the junction
ASM2I9942C
package
decrease
temperature
and
the
associated device reliability.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination. VOL, IOL, VOH and IOH are
Table 8. Die junction temperature and MTBF
a function of the output termination technique and DCQ is
the clock signal duty cycle. If transmission lines are used
ΣCL is zero in equation 2 and can be eliminated. In
Junction temperature (°C)
MTBF (Years)
100
20.4
general,
110
9.1
techniques eliminates the impact of the lumped capacitive
120
4.2
loads at the end lines and greatly reduces the power
130
2.0
dissipated
in
the
ASM2I9942C
is
According to Table 8, the junction temperature can be
used to estimate the long-term device reliability. Further,
power
represented
combining equation 1 and equation 2 results in a
in
maximum operating frequency for the ASM2I9942C in a
equation1.
series terminated transmission line system, equation 4.



PTOT =  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  ⋅VCC
M



Equation 1



PTOT = VCC ⋅  I CCQ + VCC ⋅ f CLOCK ⋅  N ⋅ C PD + ∑ C L  + ∑ DCQ ⋅ I OH (VCC − VOH ) + (1 − DCQ )⋅ I OL ⋅VOL
M

 P

TJ = TA + PTOT ⋅ Rthja
[
f CLOCKMAX =
line
Where Rthja is the thermal impedance of the package
needs to be controlled and the thermal impedance of the
The
transmission
(junction to ambient) and TA is the ambient temperature.
MTBF, the die junction temperature of the ASM2I9942C
optimized.
controlled
consumption.
(MTBF). According to the system-defined tolerable
be
of
junction temperature TJ as a function of the power
junction temperature and impact the device reliability
should
use
dissipation of the device. Equation 3 describes the die
Increased power consumption will increase the die
board/package
the

T
− TA
1
⋅  J , MAX
− (I CCQ ⋅VCC )
2
C PD ⋅ N ⋅ VCC  Rthja

Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
]
Equation 2
Equation 3
Equation 4
5 of 10
ASM2I9942C
May 2005
rev 0.2
TJ,MAX should be selected according to the MTBF
If the calculated maximum frequency is below 350 MHz, it
system requirements and Table 8. Rthja can be derived
becomes the upper clock speed limit for the given
from Table 9. The Rthja represent data based on 1S2P
application conditions. The following eight derating charts
boards, using 2S2P boards will result in a lower thermal
describe the safe frequency operation range for the
impedance than indicated below.
ASM2I9942C. The charts were calculated for a maximum
Table 9. Thermal package impedance of the
32LQFP
tolerable die junction temperature of 110°C (120°C),
corresponding
to
an
estimated
MTBF of 9.1 years
(4 years), a supply voltage of 3.3V and series terminated
Convection,
LFPM
Rthja (1P2S
board), °C/W
Rthja (2P2S
board), °C/W
transmission line or capacitive loading. Depending on a
given set of these operating conditions and the available
Still air
86
61
device convection a decision on the maximum operating
100 lfpm
76
56
frequency can be made.
200 lfpm
71
54
300 lfpm
68
53
400 lfpm
66
52
500 lfpm
60
49
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
6 of 10
ASM2I9942C
May 2005
rev 0.2
Package Information
32-lead LQFP Package
SECTION A-A
Symbol
Dimensions
Inches
Millimeters
Min
Max
Min
Max
A
….
0.0630
…
1.6
A1
0.0020
0.0059
0.05
0.15
A2
0.0531
0.0571
1.35
1.45
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.20
e
a
0.031 BASE
0°
7°
0.8 BASE
0°
7°
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
7 of 10
ASM2I9942C
May 2005
rev 0.2
32-lead TQFP Package
SECTION A-A
Symbol
Dimensions
Inches
Millimeters
Min
Max
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.3465
0.3622
8.8
9.2
D1
0.2717
0.2795
6.9
7.1
E
0.3465
0.3622
8.8
9.2
E1
0.2717
0.2795
6.9
7.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0118
0.0177
0.30
0.45
b1
0.0118
0.0157
0.30
0.40
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.031 BASE
0.8 BASE
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
8 of 10
ASM2I9942C
May 2005
rev 0.2
Ordering Information
Ordering Code
Top Mark
Package Type
Operating Range
ASM2I9942C-32-LT
ASM2I9942CL
32-pin LQFP, Tray
Industrial
ASM2I9942C-32-LR
ASM2I9942CL
32-pin LQFP –Tape and Reel
Industrial
ASM2I9942CG-32-LT
ASM2I9942CGL
32-pin LQFP, Tray, Green
Industrial
ASM2I9942CG-32-LR
ASM2I9942CGL
32-pin LQFP –Tape and Reel, Green
Industrial
ASM2I9942C-32-ET
ASM2I9942CE
32-pin TQFP, Tray
Industrial
ASM2I9942C-32-ER
ASM2I9942CE
32-pin TQFP –Tape and Reel
Industrial
ASM2I9942CG-32-ET
ASM2I9942CGE
32-pin TQFP, Tray, Green
Industrial
ASM2I9942CG-32-ER
ASM2I9942CGE
32-pin TQFP –Tape and Reel, Green
Industrial
Device Ordering Information
A S M 2 I 9 9 4 2 C G - 3 2 - L R
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
9 of 10
ASM2I9942C
May 2005
rev 0.2
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM2I9942C
Document Version: 0.2
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
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respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
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Low Voltage 1:18 Clock Distribution Chip
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