Cypress B9949CA 3.3v 160-mhz 1:15 clock distribution buffer Datasheet

B9949
3.3V 160-MHz 1:15 Clock Distribution Buffer
Features
•
•
•
•
•
•
•
•
•
•
Description
160MHz Clock Support
LVPECL or LVCMOS/LVTTL Clock Input
LVCMOS/LVTTL Compatible Inputs
15 Clock Outputs: Drive up to 30 Clock Lines
1X and 1/2X Configurable Outputs
Output Three-state Control
350 ps Maximum Output-to-Output Skew
Pin Compatible with MPC949
Industrial Temp. Range: –40°C to +85°C
52-Pin TQFP Package
The B9949 is a low-voltage clock distribution buffer with the
capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources
can be used to provide for test clocks as well as the primary
system clocks. All other control inputs are LVCMOS/LVTTL
compatible. The 15 outputs are 3.3V LVCMOS or LVTTL compatible and can drive two series terminated 50Ω transmission
lines. With this capability the B9949 has an effective fan-out of
1:30.
The B9949 is capable of generating 1X and 1/2X signals from
a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of
1X to1/2X outputs.
The B9949 outputs can also be three-stated via MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops
and three-states the outputs.
Block Diagram
TCLK_SEL
TCLK0 (LVTTL)
0
TCLK1 (LVTTL)
1
/1
0
1
/2
R
PECL_CLK
PECL_CLK#
0
PCLK_SEL
1
2
QA0:1
DSELA
0
3
QB0:2
1
DSELB
0
4
QC0:3
1
DSELC
0
6
QD0:5
1
DSELD
MR/OE#
Cypress Semiconductor Corporation
Document #: 38-07081 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 21, 2002
B9949
Pin Configuration
NC
VDDC
QB2
VSS
QB1
VDDC
QB0
VSS
VSS
QA1
VDDC
QA0
VSS
52 51 50 49 48 47 46 45 44 43 42 41 40
MR/OE#
TCLK_SEL
VDD
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
B9949
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
VSS
QC0
VDDC
QC1
VSS
QC2
VDDC
QC3
VSS
VSS
QD5
NC
14 15 16 17 18 19 20 21 22 23 24 25 26
NC
VDDC
QD4
VSS
QD3
VDDC
QD2
VSS
QD1
VDDC
QD0
VSS
NC
Document #: 38-07081 Rev. *C
Page 2 of 8
B9949
Pin Description [1]
Pin
Name
PWR
I/O
Description
6
PECL_CLK
I, PD
PECL Input Clock.
7
PECL_CLK#
I, PU
PECL Input Clock.
TCLK(0,1)
I, PU
External Reference/Test Clock Input.
4, 5
49, 51
QA(1,0)
VDDC
O
Clock Outputs.
42, 44, 46
QB(2:0)
VDDC
O
Clock Outputs.
31, 33, 35, 37
QC(3:0)
VDDC
O
Clock Outputs.
16, 18, 20, 22,
24, 28
QD(5:0)
VDDC
O
Clock Outputs.
9, 10, 11, 12
DSEL(A:D)
I, PD
Divider Select Inputs. When HIGH, selects ÷2 input divider. When
LOW, selects ÷1 input divider.
2
TCLK_SEL
I, PD
TCLK Select Input. When LOW, TCLK0 clock is selected and when
HIGH TCLK1 is selected.
8
PCLK_SEL
I, PD
PECL Select Input. When HIGH, PECL clock is selected and when
LOW TCLK(0,1) is selected
1
MR_OE#
I, PD
Output Enable Input. When asserted LOW, the outputs are enabled and when asserted HIGH, internal flip-flops are reset and
the outputs are three-stated.
17, 21, 25, 32,
36, 41, 45, 50
VDDC
3.3V Power Supply for Output Clock Buffers.
3
VDD
3.3V Power Supply
13, 15, 19, 23,
29, 30, 34, 38,
43, 47, 48, 52
VSS
Common Ground
14, 26, 27, 39,
40,
NC
Not Connected
Note:
1. PD = Internal Pull-Down, PU = Internal Pull-Up.
Document #: 38-07081 Rev. *C
Page 3 of 8
B9949
Maximum Ratings[2]
Storage Temperature: ................................ –65°C to + 150°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
Operating Temperature: ................................ –40°C to +85°C
VSS < (Vin or Vout) < VDD
Maximum ESD protection ............................................... 2KV
Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
Maximum Input Voltage Relative to VSS: ............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V
Maximum Power Supply: ................................................5.5V
Maximum Input Current:...................................................±20mA
DC Parameters: VDDC = 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C
Parameter
VIL
VIH
Description
Input Low Voltage
Input High Voltage
Conditions
Min.
Typ.
Max.
Unit
V
PECL_CLK, Single Ended
1.49
1.825
All other inputs
VSS
0.8
PECL_CLK, Single Ended
2.135
2.42
2.0
VDD
All other inputs
V
IIL
Input Low Current (@VIL = VSS) Note 3
–100
µA
IIH
Input High Current (@VIL = VDD)
100
µA
VPP
Peak-to-Peak Input Voltage
PECL_CLK
300
1000
mV
VCMR
Common Mode Range
PECL_CLK
VDD – 2.0
VDD – 0.6
V
VOL
Output Low Voltage
IOL = 20 mA, Note 5
0.4
V
VOH
Output High Voltage
IOH = –20 mA, VDDC = 3.3V, Note 5
IDD
Quiescent Supply Current
All VDDC and VDD
Cin
Input Capacitance
Note 4
2.5
V
1
2
mA
4
pF
Notes:
2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification.
5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07081 Rev. *C
Page 4 of 8
B9949
AC Parameters[6]: VDDC = 3.3V ±5%, VDD = 3.3V ±5%, TA = –40°C to +85°C
Parameter
Fmax
Tpd
Description
Maximum Input Frequency
PECL_CLK to Q Delay
Delay[7]
FoutDC
Output Duty
tpZL, tpZH
tpLZ, tpHZ
Tskew (pp)
Tr/Tf
Min.
Typ.
Max.
160
[7]
TCLK to Q
Tskew
Conditions
[7]
Cycle[7, 8]
MHz
4.0
-
8.6
4.2
-
10.5
ns
TCYCLE/2
–1
TCYCLE/2 +
1
ns
Output Enable Time (all outputs)
2
10
ns
Output Disable Time (all outputs)
2
10
ns
350
ps
ns
Output-to-Output Skew
Part-to-Part Skew
Measured at VDDC/2
Unit
[7, 9]
Fin<130MHz
[10]
Output Clocks Rise/Fall Time
[9]
PECL_CLK to Q
1.5
2.75
TCLK to Q
2.0
4.0
0.8V to 2.0V
0.10
1.0
ns
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50Ω transmission lines.
8. 50% input duty cycle.
9. Outputs loaded with 30 pF each
10. Part-to-Part Skew at a given temperature and voltage
Document #: 38-07081 Rev. *C
Page 5 of 8
B9949
Package Drawing and Dimensions (52 TQFP)
D
D1
10°
A1
A2
A
L
e
b
52-Pin TQFP Outline Dimensions
Inches
Symbol
Millimeters
Min.
Nom.
Max.
Min.
Nom.
Max.
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
-
0.041
0.95
-
1.05
D
-
0.472
-
-
12.00
-
D1
-
0.394
-
-
10.00
-
0.009
-
0.015
0.22
-
0.38
b
e
L
0.026 BSC
0.018
Document #: 38-07081 Rev. *C
-
0.65 BSC
0.030
0.45
-
0.75
Page 6 of 8
B9949
Ordering Information
Part Number
B9949CA[11]
Package Type
52 PIN TQFP
Production Flow
Industrial, –40°C to +85°C
Note:
11. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below.
Marking: Example:
Cypress
B9949CA,
Date Code, Lot #
B9949CA
Package
A = TQFP
Revision
Device Number
Document #: 38-07081 Rev. *C
Page 7 of 8
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
B9949
Document Tital: B9949 3.3V, 160-MHz, 1:15 Clock Distribution Buffer
Document Number: 38-07081
Rev.
ECN No.
Issue
Date
Orig. of
Change
**
107117
06/06/01
IKA
Convert from IMI to Cypress
*A
108062
07/03/01
NDP
Changed Commercial to Industrial
*B
109807
02/01/02
DSG
Convert from Word Doc to Adobe Framemaker
*C
122766
12/14/02
RBI
Add power up requirements to maximum ratings information
Document #: 38-07081 Rev. *C
Description of Change
Page 8 of 8
Similar pages