TOSHIBA TMP91FW60FG

16 Bit Microcontroller
TLCS-900/L1 Series
TMP91FW60FG
TMP91FW60DFG
Revision 1.9
TOSHIBA CORPORATION
The information contained herein is subject to change without notice.
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or
failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.
The Toshiba products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.).
These Toshiba products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage
of Toshiba products listed in this document shall be made at the customer's own risk.
The products described in this document shall not be used or embedded to any downstream products of
which manufacture, use and/or sale are prohibited under any applicable laws and regulations.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any patents
or other rights of TOSHIBA or the third parties.
Please contact your sales representative for product-by-product details in this document regarding RoHS
compatibility. Please use these products in this document in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for
damage or losses occurring as a result of noncompliance with applicable laws and regulations.
© 2007 TOSHIBA CORPORATION
All Rights Reserved
Revision History
Date
Revision
2006/2/28
0.1
TENTATIVE
2006/3/06
0.2
Flash section is corrected.
2006/3/13
0.3
Correction of a clerical error.
2006/8/04
1.4
P99 Figure 5-3 is corrected.
P99 Figure 5-4 is deleted.
P272 The value is added to T.B.D of Specification section.
P126 Figure 7-1
P132-133 TMRB Mode register
TA1OUT of TB3MOD and TB4MOD is corrected.
TA1OUT -> TA3OUT, TA5OUT
P226 Table 14-6 is corrected
P178 9.3.3.14 The description is corrected.
2006/10/31
1.5
SCOUT: System clock output fFPH -> fSYS
DC SPEC VIH/VIL is corrected.
Table 2-8 Sample Warm-up Times after Clearance of STOP
Mode is corrected.
Table 4-2 I/O Port Setting List is corrected.
PORT 3, 4, 7 control register/function register contrast table is
corrected.
1.1 Features Interrupts is corrected
9.3.2 I2CBus Mode control Register
Note1:Set the <BC2:0> to “000” before switching to a clockedsynchronous 8-bit SIO mode is deleted.
9.3.4.1 Device initialization SBI0CR1<P4EN> is deleted.
9.3.4.2 Start condition and slave address generation (1) Master
mode register settings is corrected.
6.4.1.2 Generating a 50% duty radio square wave pulse
register settings example is corrected.
6.4.3 8-bit PPG output mode.
Register settings is corrected.
6.4.4 8-bit PWM output mode
Register settings example is corrected.
Table 14-6 Correspondence between Operating Frequency and
Baund Rate in Single Boot Mode is corrected.
15.2 DC Electrical Characteristics
Peak current for intermittent operation
T.B.D -> 20mA
Date
Revision
2007/2/16
1.6
1.1 Features
Program patch logic
2.3.4 Prescaler Clock Controller is corrected.
16.Table of SFR's
2.1 RESET 10 system clocks 16us -> 1us
18. Points to Note and Restriction
2007/4/16
1.7
15.2 DC Electrical Characteristics
Power down voltage Min 4.5V -> 2.0V
14.6.10 Addresses of Program example are corrected
2007/8/27
1.8
DMAR register (89H) is corrected by RWM prohibition.
18.2 Points of note
j. Releasing the HALT mode by requesting an interruption is
deleted.
2.3.2 Note3 is added
8.2.1 SIO Plescaler is corrected, and Table 8-2 is corrected
8.3 Note2 and Note3 are added
18.2 Points of note
j.Clocks for serial channels (SIO) is added
2007/10/15
1.9
7.3 SFR
16. Table of SFR's
TB0FFCR, TB1FFCR, TB2FFCR, TB3FFCR and TB4FFCR
register is corrected.
TMP91FW60
CMOS 16 Bit Microcontroller
TMP91FW60FG/DFG
Product No.
ROM
(Flash ROM)
RAM
128K bytes
8K bytes
TMP91FW60FG
Package
LQFP100-P-1414-0.50F
TMP91FW60DFG
QFP100-P-1420-0.65A
1.1 Features
• High-speed 16-bit CPU (900/L1 CPU)
- Instruction mnemonics are upward-compatible with TLCS-900,900/H,900/L
- 16 Mbytes of linear address space
- General-purpose registers and register banks
- 16-bit multiplication and division instructions; bit transfer and arithmetic instructions
- Micro DMA: 4 channels (800ns/2 bytes at 20MHz)
• Minimum instruction execution time:200ns (at 20MHz)
• Built-in memory
- ROM:128K bytes (Flash ROM)
- RAM:8K bytes
• External memory expansion
- Expandable up to 16 Mbytes (shared program/data area)
- Can simultaneously support 8/16-bit width external data bus
Dynamic data bus syzing
• 8-bit timers: 6 channels
• 16-bit timers: 5 channels
• General-purpose serial interface: 5 channels
- UART/Synchronous mode: 3 channels
- I2C bus mode: 2 channels
• 10-bit AD converter (Built-in Sample hold circuit): 16 channels
• Special timer for CLOCK
This product uses the Super Flash® technology under the licence of Silicon Storage Technology, Inc. Super Flash® is registered trademark of Silicon Storage
Technology, Inc.
20070701-EN
• The information contained herein is subject to change without notice.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's
own risk.
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or
sale are prohibited under any applicable laws and regulations.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.
• Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these
products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
Page 1
2007-10-15
TMP91FW60
• Watchdog timer
• Program patch logic: 6 banks
• Chip select/wait controller: 4 channels
• Interrupts: 57 interrupts
- 9 CPU interrupts: Software interrupt instruction and illegal instruction
- 36 internal interrupts: 7 priority levels are selectable
- 12 external interrupts: 7 priority levels are selectable (among 1 interrupts are selectable edge mode)
• Input/output ports: 83 pins
• Standby function: Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP
• Clock controller
- Clock gear function: Select a High-frequency clock fc/1 to fc/16
- Oscillator for CLOCK (fs = 32.768 kHz)
• Operating voltage
Flash read operation
> Vcc=4.5 V - 5.5 V (fc max = 20MHz)
Flash write/erase operation
> Vcc=4.75 V - 5.25 V (fc max = 20MHz)
• Package
- LQFP100-P-1414-0.50F (TMP91FW60FG)
- QFP100-P-1420-0.65A (TMP91FW60DFG)
Page 2
2007-10-15
TMP91FW60
80
85
90
95
1
75
5
70
10
TMP91FW60FG
65
LQFP100
TOPVIEW
15
60
20
50
45
40
35
25
30
55
P30/TB3IN0/INT3/SDA0
PZ3/R/W
PZ2/HWR
PZ1/WR
PZ0/RD
P27/A7/A23
P26/A6/A22
P25/A5/A21
P24/A4/A20
P23/A3/A19
P22/A2/A18
DVCC
NMI
DVSS
P21/A1/A17
P20/A0/A16
P17/AD15/A15
P16/AD14/A14
P15/AD13/A13
P14/AD12/A12
P13/AD11/A11
P12/AD10/A10
P11/AD9/A9
P10/AD8/A8
P07/AD7
X2
DVSS
X1
AM1
RESET
P96/XT1
P97/XT2
BOOT/EMU0
EMU1
PA0/TB2IN0/INT1
PA1/TB2IN1/INT2
PA2/TB2OUT0
PA3/TB2OUT1
P40/CS0/SCOUT
P41/CS1/TXD2
P42/CS2/RXD2
P43/CS3/SCLK2/CTS2
P44/ALE
P00/AD0
P01/AD1
P02/AD2
P03/AD3
P04/AD4
P05/AD5
P06/AD6
VREFH
AVSS
AVCC
P70/TA0IN
P71/TA1OUT
P72/TA3OUT
P73/TA4IN
P74/TA5OUT
P75/INT0
P80/TB0IN0/INT5
P81/TB0IN1/INT6
P82/TB0OUT0
P83/TB0OUT1
P84/TB1IN0/INT7
P85/TB1IN1/INT8
P86/TB1OUT0
P87/TB1OUT1
P90/TXD0
P91/RXD0
P92/SCLK0/CTS0
P93/TXD1
P94/RXD1
P95/SCLK1/CTS1
AM0
DVCC
100
P67/AN15
P66/AN14
P65/AN13
P64/AN12
P63/AN11
P62/AN10
P61/AN9
P60/AN8
P57/AN7
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1
P50/AN0
DVSS
DVCC
PB3/TB4OUT1
PB2/TB4OUT0
PB1/TB4IN1/INT10/SCL1
PB0/TB4IN0/INT9/SDA1
P33/TB3OUT1
P32/WAIT/TB3OUT0
P31/TB3IN1/INT4/SCL0
1.2 Pin Assignment Diagram
Figure 1-1 Pin Assignment(TMP91FW60FG)
Page 3
2007-10-15
5
100
Page 4
QFP100
30
25
20
90
15
10
1
55
60
65
70
75
80
PB0/TB4IN0/INT9/SDA1
PB1/TB4IN1/INT10/SCL1
PB2/TB4OUT0
PB3/TB4OUT1
DVCC
DVSS
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
P60/AN8
P61/AN9
P62/AN10
P63/AN11
P64/AN12
P65/AN13
P66/AN14
P67/AN15
VREFH
AVSS
AVCC
P70/TA0IN
P71/TA1OUT
P72/TA3OUT
P73/TA4IN
P74/TA5OUT
P75/INT0
P80/TB0IN0/INT5
P81/TB0IN1/INT6
P82/TB0OUT0
P83/TB0OUT1
P84/TB1IN0/INT7
P85/TB1IN1/INT8
P86/TB1OUT0
P87/TB1OUT1
P90/TXD0
P91/RXD0
P92/SCLK0/CTS0
P93/TXD1
P94/RXD1
P95/SCLK1/CTS1
AM0
DVCC
X2
DVSS
X1
P33/TB3OUT1
P32/WAIT/TB3OUT0
P31/TB3IN1/INT4/SCL0
P30/TB3IN0/INT3/SDA0
PZ3/R/W
PZ2/HWR
PZ1/WR
PZ0/RD
P27/A7/A23
P26/A6/A22
P25/A5/A21
P24/A4/A20
P23/A3/A19
P22/A2/A18
DVCC
NMI
DVSS
P21/A1/A17
P20/A0/A16
P17/AD15/A15
P16/AD14/A14
P15/AD13/A13
P14/AD12/A12
P13/AD11/A11
P12/AD10/A10
P11/AD9/A9
P10/AD8/A8
P07/AD7
P06/AD6
P05/AD5
TMP91FW60
50
85
45
TMP91FW60DFG
40
TOPVIEW
95
35
P04/AD4
P03/AD3
P02/AD2
P01/AD1
P00/AD0
P44/ALE
P43/CS3/SCLK2/CTS2
P42/CS2/RXD2
P41/CS1/TXD2
P40/CS0/SCOUT
PA3/TB2OUT1
PA2/TB2OUT0
PA1/TB2IN1/INT2
PA0/TB2IN0/INT1
EMU1
EMU0/BOOT
P97/XT2
P96/XT1
RESET
AM1
Figure 1-2 Pin Assignment(TMP91FW60DFG)
2007-10-15
TMP91FW60
1.3 Block Diagram
Figure 1-3 Block Diagram
Page 5
2007-10-15
TMP91FW60
1.4 Pin Names and Functions
Table 1-1
Pin Names and Functions(1/3)
Pin
Number
Input
/
Output
P00-P07
AD0-AD7
8
IO
IO
Port 0: I/O port that allows I/O to be selected at the bit level
Address data (Lower): 0 to 7 address/data bus
P10-P17
AD8-AD15
A8-A15
8
IO
IO
O
Port1: I/O port that allows I/O to be selected at the bit level
Address data (Upper): 8 to 15 of address/data bus
Address: 8 to 15 of address bus
P20-P27
A0-A7
A16-A23
8
IO
O
O
Port 2: I/O port that allows I/O to be selected at the bit level
Address: 0 to 7 of address bus
Address: 16 to 23 of address bus
PZ0
RD
1
O
O
Port Z0: Output port
Read:Strobe signal for reading external memory
PZ1
WR
1
O
O
Port Z1: Output port
Write: Strobe signal for writing data to pins AD0 to AD7
PZ2
HWR
1
IO
O
Port Z2: I/O port (with pull-up resistor)
High write: Strobe signal for writing data to pins AD8 to AD15
PZ3
R/W
1
IO
O
Port Z3: I/O port (with pull-up resistor)
Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle.
1
IO
I
I
IO
Port 30: I/O port
16-bit timer 3 input 0:Timer B3 count/capture trigger Input 0
Interrupt Request Pin 3: Interrupt request pin with programmable rising edge / falling edge.
Serial bus interface data 0 in I2C bus Mode.
P31
TB3IN1
INT4
SCL0
1
IO
I
I
IO
Port 31: I/O port
16-bit timer 3 input 1:Timer B3 count/capture trigger Input 1
Interrupt Request Pin 4: Interrupt request on rising edge
Serial bus interface clock 0 in I2C bus Mode.
P32
WAIT
TB3OUT0
1
IO
I
O
Port 32: I/O port
Wait: Pin used to request CPU bus wait ((1 N) wait mode)
16-bit timer 3 output 0: Timer B3 Output 0
P33
TB3OUT1
1
IO
O
Port 33: I/O port
16-bit timer 3 output 1: Timer B3 Output 1
P40
CS0
SCOUT
1
IO
O
O
Port 40: I/O port (with pull-up resistor)
Chip Select 0: Outputs 0 when address is within specified address area
System Clock Output: Outputs fSYS or fs clock.
P41
CS1
TXD2
1
IO
O
O
Port 41: I/O port (with pull-up resistor)
Chip Select 1: Outputs 0 when address is within specified address area
Serial Send Data 2
P42
CS2
RXD2
1
IO
O
I
Port 42: I/O port (with pull-up resistor)
Chip Select 2: Outputs 0 when address is within specified address area
Serial Receive Data 2
P43
CS3
SCLK2
CTS2
1
IO
O
IO
I
Port 43: I/O port (with pull-up resistor)
Chip Select 3: Outputs 0 when address is within specified address area
Serial Clock I/O 2
Serial Data Send Enable 2 (Clear to Send)
P44
ALE
1
IO
O
Port 44: I/O port (with pull-up resistor)
Address Latch Enable
P50-57
AN0-AN7
8
IO
I
Port 5: I/O port
Analog input: Pin used to input to AD converter
Pin
Name
P30
TB3IN0
INT3
SDA0
Functions
Page 6
2007-10-15
TMP91FW60
Table 1-1
Pin Names and Functions(2/3)
Pin
Number
Input
/
Output
P60-67
AN8-AN15
8
IO
I
Port 6: I/O port
Analog input: Pin used to input to AD converter
P70
TA0IN
1
IO
I
Port 70: I/O port
8-bit timer 0 input: Timer A0 Input
P71
TA1OUT
1
IO
O
Port 71: I/O port
8-bit timer 1 output:Timer A1 Output
P72
TA3OUT
1
IO
O
Port 72: I/O port
8-bit timer 3 output:Timer A3 Output
P73
TA4IN
1
IO
I
Port 73: I/O port
8-bit timer 4 input: Timer A4 Input
P74
TA5OUT
1
IO
O
Port 74: I/O port
8-bit timer 5 output:Timer A5 Output
P75
INT0
1
IO
I
Port 75: I/O port
Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge.
P80
TB0IN0
INT5
1
IO
I
I
Port 80: I/O port
16-bit timer 0 input 0:Timer B0 count/capture trigger Input 0
Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge.
P81
TB0IN1
INT6
1
IO
I
I
Port 81: I/O port
16-bit timer 0 input 1:Timer B0 count/capture trigger Input 1
Interrupt Request Pin 6: Interrupt request on rising edge
P82
TB0OUT0
1
IO
O
Port 82: I/O port
16-bit timer 0 output 0: Timer B0 Output 0
P83
TB0OUT1
1
IO
O
Port 83: I/O port
16-bit timer 0 output 1: Timer B0 Output 1
P84
TB1IN0
INT7
1
IO
I
I
Port 84: I/O port
16-bit timer 1 input 0:Timer B1 count/capture trigger Input 0
Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge.
P85
TB1IN1
INT8
1
IO
I
I
Port 85: I/O port
16-bit timer 1 input 1:Timer B1 count/capture trigger Input 1
Interrupt Request Pin 8: Interrupt request on rising edge
P86
TB1OUT0
1
IO
O
Port 86: I/O port
16-bit timer 1 output 0: Timer B1 Output 0
P87
TB1OUT1
1
IO
O
Port 87: I/O port
16-bit timer 1 output 1: Timer B1 Output 1
P90
TXD0
1
IO
O
Port 90: I/O port
Serial Send Data 0
P91
RXD0
1
IO
I
Port 91: I/O port
Serial Receive Data 0
P92
SCLK0
CTS0
1
IO
IO
I
Port 92: I/O port
Serial Clock I/O 0
Serial Data Send Enable 0 (Clear to Send)
P93
TXD1
1
IO
O
Port 93: I/O port
Serial Send Data 1
P94
RXD1
1
IO
I
Port 94: I/O port
Serial Receive Data 1
Pin
Name
Functions
Page 7
2007-10-15
TMP91FW60
Table 1-1
Pin Names and Functions(3/3)
Pin
Number
Input
/
Output
P95
SCLK1
CTS1
1
IO
IO
I
Port 95: I/O port
Serial Clock I/O 1
Serial Data Send Enable 1 (Clear to Send)
P96
XT1
1
IO
I
Port 96: I/O port
Low-frequency oscillator connection pin
P97
XT2
1
IO
O
Port 97: I/O port
Low-frequency oscillator connection pin
PA0
TB2IN0
INT1
1
IO
I
I
Port A0: I/O port
16-bit timer 2 input 0:Timer B2 count/capture trigger Input 0
Interrupt Request Pin 1: Interrupt request pin with programmable rising edge / falling edge.
PA1
TB2IN1
INT2
1
IO
I
I
Port A1: I/O port
16-bit timer 2 input 1:Timer B2 count/capture trigger Input 1
Interrupt Request Pin 2: Interrupt request on rising edge
PA2
TB2OUT0
1
IO
O
Port A2: I/O port
16-bit timer 2 output 0: Timer B2 Output 0
PA3
TB2OUT1
1
IO
O
Port A3: I/O port
16-bit timer 2 output 1: Timer B2 Output 1
1
IO
I
I
IO
Port B0: I/O port
16-bit timer 4 input 0:Timer B4 count/capture trigger Input 0
Interrupt Request Pin 9: Interrupt request pin with programmable rising edge / falling edge.
Serial bus interface data 1 in I2C bus Mode.
PB1
TB4IN1
INT10
SCL1
1
IO
I
I
IO
Port B1: I/O port
16-bit timer 4 input 1:Timer B4 count/capture trigger Input 1
Interrupt Request Pin 10: Interrupt request on rising edge
Serial bus interface clock 1 in I2C bus Mode.
PB2
TB4OUT0
1
IO
O
Port B2: I/O port
16-bit timer 4 output 0: Timer B4 Output 0
PB3
TB4OUT1
1
IO
O
Port B3: I/O port
16-bit timer 4 output 1: Timer B4 Output 1
NMI
1
I
Non-Maskable Interrupt Request Pin: Interrupt request pin with programmable falling edge or both
edge.
AM0-1
2
I
Operation mode:Fixed to AM1 "1", AM0 "1".
EMU0-1
2
O
Set to Open pins
RESET
1
I
Reset: initializes TMP91FW60. (with pull-up resistor)
VREFH
1
I
Pin for reference voltage input to AD converter
AVCC
1
Power supply pin for AD converter
AVSS
1
GND pin for AD converter (0 V)
X1/X2
2
DVCC
3
Power supply pins (All DVCC pins should be connected with the power supply pin.)
DVSS
3
GND pins (0 V) (All DVSS pins should be connected with the GND (0V) pin.)
Pin
Name
PB0
TB4IN0
INT9
SDA1
IO
Functions
High frequency oscillator connection pins
Note: All pins that have built-in pull-up resistors (other than the RESET pin) can be disconnected from the built-in pull-up
resistor by software.
Page 8
2007-10-15
TMP91FW60
2. CPU
The TMP91FW60 incorporates a high-performance 16-bit CPU (The 900/L1-CPU). For CPU operation, see the
"TLCS-900/L1 CPU".
The following describe the unique function of the CPU used in the TMP91FW60; these functions are not covered
in the TLCS-900/L1 CPU section.
2.1 RESET
When resetting the TMP91FW60 microcontroller, ensure that the power supply voltage is within the operating
voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level
at least for 10 system clocks (1us at 20 MHz).
Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that
the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system
clocks.
It means that the system clock mode fSYS is set to fc/2.
When the reset is accept, the CPU:
1. Sets as follows the program counter (PC) in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
- PC (7:0)
<- Value at FFFF00H address
- PC (15:8)
<- Value at FFFF01H address
- PC (23:16) <- Value at FFFF02H address
2. Sets the stack pointer (XSP) to 100H.
3. Sets bits<IFF2:0> of the status register (SR) to 111 (Sets the interrupt level mask register to level 7).
4. Sets the <MAX> bit of the status register (SR) to 1 (MAX mode).
5. Clears bits<RFP2:0> of the status register (SR) to 000 (Sets the register bank to 0).
When reset is released, the CPU starts executing instructions in accordance with the program counter settings.
CPU internal registers not mentioned above do not change when the reset is released.
When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows.
1. Initializes the internal I/O registers.
2. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output
port mode.
3. Sets ALE pin to high impedance.
Note 1: The CPU internal register (except to PC, SR, XSP in CPU) and internal RAM data do not change by resetting.
Note 2: It is necessary to re-set up a stack pointer XSP by the user program.
Figure 2-1 is a reset timing chart of the TMP91FW60.
Page 9
2007-10-15
Page 10
P00~P07, P10~P17,
P20~P27, P60~P67,
P70~P75, P80~P87,
P90~P97, PA0~PA3
PB0~PB3
PZ2,PZ3, P40~P43
PZ0∼PZ1
HWR
Data-out
2WNNWR
+PVGTPCN
*KIJKORGFCPEG
Address
Address
Address
Address
Sampling
(input mode)
(input mode)
(output mode)
(P32 input mode)
(P31 output mode)
(P00 to P07, P10 to P17 input mode)
(P30 output mode)
(P00 to P07, P10 to P17 input mode)
(P44 input mode)
(PZ3 input mode)
(P40 to P43 input mode)
(P20 to P27 input mode)
Sampling
#HVGTTGUGVTGNGCUGFUVCTVKPIYCKVU
TGCFE[ENG
4GCF
WR
AD0~AD15
RD
AD0~AD15
ALE
R/W
CS0∼CS3
A16~A23
RESET
fFPH
TMP91FW60
9TKVG
Figure 2-1 TMP91FW60 Reset Timing Chart
2007-10-15
TMP91FW60
2.2 Memory Map
Figure 2-2 is a memory map of the TMP91FW60.
000000H
Internal I/O
(4 Kbytes)
(n)
000100H
001000H
64 Kbyte area
(nn)
Internal RAM
(8 Kbytes)
003000H
010000H
16-Mbyte area
(R)
(−R)
(R+)
(R + R8/16)
(R + d8/16)
(nnn)
FE0000H
128 Kbyte
FFFF00H
FFFFFFH
Figure 2-2 TMP91FW60 Memory Map
Page 11
2007-10-15
TMP91FW60
2.3 System Clock Function and Standby Control
TMP91FW60 contains a clock gear, stand-by controller and noise-reduction circuit. It is used for low-noise systems.
The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode
(X1,X2,XT1 and XT2 pins).
Figure 2-3 shows a transition figure.
IDLE2 mode
(I/O operate)
IDLE1 mode
+PUVTWEVKQP
+PVGTTWRV
+PUVTWEVKQP
+PVGTTWRV
4GUGV
(fOSCH/2)
4GNGCUG
NORMAL mode
(fOSCH /gear value/2)
+PUVTWEVKQP
+PVGTTWRV
STOP mode
(Stops All circuits)
(Operate only oscillator)
(a) Single clock mode transition figure
IDLE2 mode
(I/O operate)
IDLE1 mode
+PUVTWEVKQP
+PVGTTWRV
+PUVTWEVKQP
+PVGTTWRV
NORMAL mode
IDLE1 mode
+PUVTWEVKQP
+PVGTTWRV
+PUVTWEVKQP
+PVGTTWRV
+PUVTWEVKQP
(fOSCH /gear value/2)
(Operate only oscillator)
IDLE2 mode
(I/O operate)
4GUGV
(fOSCH/2)
4GNGCUG
+PUVTWEVKQP
SLOW mode
(fs/2)
+PVGTTWRV
STOP mode
(Stops All circuits)
+PUVTWEVKQP
(Operate only oscillator)
(b) Dual clock mode transition figure
Figure 2-3 TMP91FW60 Clock Operating Mode
Note: The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and
XT2 pins is called fs. The clock frequency selected by SYSCR1<SYSCK> is called fFPH. The system clock fSYSis
defined as the divided clock of fFPH, and one cycle of fSYS is regret to as one state.
Page 12
2007-10-15
TMP91FW60
2.3.1
Block Diagram of System Clock
SYSCR0<WUEF>
SYSCR2<WUPTM1:0>
SYSCR0
<PRCK1>
Warm-up timer
(for high/low frequency oscillator)
φT0
fc/16
fFPH
SYSCR0
<XTEN, RXTEN>
XT1
XT2
÷4
fs
fFPH
Lowfrequency
oscillator
fs
¸2
fc
fSYS
fc/2
fc/4
SYSCR0
<XEN, RXEN>
X1
X2
SYSCR1<SYSCK>
fc/8
fc/16
÷ ÷ ÷ ÷
High
frequency
oscillator fOSCH
%NQEMIGCT
fSYS
SYSCR1<GEAR2:0>
CPU
TMRA01 to TMRA45
φT0
ROM
Prescaler
RAM
TMRB0 toTMRB4
+PVGTTWRV
EQPVTQNNGT
Prescaler
WDT
I/O port
SIO0 to SIO2
ADC
Prescaler
SBI0 to SBI1
Prescaler
46%
fs
Binary
counter
SYSCR2<SCOSEL>
P40
f 5;5
Figure 2-4 Block Diagram of System Clock
Page 13
2007-10-15
TMP91FW60
2.3.2
Table 2-1
SFR
SFR for System Clock
Bit Symbol
7
6
5
4
3
2
1
0
XEN
XTEN
RXEN
RXTEN
RSYSCK
WUEF
PRCK1
−
Read/Write
After reset
1
0
1
0
SYSCK
GEAR2
0
0
Bit Symbol
−
−
−
−
Read/Write
−
−
−
−
After reset
−
−
−
−
SYSCR1
(00E1H)
Function
−
−
−
−
SCOSEL
WUPTM1
WUPTM0
Bit Symbol
−
−
After reset
−
SYSCR2
(00E2H)
Function
−
Select
SCOUT
0:fs
1:fSYS
1
0
Select warm-up time for
oscillator
00:218/inputted frequency
01:28/inputted frequency
10:214/inputted frequency
11:216/inputted frequency
−
Select prescaler clock
0:fFPH
1:fc/16
GEAR1
GEAR0
0
0
R/W
Select system clock
0: fc
1: fs
Select gear value of high frequency (fc)
000:fc
001:fc/2
010:fc/4
011:fc/8
100:fc/16
101:reserved
110:reserved
111:reserved
HALTM1
HALTM0
R/W
0
0
Selects
clock after
release of
STOP mode
0:fc
1:fs
Lowfrequency
oscillator
0:Stop
1:Oscillation
Read/Write
0
Lowfrequency
oscillator
(fs) after
release of
STOP mode
0:Stop
1:Oscillation
Highfrequency
oscillator
0:Stop
1:Oscillation
Function
0
Warm-up
timer control
0 Write:
Don't care
1 Write:
Start warmup
0 Read:
End warmup
1 Read:
Do not end
warm-up
Highfrequency
oscillator
(fc) after
release of
STOP mode
0:Stop
1:Oscillation
SYSCR0
(00E0H)
−
R/W
1
HALT mode
00:reserved
01:STOP mode
10:IDLE1 mode
11:IDLE2 mode
1
−
DRVE
−
R/W
−
0
−
Pin state
control in
STOP mode
0: I/O off
1: Remains
the state
before HALT
Note 1: "-" = Don’t care
Note 2: SYSCR0<bit0>,SYSCR1<bit 7:4>,SYSCR2<bit7,bit1> are read as undefined value.
Note 3: As for the serial channels SIO0, SIO1 and SIO2, a baud rate generator is unavailable as an input clock of an I/O interface
and a clock for a serial transfer if a prescaler clock is set to fc/16 when SYSCR0<PRCK1> is "1".
Page 14
2007-10-15
TMP91FW60
2.3.3
System Clock Controller
The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O.It
contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register
SYSCR1<SYSCK> changes the system clock to either fc or fs, SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator, and SYSCR1<GEAR2:0> sets the high-frequency clock gear to
either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the
equipment in which the device is installed.
The combination of settings <XEN> = "1", <XTEN> = "0", <SYSCK> = "0" and <GEAR2:0> = "000" will
cause the system clock (fSYS) to be set to fc/2 (=fc x 1/2) after a Reset. For example, fSYS is set to 8 MHz when
the 16 MHz oscillator connected to the X1 and X2 pins.
(1) Switching from NORMAL mode to SLOW mode
When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer
can be used to change the operation frequency after stable oscillation has been attained.
The warm-up time can be selected using SYSCR2<WUPTM1:0>.
This warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2.
Table 2-2 shows the warm-up time.
Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed.
Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up
time.
Note 3: Note of using low-frequency oscillator
When connect low-frequency oscillator to ports 96 and 97, need below setting for cut consumption power.
(Case of resonators)
Set P9CR<P96C, P97C> = "11", P9<P96:97> = "00"
(Case of oscillator)
Set P9CR<P96C, P97C> = "11", P9<P96:97> = "10"
Table 2-2 Warm-up Times (when changing clock)
Select Warm-up Time
SYSCR2<WUPTM1:0>
Change to NORMAL (fc)
Change to SLOW (fs)
01(28/frequency)
12.8[us]
7.8[ms]
10(214/frequency)
0.819[ms]
500[ms]
11(216/frequency)
3.277[ms]
2000[ms]
00(218/frequency)
13.107[ms]
8000[ms]
Note: At fOSCH=20MHz，fs=32.768kHz
Page 15
2007-10-15
TMP91FW60
Example 1:
Changing from high frequency (fc) to low frequency (fs).
SYSCR0
EQU
00E0H
SYSCR1
EQU
00E1H
SYSCR2
EQU
00E2H
LD
(SYSCR2),X-11--X-B
;
Sets warm-up time to 216/fs.
SET
6,(SYSCR0)
;
Enables low-frequency oscillation.
SET
2,(SYSCR0)
;
Clears and starts warm-up timer.
BIT
2,(SYSCR0)
;
JR
NZ,WUP
;
SET
3,(SYSCR1)
;
Changes fSYS from fc to fs.
RES
7,(SYSCR0)
;
Disables high-frequency oscillation.
WUP:
Detects stopping of warm-up timer.
Note: X: Don’t care, -:No change
<XEN>
X1 and X2 pins
<XTEN>
XT1 and XT2 pins
Counts up by fSYS
Counts up by fs
<SYSCK>
fSYS
Figure 2-5 Changing from high frequency (fc) to low frequency (fs)
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TMP91FW60
Example 2:
Changing from low frequency (fs) to high frequency (fc).
SYSCR0
EQU
00E0H
SYSCR1
EQU
00E1H
SYSCR2
EQU
00E2H
LD
(SYSCR2),X-10--X-B
;
Sets warm-up time to 214/fc.
SET
7,(SYSCR0)
;
Enables high-frequency oscillation.
SET
2,(SYSCR0)
;
Clears and starts warm-up timer.
BIT
2,(SYSCR0)
;
JR
NZ,WUP
;
RES
3,(SYSCR1)
;
Changes fSYS from fs to fc
RES
6,(SYSCR0)
;
Disables low-frequency oscillation.
WUP:
Detects stopping of warm-up timer.
Note: X: Don’t care, -:No change
<XEN>
X1 and X2 pins
<XTEN>
XT1 and XT2 pin2
Counts up by fSYS
Counts up by fc
<SYSCK>
fSYS
Figure 2-6 Changing from low frequency (fs) to high frequency (fc)
(2) Clock gear controller
When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> = "0", fFPH is set according
to the contents of the clock gear select register SYSCR1<GEAR2:0> to either fc, fc/2, fc/4, fc/8 or fc/16.
Using the clock gear to select a lower value of fFPH reduces power consumption.
Below show example of changing clock gear.
Page 17
2007-10-15
TMP91FW60
Example 3:
Changing to a clock gear
SYSCR1
EQU
00E1H
LD
(SYSCR1),XXXX0000B
;
Changes fSYS to fc/2.
X:Don’t care
(Clock gear changing)
To change the clock gear, write the register value to the SYSCR1<GEAR2:0> register. It is necessary the
warm-up time until changing after writing the register value.
There is the possibility that the instruction next to the clock gear changing instruction is executed by the
clock gear before changing. To execute the instruction next to the clock gear switching instruction by the clock
gear after changing, input the dummy instruction as follows (instruction to execute the write cycle).
SYSCR1
EQU
00E1H
LD
(SYSCR1),XXXX0000B
;
Changes fSYS to fc/2.
LD
(DUMMY),00H
;
Dummy instruction
Instruction to be executed after clock gear has changed.
(3)Internal clock output
The fSYS or fs internal clock can be driven out from the P40/SCOUT pin.
The P40/SCOUT pin is configured as SCOUT (System clock output) by programming the port 4 registers as follows: P4CR<P40C> = "1" and P4FC<P40F> = "1". The output clock is selected through the
SYSCR2<SCOSEL> bit.
Table 2-3 shows the pin states in each clocking mode when the P40/SCOUT pin is configured as
SCOUT.
Table 2-3
SCOUT Output States
HALT mode
NORMAL SLOW
IDLE2
<SCOSEL>="0"
<SCOSEL>="1"
2.3.4
The fs clock is driven out.
The fSYS clock is driven out.
IDLE1
STOP
HOLD at either "1"
or "0"
Prescaler Clock Controller
For the internal I/O (TMRA01 to TMRA45, TMRB0 to TMRB4, SIO0 to SIO2, SBI0, SBI1) there is a
prescaler which can divide the clock.
The φT0 clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 4.
The setting of the SYSCR0<PRCK1> register determines which clock signal is input.
Page 18
2007-10-15
TMP91FW60
2.3.5
Runaway provision with SFR protection register
(Purpose)
Provision in runaway of program by noise mixing.
Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in
the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller) is
changed.
Specified SFR list
1. CS/WAIT controller
B0CS, B1CS, B2CS, B3CS, BEXCS,
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3
2. Clock gear (write enable only EMCCR1)
SYSCR0, SYSCR1, SYSCR2
(Block diagram)
EMCCR0<PROTECT>
S
R
Q
Write signal to SFR
(Setting method)
If writing except "1FH" code to EMCCR1 register, it become protect ON. By this operation, write operation
to specified SFR is disabling.
If writing "1FH" to EMCCR1 register, it become protect OFF. State of protect can to confirm by reading
EMCCR0<PROTECT>.
Table 2-4
EMCCR0
(00E3H)
SFR for EMCCR
7
6
5
4
Bit Symbol
PROTECT
−
−
−
Read/Write
R
After reset
0
Function
Protect flag
0: OFF
1: ON
3
2
1
0
−
−
−
−
0
1
1
R/W
0
Write "0".
1
0
Write "1".
Write "0".
0
Write "0".
Write "0".
Write "1".
Write "1".
Bit Symbol
EMCCR1
(00E4H)
Read/Write
After reset
Protect OFF by writing "1FH".
Protect ON by writing except "1FH".
Function
Page 19
2007-10-15
TMP91FW60
2.3.6
Standby Controller
(1)HALT modes
When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode,
depending on the contents of the SYSCR2<HALTM1:0> register.
The subsequent actions performed in each mode are as follows:
1. IDLE2: Only the CPU halts.
The internal I/O is available to select operation during IDLE2 mode by setting the following register.
Shows the registers of setting operation during IDLE2 mode.
Table 2-5 SFR Setting Operation during IDLE2 Mode
Internal I/O
SFR
Internal I/O
SFR
TMRA01
TA01RUN<I2TA01>
SIO0
SC0MOD1<I2S0>
TMRA23
TA23RUN<I2TA23>
SIO1
SC1MOD1<I2S1>
TMRA45
TA45RUN<I2TA45>
SIO2
SC2MOD1<I2S2>
TMRB0
TB0RUN<I2TB0>
SBI0
SBI0BR<I2SBI0>
TMRB1
TB1RUN<I2TB1>
SBI1
SBI1BR<I2SBI1>
TMRB2
TB2RUN<I2TB2>
AD
ADCCR2<I2AD>
TMRB3
TB3RUN<I2TB3>
WDT
WDMOD<I2WDT>
TMRB4
TB4RUN<I2TB4>
2. IDLE1: Only the oscillator and the RTC (Real time clock) continue to operate.
3. STOP: All internal circuits stop operating.
The operation of each of the different HALT modes is described in Table 2-6.
Table 2-6 I/O Operation during HALT Modes
HALT mode
IDLE2
IDLE1
STOP
SYSCR2<HALTM1:0>
11
10
01
Stop
CPU
I/O port
Keep the state when the HALT instruction was
executed.
See Table 2-9
TMRA,TMRB
Block RTC
SIO,SBI
Operate enable
Available to select
operation block
AD
Stop
WDT
Interrupt controller
Operate
Page 20
2007-10-15
TMP91FW60
(2)How to release the HALT mode
These halt states can be released by resetting or requesting an interrupt. The halt release sources are
determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT
modes. The details for releasing the halt status are shown in Table 2-7.
Released by requesting an interrupt
The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of interrupt mask register,
the interrupt due to the source is processed after releasing the HALT mode, and CPU status executing an
instruction that follows the HALT instruction. When the interrupt request level set before executing the
HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not
executed. (In non-maskable interrupts, interrupt processing is processed after releasing the HALT mode
regardless of the value of the mask register.) However only for INT0 and RTC interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask
register, releasing the HALT mode is executed. In this case, interrupt processing, and CPU starts executing the instruction next to the HALT instruction, but the interrupt request flag is held at "1".
Note:Usually, interrupts can release all halts status. However, the interrupts (NMI, INT0, INTRTC) which can release
the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode
(for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an
interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode
completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of
the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other
interrupt.
Releasing by resetting
Releasing all halt status is executed by resetting.
When the STOP mode is released by RESET, it is necessary enough resetting time (See Table 2-6)to set
the operation of the oscillator to be stable.
When releasing the HALT mode by resetting, the internal RAM data keeps the state before the "HALT"
instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps
the state before the "HALT" instruction is executed.)
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TMP91FW60
Table 2-7 Source of Halt State Clearance and Halt Clearance Operation
Status of Received Interrupt
Interrupt
Source of Halt state clearance
HALT mode
Interrupt Enable
(Interrupt level)
≥ (Interrupt mask)
Interrupt Disable
(Interrupt level) < (Interrupt mask)
IDLE2
IDLE1
STOP
IDLE2
IDLE1
STOP
NMI
♦
♦
♦*1
-
-
-
INTWDT
♦
×
×
-
-
-
INT0(Note 1)
♦
♦
♦*1
Ο
Ο
Ο*1
INTRTC
♦
♦
×
Ο
Ο
×
♦(Note 2)
×
×
×
×
×
INTTA0-INTTA5
♦
×
×
×
×
×
INTTB00-40,INTTB01-41
♦
×
×
×
×
×
INTTB0F0-4
♦
×
×
×
×
×
INTRX0-INTRX2,TX0-TX2
♦
×
×
×
×
×
INTSBI0-1
♦
×
×
×
×
×
INTAD
♦
×
×
×
×
×
INT1-INT10
RESET
Initialize LSI
♦:After clearing the HALT mode, CPU starts interrupt processing.
Ο:After clearing the HALT mode, CPU resumes executing starting from instruction following the
HALT instruction. (Interrupt routine don't execute.)
×:It can not be used to release the HALT mode.
- :The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest
priority level. There is not this combination type.
*1:Releasing the HALT mode is executed after passing the warm-up time.
Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold
high level until starting interrupt process. If low level was set before interrupt process is stared, interrupt
process is not started correctly.
Note 2: If using external interrupt INT1 to INT10 in IDLE2 mode, set 16-bit timer RUN register TB0RUN<I2TB0>,
TB1RUN<I2TB1>, TB2RUN<I2TB2>, TB3RUN<I2TB3>, TB4RUN<I2TB4> to "1".
Page 22
2007-10-15
TMP91FW60
Example:Clearing halt state
An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
#FFTGUU
8203H
8206H
8209H
820BH
820EH
LD
LD
EI
LD
HALT
(IIMC), 00H
(INTE0AD), 06H
5
(SYSCR2), 28H
; Selects INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets CPU interrupt level to 5.
; Sets HALT mode to IDLE1 mode.
; Halts CPU.
INT0 interrupt routine
INT0
RETI
820FH
LD
XX, XX
(3)Operation
1. IDLE2 mode
In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can
take place. Instruction execution by the CPU stops.
Figure 2-7 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt.
X1
A0~A23
ALE
AD0~AD15
Address
Data
Address
Address
Data
RD
WR
IDLE2
Figure 2-7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt
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TMP91FW60
2. IDLE1 mode
In IDLE1 mode, only the internal oscillator and the RTC continue to operate. The system clock in the
MCU stops.
In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (e.g., restart of operation) is synchronous with it.
Figure 2-8 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt.
X1
A0∼A23
ALE
AD0∼AD15
Address
Address
Data
Data
RD
WR
IDLE1 mode
Figure 2-8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt
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TMP91FW60
3. STOP mode
When STOP mode is selected, all internal circuits stop, including the internal oscillator. Pin status in
STOP mode depends on the settings in the SYSCR2<DRVE> register. Table 2-9 summarizes the state of
these pins in STOP mode.
After STOP mode has been cleared, system clock output starts when the warm-up time has elapsed, in
order to allow oscillation to stabilize. After STOP mode has been cleared, either NORMAL mode or
SLOW mode can be selected using the SYSCR0<RSYSCK> register. Therefore, <RSYSCK>, <RXEN>
and <RXTEN> must be set. See the sample warm-up times in Table 2-8.
Figure 2-9 illustrates the timing for clearance of the STOP mode halt state by an interrupt.
X1
A0∼A23
ALE
AD0∼AD15
Address
Data
Address
Data
RD
WR
STOP
Figure 2-9 Timing Chart for STOP Mode Halt State Cleared by Interrupt
Table 2-8 Sample Warm-up Times after Clearance of STOP Mode
SYSCR2<WUPTM1:0>
SYSCR0
<RSYSCK>
01(28)
10(214)
11(216)
00(218)
0(fc)
12.8us
0.819ms
3.277ms
13.107ms
1(fs)
7.8ms
500ms
2000ms
8000ms
Note: fOSCH=20MHz, fs=32.768kHz
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TMP91FW60
Example:
"The STOP mode is entered when the low-frequency operates, and high-frequency operates after releasing due to NMI.
SYSCR0
SYSCR1
SYSCR2
8FFDH
EQU
EQU
EQU
LD
00E0H
00E1H
00E2H
(SYSCR1), 08H
;
9000H
LD
(SYSCR2), X−1001X1B
;
9002H
LD
(SYSCR0), 011000 − −B
;
9005H
HALT
fSYS = fs/2
214/fOSCH
NMI
NMI
9006H
LD
XX, XX
RETI
−: No change
Note:When different modes are used before and after STOP mode as the above mentioned, there is possible to
release the HALT mode without changing the operation mode by acceptance of the halt release interrupt
request during execution of "HALT" instruction (during 6 state). In the system which accepts the interrupts during execution "HALT" instruction, set the same operation mode before and after the STOP mode.
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TMP91FW60
Table 2-9 Input/output Buffer State Table
Port Name
-:
Input / Output
<DRVE>=0
<DRVE>=1
P00-07
input mode
output mode
AD0-AD7
-
output
-
P10-17
input mode
output mode
AD8-AD15
-
output
-
P20-27
input mode
output mode,A0-A7/A16-A23
-
output
PZ0(RD),PZ1(WR)
output
-
output
PZ2(HWR),PZ3(R/W)
input mode
output mode
PU*
PU*
PU*
output
P30-33
input mode
output mode
-
output
P40-44
input mode
output mode
PU*
PU*
PU*
output
P50-57
input mode
output mode
analog input
-
output
-
P60-67
input mode
output mode
analog input
-
output
-
P70-74
input mode
output mode
-
input
output
P75
input mode
output mode
input
-
input
output
P80-87
input mode
output mode
-
output
P90-97
input mode
output mode
-
output
PA0-A3
input mode
output mode
-
output
PB0-B3
input mode
output mode
-
output
NMI
input
input
input
RESET
input
input
input
AM0,AM1
input
input
input
X1
input
-
-
X2
output
"H" level output
"H" level output
Input for input mode / input pins is invalid; output mode / output pin is at high impedance.
input: Input gate in operation. Fix input voltage to "L" or "H" so that input pin stays constant.
output: Output state
PU*: Programmable pull-up pin. Input gate disable state. No through current even if the pin is
set high impedance.
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TMP91FW60
3. Interrupts
Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in interrupt controller.
The TMP91FW60 has a total of 57 interrupts divided into the following three types:
• Interrupts generated by CPU: 9 sources
(Software interrupts, illegal instruction interrupt)
• Interrupts on external pins (NMI, INT0 to INT10): 12 sources
• Internal interrupts: 36 sources
A (fixed) individual interrupt vector number is assigned to each interrupt.
One of six (Variable) priority level can be assigned to each maskable interrupt.
The priority level of non-maskable interrupts are fixed at 7 as the highest level.
When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. If multiple
interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the
CPU. (The highest priority is level 7 using for non-maskable interrupts.)
The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register <IFF2:0>.
If the priority level of the interrupt is higher than the value of the interrupt mask register, the CPU accepts the interrupt.
The interrupt mask register <IFF2:0> value can be updated using the value of the EI instruction ("EI num" sets
<IFF2:0> data to num).
For example, specifying "EI3" enables the maskable interrupts which priority level set in the interrupt controller is
3 or higher, and also non-maskable interrupts.
Operationally, the DI instruction (<IFF2:0> "7") is identical to the "EI7" instruction. DI instruction is used to disable maskable interrupts because of the priority level of maskable interrupts is 0 to 6. The EI instruction is valid
immediately after execution.
In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a micro DMA interrupt
processing mode as well. The CPU can transfer the data (1/2/4 bytes) automatically in micro DMA mode, therefore
this mode is used for speed-up interrupt processing, such as transferring data to the internal or external peripheral I/
O. Moreover, TMP91FW60 has software start function for micro DMA processing request by the software not by
the hardware interrupt.
Figure 3-1 shows the overall interrupt processing flow.
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2007-10-15
TMP91FW60
Interrupt processing
Interrupt
specified by micro DMA
start vector?
Yes
Micro DMA soft start
request
No
Interrupt vector value "V"
read
Interrupt request F/F clear
General-purpose
interrupt
processing
PUSH
PUSH
SR<IFF2:0>
INTNEST
PC
PC
SR
Level of accepted
interrupt + 1
INTNEST + 1
Clear interrupt request flag
Data transfer by
micro DMA
Count
Count − 1
Micro DMA processing
Yes
(FFFF00H + V)
Count = 0
No
Clear vector register
generating micro DMA
transfer and interrupt
(INTTC0 to INTTC3)
Interrupt processing
program
RETI instruction
POP SR
POP PC
INTNEST − 1
INTNEST
End
Figure 3-1 Overall Interrupt Processing Flow
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TMP91FW60
3.1 General-purpose Interrupt Processing
When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same
as TLCS-900/L and TLCS-900/H.
1. The CPU reads the interrupt vector from the interrupt controller.
If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in
accordance with the default priority and clears the interrupt request.
(The default priority is already fixed for each interrupt. The smaller vector value has the higher priority
level.)
2. The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (Indicated
by XSP).
3. The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask
register <IFF2:0>. However, if the priority level of the accepted interrupt is 7, the register’s value is set to
7.
4. The CPU increases the interrupt nesting counter INTNEST by 1 (+1).
5. The CPU jumps to the address indicated by the data at address “FFFF00H + Interrupt vector” and starts the
interrupt processing routine.
The above processing time is 18 states (1.8 μs at 20 MHz) as the best case (16-bit data bus width and 0 waits).
When the CPU completed the interrupt processing, use the RETI instruction to return to the main routine. RETI
restores the contents of program counter (PC) and status register (SR) from the stack and decreases the interrupt
nesting counter INTNEST by 1 (−1).
Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or
disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of
0 or 7 will disable an interrupt request.)
If an interrupt request which has a priority level equal to or greater than the value of the CPU interrupt mask register <IFF2:0> comes out, the CPU accepts its interrupt. Then, the CPU interrupt mask register <IFF2:0> is set to the
value of the priority level for the accepted interrupt plus 1 (+1).
Therefore, if an interrupt is generated with a higher level than the current interrupt during its processing, the CPU
accepts the later interrupt and goes to the nesting status of interrupt processing.
Moreover, if the CPU receives another interrupt request while performing the said 1. to 5. processing steps of the
current interrupt, the latest interrupt request is sampled immediately after execution of the first instruction of the current interrupt processing routine. Specifying DI as the start instruction disables maskable interrupt nesting.
A reset initializes the interrupt mask register <IFF2:0> to “111”, disabling all maskable interrupts.
Table 3-1 shows the TMP91FW60 interrupt vectors and micro DMA start vectors. The address FFFF00H to
FFFFFFH (256 bytes) is assigned for the interrupt vector area.
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TMP91FW60
Table 3-1 TMP91FW60 Interrupt Vectors Table(1/2)
Default Priority
Type
Interrupt Source and Source of Micro DMA Request
Vector Value
(V)
Vector Reference Address
Micro DMA
Start Vector
1
“Reset” or “SWI 0” instruction
0000H
FFFF00H
–
2
“SWI 1” instruction
0004H
FFFF04H
–
3
INTUNDEF: Illegal instruction or “SWI 2” instruction
0008H
FFFF08H
–
4
“SWI 3” instruction
000CH
FFFF0CH
–
“SWI 4” instruction
0010H
FFFF10H
–
“SWI 5” instruction
0014H
FFFF14H
–
7
“SWI 6” instruction
0018H
FFFF18H
–
8
“SWI 7” instruction
001CH
FFFF1CH
–
9
NMI:NMI pin
0020H
FFFF20H
–
10
INTWD: Watchdog timer
0024H
FFFF24H
–
–
Micro DMA (MDMA)
–
–
–
11
INT0: INT0 pin
0028H
FFFF28H
0AH
12
INT1: INT1 pin
002CH
FFFF2CH
0BH
13
INT2: INT2 pin
0030H
FFFF30H
0CH
14
INT3: INT3 pin
0034H
FFFF34H
0DH
15
INT4: INT4 pin
0038H
FFFF38H
0EH
16
INT5: INT5 pin
003CH
FFFF3CH
0FH
17
INT6: INT6 pin
0040H
FFFF40H
10H
18
INT7: INT7 pin
0044H
FFFF44H
11H
19
INT8: INT8 pin
0048H
FFFF48H
12H
20
INT9: INT9 pin
004CH
FFFF4CH
13H
21
INT10: INT10 pin
0050H
FFFF50H
14H
22
INTTA0: 8-bit timer 0
0054H
FFFF54H
15H
INTTA1: 8-bit timer 1
0058H
FFFF58H
16H
24
INTTA2: 8-bit timer 2
005CH
FFFF5CH
17H
25
INTTA3: 8-bit timer 3
0060H
FFFF60H
18H
26
INTTA4: 8-bit timer 4
0064H
FFFF64H
19H
27
INTTA5: 8-bit timer 5
0068H
FFFF68H
1AH
28
INTTB00: 16-bit timer 0 (TB0RG0)
006CH
FFFF6CH
1BH
29
INTTB01: 16-bit timer 0 (TB0RG1)
0070H
FFFF70H
1CH
30
INTTB10: 16-bit timer 1 (TB1RG0)
0074H
FFFF74H
1DH
31
INTTB11: 16-bit timer 1 (TB1RG1)
0078H
FFFF78H
1EH
32
INTTB20: 16-bit timer 2 (TB2RG0)
007CH
FFFF7CH
1FH
33
INTTB21: 16-bit timer 2 (TB2RG1)
0080H
FFFF80H
20H
34
INTTB30: 16-bit timer 3 (TB3RG0)
0084H
FFFF84H
21H
35
INTTB31: 16-bit timer 3 (TB3RG1)
0088H
FFFF88H
22H
36
INTTB40: 16-bit timer 4 (TB4RG0)
008CH
FFFF8CH
23H
37
INTTB41: 16-bit timer 4 (TB4RG1)
0090H
FFFF90H
24H
5
6
Nonmaskable
23
Maskable
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TMP91FW60
Table 3-1 TMP91FW60 Interrupt Vectors Table(2/2)
Default Priority
Type
Interrupt Source and Source of Micro DMA Request
Vector Value
(V)
Vector Reference Address
Micro DMA
Start Vector
38
INTTBOF0: 16-bit timer 0 (Over flow)
0094H
FFFF94H
25H
39
INTTBOF1: 16-bit timer 1 (Over flow)
0098H
FFFF98H
26H
40
INTTBOF2: 16-bit timer 2 (Over flow)
009CH
FFFF9CH
27H
41
INTTBOF3: 16-bit timer 3 (Over flow)
00A0H
FFFFA0H
28H
42
INTTBOF4: 16-bit timer 4 (Over flow)
00A4H
FFFFA4H
29H
43
INTRX0:Serial reception (Channel 0)
00A8H
FFFFA8H
2AH
44
INTTX0:Serial transmission (Channel 0)
00ACH
FFFFACH
2BH
45
INTRX1:Serial reception (Channel 1)
00B0H
FFFFB0H
2CH
46
INTTX1:Serial transmission (Channel 1)
00B4H
FFFFB4H
2DH
47
INTRX2:Serial reception (Channel 2)
00B8H
FFFFB8H
2EH
INTTX2:Serial transmission (Channel 2)
00BCH
FFFFBCH
2FH
49
INTSBI0:Serial bus interface interrupt (Channel 0)
00C0H
FFFFC0H
30H
50
INTSBI1:Serial bus interface interrupt (Channel 1)
00C4H
FFFFC4H
31H
51
INTRTC: Interrupt for special timer for CLOCK
00C8H
FFFFC8H
32H
52
INTAD: AD conversion end
00CCH
FFFFCCH
33H
53
INTTC0 Micro DMA end (Channel 0)
00D0H
FFFFD0H
–
54
INTTC1: Micro DMA end (Channel 1)
00D4H
FFFFD4H
–
55
INTTC2: Micro DMA end (Channel 2)
00D8H
FFFFD8H
–
56
INTTC3: Micro DMA end (Channel 3)
00DCH
FFFFDCH
–
(Reserved)
:
(Reserved)
00E0H
:
00FCH
FFFFE0H
:
FFFFFCH
–
:
48
Maskable
–
Note: Micro DMA default priority: Micro DMA stands up prior to other maskable interrupt.
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TMP91FW60
3.2 Micro DMA Processing
In addition to general-purpose interrupt processing, the TMP91FW60 supports a micro DMA function. Interrupt
requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable
interrupts, regardless of the priority level of the particular interrupt source. The micro DMA has 4 channels and is
possible continuous transmission by specifying the described later burst mode.
The micro DMA has 4 channels and is possible continuous transmission by specifying the described later burst
mode.
Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes
to a standby mode (STOP, IDLE1 and IDLE2) by HALT instruction, the requirement of micro DMA will be ignored
(Pending) and DMA transfer is started after release HALT.
3.2.1
Micro DMA Operation
When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA
triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite
of any interrupt source’s level. The micro DMA is ignored on <IFF2:0> = “7”.
The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of interrupts at any one
time. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared.
The data are automatically transferred once (1/2/4 bytes) from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decreased by 1 (−1). If the decreased
result is “0”, the micro DMA transfer end interrupt (INTTC0 to INTTC3) passes from the CPU to the interrupt
controller. In addition, the micro DMA start vector register DMAnV is cleared to 0, the next micro DMA is
disabled and micro DMA processing completes. If the decreased result is other than “0”, the micro DMA processing completes if it does not specify the described later burst mode. In this case, the micro DMA transfer
end interrupt (INTTC0 to INTTC3) aren’t generated.
If an interrupt request is triggered for the interrupt source in use during the interval between the clearing of
the micro DMA start vector and the next setting, general-purpose interrupt processing executes at the interrupt
level set. Therefore, if only using the interrupt for starting the micro DMA (Not using the interrupts as a general-purpose interrupt: Level 1 to 6), first set the interrupts level to 0 (Interrupt requests disabled).
If using micro DMA and general-purpose interrupts together, first set the level of the interrupt used to start
micro DMA processing lower than all the other interrupt levels. (Note) In this case, the cause of general interrupt is limited to the edge interrupt.
The priority of the micro DMA transfer end interrupt (INTTC0 to INTTC3) is defined by the interrupt level
and the default priority as the same as the other maskable interrupt.
If a micro DMA request is set for more than one channel at the same time, the priority is not based on the
interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > Channel 3 (Low)).
While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this
register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (The
upper eight bits of the 32 bits are not valid).
Note:If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.
In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt
specified by micro DMA start vector" (in the Figure 3-1) and reading interrupt vector with setting below, the
vector shifts to that of INTyyy at the time.
This is because the priority level of INTyyy is higher than that of INTxxx.
In the interrupt routine, CPU reads the vector of INTyyy because checking of micro DMA has been finished.
And INTyyy is generated regardless of transfer counter of micro DMA.
INTxxx: level 1 without micro DMA
INTyyy: level 6 with micro DMA
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TMP91FW60
Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One-word) transfer, and 4-byte
transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or
remain unchanged.
This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details
of the transfer modes, see" 3.2.4 Detailed Description of the Transfer Mode Register ".
As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to
0000H.)
Micro DMA processing can be started by the 42 interrupts shown in the micro DMA start vectors of Table 31 and by the micro DMA soft start, making a total of 43 interrupts.
Figure 3-2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for
counter mode, the same as for other modes).
(The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination
addresses both even-numberd values).
(Note 1)
1 state
DM1
DM2
DM3
DM4
DM5
(Note 2)
DM6
DM7
DM8
X1
A0 to A23
Transfer source address
Transfer destination
address
RD
WR, HWR
D0 to D15
Input
Output
Figure 3-2 Timing for Micro DMA Cycle
States 1 to 3: Instruction fetch cycle (Gets next address code).
If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle
becomes a dummy cycle.
States 4 to 5: Micro DMA read cycle
State 6:
Dummy cycle (The address bus remains unchanged from state 5.)
States 7 to 8: Micro DMA write cycle
Note 1: If the source address area is an 8-bit bus, it is increased by two states.
If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two
states.
Note 2: If the destination address area is an 8-bit bus, it is increased by two states.
If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by
two states.
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TMP91FW60
3.2.2
Soft Start Function
In addition to starting the micro DMA function by interrupts, TMP91FW60 includes a micro DMA software
start function that starts micro DMA on the generation of the write cycle to the DMAR register.
Writing “1” to each bit of DMAR register causes micro DMA once (If write “0” to each bit, micro DMA
doesn’t operate) At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to
“0”.
Only one-channel can be set once for micro DMA. (Do not write “1” to plural bits.)
When writing again “1” to the DMAR register, check whether the bit is “0” before writing “1”. If read “1”,
micro DMA transfer isn’t started yet.
When a burst is specified by DMAB register, data is continuously transferred until the value in the micro
DMA transfer counter is “0” after start up of the micro DMA. If execute soft start during micro DMA transfer
by interrupt source, micro DMA transfer counter doesn’t change. Don’t use Read-modify-write instruction to
avoid writing to other bits by mistake.
Symbol
DMAR
3.2.3
Name
DMA
Request
Register
Address
7
6
5
4
3
2
1
0
89H
–
–
–
–
DMAR3
DMAR2
DMAR1
DMAR0
–
–
–
–
–
–
–
–
0
0
RMW
instructions
are prohibited.
R/W
0
0
DMA request
Transfer Control Registers
The transfer source address and the transfer destination address are set in the following registers in CPU.
Data setting for these registers is done by an “LDC cr, r” instruction.
Channel 0
DMA source address register 0: Only use LSB 24 bits
DMAS0
DMA destination address register 0: Only use LSB 24 bits
DMAD0
DMAC0
DMAM0
DMA counter register 0: 1 to 65536
DMA mode register 0
Channel 3
DMAS3
DMA source address register 3
DMAD3
DMA destination address register 3
DMAC3
DMAM3
DMA counter register 3
DMA mode register 3
8 bits
16 bits
32 bits
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TMP91FW60
3.2.4
Detailed Description of the Transfer Mode Register
(DMAM0 to DMAM3)
0
0
0
Mode
Note: The upper three bit of data programmed to these registers must always be 0.
Execution time
ZZ: 0 = Byte transfer, 1 = Word transfer, 2 = 4-byte transfer, 3 = Reserved
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Z
Z
Z
Z
Z
0
Z
Z
Z
Z
Z
0
Transfer destination address INC mode・・・・・・・・・・I/O to memory
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC is generated
Transfer destination address DEC mode ・・・・・・・・・I/O to memory
(DMADn-) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC is generated
Transfer source address INT mode・・・・・・・・・・・・memory to I/O
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC is generated
Transfer source address DEC mode ・・・・・・・・・・・memory to I/O
(DMADn) ← (DMASn-)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC is generated
Address fixed mode・・・・・・・・・・・・・・・・・・・・・I/O to I/O
(DMADn) ← (DMASn)
DMACn ← DMACn − 1
if DMACn = 0 then INTTC is generated
Counter mode for counting number of times interrupt is generated
DMASn ← DMASn + 1
DMACn ← DMACn − 1
if DMACn = 0 then INTTC is generated
8 states (800 ns)
@ byte/word transfer
12 states (1200 ns)
@ 4-byte/word transfer
8 states (800 ns)
@ byte/word transfer
12 states (1200 ns)
@ 4-byte/word transfer
8 states (800 ns)
@ byte/word transfer
12 states (1200 ns)
@ 4-byte/word transfer
8 states (800 ns)
@ byte/word transfer
12 states (1200 ns)
@ 4-byte/word transfer
8 states (800 ns)
@ byte/word transfer
12 states (1200 ns)
@ 4-byte/word transfer
5 states
(500 ns)
Note 1: “n” is the corresponding micro DMA channels 0 to 3.
DMADn+/DMASn+: Post-increment (Increment register value after transfer)
DMADn-/DMASn-: Post-decrement (Decrement register value after transfer)
The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC)
addresses.
Note 2: Execution time is under the condition of:
16-bit bus width (Both transfer and destination address area)/0 waits/
fc = 20 MHz/selected high-frequency mode (fc × 1)
Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the
above table.
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3.3 Interrupt Controller Operation
The block diagram in Figure 3-3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit.
For interrupt controller there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals.
The flag is cleared to 0 in the following cases:
• When reset occurs
• When the CPU reads the channel vector after accepted its interrupt
• When executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register)
• When the CPU receives a micro DMA request (when micro DMA is set)
• When the micro DMA burst transfer is terminated
An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE56). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable
interrupts (NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are
generated at the same time, the default priority is used to determine which interrupt request is accepted first.
The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus
whether an interrupt request for a given channel has occurred.
The interrupt controller sends the interrupt request and its vector address to the CPU. The CPU compares the priority value <IFF2:0> in the status register by the interrupt request signal with the priority value set; if the latter is
higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1 (+1) in the CPU
SR<IFF2:0>. Interrupt request where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine.
When interrupt processing is completed (after execution of the RETI instruction), the CPU restores the priority
value saved in the stack before the interrupt was generated to the CPU SR<IFF2:0>.
The interrupt controller also has registers (4 channels) used to store the micro DMA start vector. Writing the start
vector of the interrupt source for the micro DMA processing beforehand (see Table 3-1), enables the corresponding
interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter register
(e.g., DMAS and DMAD) prior to the micro DMA processing.
Page 37
2007-10-15
Micro DMA
counter
zero
interrupt
INTAD
INTTC0
INTTC1
INTTC2
INTTC3
INT1
INT2
INT3
INT0
INTWD
NMI
D Q
CLR
Q
Q
Page 38
INTTC0
Micro DMA start vector setting register
D5
D4
D3
42
D Q
D2
D1
6
CLR
D0
RESET
A
B
C
Y1
Y2
Y3
Y4
Y5
Y6
Decoder
S
DMA0V
DMA1V
DMA2V
DMA3V
Selector
Software
start
V = CCH
V = D0H
V = D4H
V = D8H
V = DCH
V = 28H
V = 2CH
V = 30H
6
V = 20H
V = 24H
Dn+3
Interrupt request F/F
Interrupt vector read
Micro DMA acknowledge
S
R
Interrupt request
F/F
Dn
Dn+1
Dn+2
RESET
S
R
Priority setting register
RESET
Interrupt
vector read
Interrupt request F/F
4
1
Interrupt controller
48
A
B
Micro DMA channel
priority encoder
0
1
2
3
Interrupt request
signal to CPU
2
Interrupt vector
read
D7
D6
D5
D4
D3
D2
D1
D0
3 INTRQ2 to INTRQ0
Interrupt
vector
generator
1
2 Highest A
priority
3 interrupt B
4 level
C
select
5
6
7
4 input OR
6
7
1
Priority
encoder
RESET
EI 1 to 7
DI
2
If IFF = 7 then 0
NMI
Micro DMA request
Halt release
During IDLE1
During STOP
Interrupt request
signal
Micro DMA channel
specification
RESET
INT0, INTRTC
IFF2 to 0
Interrupt
level detect
If INTRQ2 to 0
then 1.
3
3
IFF2:0
Interrupt
mask F/F
CPU
TMP91FW60
Figure 3-3 Block Diagram of Interrupt Controller
2007-10-15
TMP91FW60
3.3.1
Interrupt Level Setting Registers
Interrupt Level Setting Registers
Symbol
Name
Address
7
6
5
4
3
2
INTAD
INTE0AD
INT0 &
INTAD
enable
IADC
IADM2
IADM1
R
IADM0
I0C
R/W
I0M2
0
R
0
0
0
0
I2C
I2M2
I2M1
R
I2M0
I1C
I1M2
R/W
0
R
I4C
0
0
0
0
I4M2
I4M1
I4M0
I3C
R/W
I3M2
0
R
0
0
0
0
I6C
I6M2
I6M1
R
I6M0
I5C
R/W
I5M2
0
R
0
0
0
0
0
I5M1
I5M0
R/W
0
I8C
0
0
I7M1
I7M0
INT7
I8M2
I8M1
R
I8M0
I7C
R/W
I7M2
0
R
0
0
0
R/W
0
I10C
I10M2
0
0
I9M1
I9M0
INT9
I10M1
I10M0
I9C
I9M2
95H
R
R/W
0
R
0
0
0
INTTA1(TMRA1)
INTETA01
I3M0
94H
0
INTTA0 &
INTTA1
enable
I3M1
INT5
INT10
INTE910
0
93H
0
INT9 &
INT10
enable
0
R/W
INT8
INTE78
I1M0
INT3
R
0
INT7 &
INT8
enable
I1M1
R/W
INT6
INTE56
0
92H
0
INT5 &
INT6
enable
0
INT1
INT4
INTE34
I0M0
R/W
91H
0
INT3 &
INT4
enable
I0M1
INT0
INT2
INTE12
0
90H
0
INT1 &
INT2
enable
1
ITA1C
ITA1M2
ITA1M1
R/W
0
0
0
INTTA0 (TMRA0)
ITA1M0
ITA0C
ITA0M2
ITA0M1
ITA0M0
96H
R
0
R/W
0
R
0
0
0
R/W
0
0
0
IxxxC
Interrupt request flag
IxxM2
IxxM1
IxxM0
0
0
0
Disables interrupt requests
0
0
1
Sets interrupt priority level to 1
0
1
0
Sets interrupt priority level to 2
0
1
1
Sets interrupt priority level to 3
1
0
0
Sets interrupt priority level to 4
1
0
1
Sets interrupt priority level to 5
1
1
0
Sets interrupt priority level to 6
1
1
1
Disables interrupt requests
Page 39
Function (Write)
2007-10-15
TMP91FW60
Interrupt Level Setting Registers
Symbol
Name
Address
7
6
5
4
3
2
INTTA3 (TMRA3)
INTETA23
INTTA2 &
INTTA3
enable
ITA3C
ITA3M2
INTTA2 (TMRA2)
ITA3M1
R
ITA3M0
ITA2C
R/W
ITA2M2
0
0
0
0
0
ITA5C
ITA5M2
ITA5M1
R
ITA5M0
ITA4C
ITA4M2
R/W
ITB01C
0
0
ITB01M2
0
R/W
0
0
ITB01M0
ITB00C
R/W
ITB11C
0
0
ITB11M2
0
0
0
ITB11M0
ITB10C
R/W
0
0
0
0
ITB10M2
ITB10M1
ITB10M0
R/W
0
0
ITB21C
ITB21M2
0
0
INTTB20(TMRB2)
ITB21M1
R
ITB21M0
ITB20C
R/W
ITB20M2
ITB20M1
0
R
0
0
ITB20M0
R/W
0
0
ITB31C
ITB31M2
0
0
INTTB30(TMRB3)
ITB31M1
ITB31M0
ITB30C
ITB30M2
ITB30M1
ITB30M0
9CH
R
R/W
0
R
0
0
R/W
0
0
ITB41C
ITB41M2
0
0
INTTB40(TMRB4)
ITB41M1
ITB41M0
ITB40C
ITB40M2
ITB40M1
ITB40M0
9DH
R
R/W
0
R
0
0
0
INTTBOF1(TMRB1 Over flow)
INTETB01V
ITB00M0
9BH
0
Interrupt
enable
TMRB0/1
(Over flow)
0
R
INTTB41(TMRB4)
INTETB4
ITB00M1
INTTB10(TMRB1)
ITB11M1
R
0
Interrupt
enable
TMRB4
ITB00M2
R/W
INTTB31(TMRB3)
INTETB3
0
9AH
0
Interrupt
enable
TMRB3
0
R
INTTB21(TMRB2)
INTETB2
ITA4M0
INTTB00(TMRB0)
ITB01M1
R
0
Interrupt
enable
TMRB2
ITA4M1
R
INTTB11(TMRB1)
INTETB1
0
99H
0
Interrupt
enable
TMRB1
0
INTTA4 (TMRA4)
INTTB01(TMRB0)
INTETB0
ITA2M0
R/W
98H
0
Interrupt
enable
TMRB0
ITA2M1
R
INTTA5 (TMRA5)
INTETA45
0
97H
0
INTTA4 &
INTTA5
enable
1
ITF1C
ITF1M2
R/W
0
0
0
INTTBOF0(TMRB0 Over flow)
ITF1M1
ITF1M0
ITF0C
ITF0M2
ITF0M1
ITF0M0
9EH
R
0
R/W
0
R
0
0
0
R/W
0
0
0
IxxxC
Interrupt request flag
IxxM2
IxxM1
IxxM0
0
0
0
Disables interrupt requests
0
0
1
Sets interrupt priority level to 1
0
1
0
Sets interrupt priority level to 2
0
1
1
Sets interrupt priority level to 3
1
0
0
Sets interrupt priority level to 4
1
0
1
Sets interrupt priority level to 5
1
1
0
Sets interrupt priority level to 6
1
1
1
Disables interrupt requests
Page 40
Function (Write)
2007-10-15
TMP91FW60
Interrupt Level Setting Registers
Symbol
Name
INTETB23V
Interrupt
enable
TMRB2/3
(Over flow)
Address
7
6
5
4
3
INTTBOF3(TMRB3 Over flow)
ITF3C
ITF3M2
ITF3M1
R
ITF3M0
ITF2C
R/W
ITF2M2
IRTCC
0
0
IRTCM2
0
0
0
IRTCM0
ITF4C
ITF4M2
R/W
0
0
0
0
R/W
0
ITX0C
ITX0M2
ITX0M1
R
ITX0M0
IRX0C
R/W
IRX0M2
ITX1C
0
0
ITX1M2
0
0
0
ITX1M0
IRX1C
IRX1M2
R/W
IRX1M1
IRX1M0
0
0
0
0
R/W
0
ITX2C
ITX2M2
0
0
IRX2M1
IRX2M0
INTRX2
ITX2M1
R
ITX2M0
IRX2C
R/W
IRX2M2
0
R
0
0
0
R/W
0
ISBI1C
ISBI1M2
0
0
ISBI0M1
ISBI0M0
INTSBI0
ISBI1M1
ISBI1M0
ISBI0C
ISBI0M2
A4H
R
R/W
0
R
0
0
0
R/W
0
ITC1C
ITC1M2
0
0
ITC0M1
ITC0M0
INTTC0
ITC1M1
ITC1M0
ITC0C
ITC0M2
A5H
R
R/W
0
R
0
0
0
R/W
0
INTTC3
INTETC23
0
A3H
0
INTTC2 &
INTTC3
enable
0
R
INTTC1
INTETC01
IRX0M0
R/W
INTRX1
ITX1M1
R
0
INTTC0 &
INTTC1
enable
IRX0M1
R
INTSBI1
INTESBI01
0
A2H
0
INTSBI0 &
INTSBI1
enable
0
INTRX0
INTTX2
INTES2
ITF4M0
A1H
0
INTRX2 &
INTTX2
enable
0
ITF4M1
R
INTTX1
INTES1
0
INTTBOF4(TMRB4 Over flow)
IRTCM1
R
0
INTRX1 &
INTTX1
enable
ITF2M0
R/W
INTTX0
INTES0
ITF2M1
R
A0H
0
INTRX0 &
INTTX0
enable
0
INTTBOF2(TMRB2 Over flow)
INTRTC
INTETB4VRTC
1
9FH
0
Interrupt
enable
TMRB4/
INTRTC
2
ITC3C
ITC3M2
0
0
ITC2M1
ITC2M0
INTTC2
ITC3M1
ITC3M0
ITC2C
ITC2M2
A6H
R
0
R/W
0
R
0
0
0
R/W
0
0
0
IxxxC
Interrupt request flag
IxxM2
IxxM1
IxxM0
0
0
0
Disables interrupt requests
0
0
1
Sets interrupt priority level to 1
0
1
0
Sets interrupt priority level to 2
0
1
1
Sets interrupt priority level to 3
1
0
0
Sets interrupt priority level to 4
1
0
1
Sets interrupt priority level to 5
1
1
0
Sets interrupt priority level to 6
1
1
1
Disables interrupt requests
Page 41
Function (Write)
2007-10-15
TMP91FW60
3.3.2
External Interrupt Control
External Interrupt Control Register (IIMC)
Symbol
Name
Address
7
6
5
4
3
2
1
0
–
–
–
–
–
I0EDGE
I0LE
NMIREE
0
0
0
0
W
IIMC
Interrupt
input
mode
control
8CH
RMW instructions are prohibited.
0
0
Always
write “0”.
0
–
0
–
–
INT0
EDGE
0: Rising
1: Falling
–
1:Operates even
on rising/
falling
edge of
INT0
mode
0: Edge
1: Level
NMI
INT0 setting
P7FC<P75F>
<IOLE>
<IOEDGE>
1
0
0
Rising edge interruption
INT0
1
0
1
Falling edge interruption
1
1
0
“H” level INT
1
1
1
“L” level INT
NMI rising edge enable
3.3.3
0
INT request generation at falling edge
1
INT request generation at rising/falling edge
Interrupt Request Flag Clear Register
The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 31, to the register INTCLR.
For example, to clear the interrupt flag INT0, perform the following register operation after execution of the
DI instruction.
INTCLR ← 0AH: Clears interrupt request flag INT0.
Interrupt Request Flag Clear Register (INTCLR)
Symbol
INTCLR
Name
Interrupt
Clear
Control
Address
7
6
5
4
3
2
1
0
88H
–
–
CLRV5
CLRV4
CLRV3
CLRV2
CLRV1
CLRV0
–
–
–
–
0
0
0
RMW
instructions
are prohibited.
W
0
0
0
Interrupt vector
Page 42
2007-10-15
TMP91FW60
3.3.4
Micro DMA Start Vector Registers
This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro
DMA start vector that matches the vector set in this register is assigned as the micro DMA start source.
When the micro DMA transfer counter value reaches 0, the micro DMA transfer end interrupt corresponding
to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro
DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro
DMA start vector register again during the processing of the micro DMA transfer end interrupt.
If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with
the lowest number has a higher priority.
Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt
generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro
DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the
higher number. (Micro DMA chaining)
Micro DMA Start Vector Registers (DMAnV)
Symbol
DMA0V
Name
DMA0
Start
Vector
Address
7
6
5
4
3
2
1
0
–
–
DMA0V5
DMA0V4
DMA0V3
DMA0V2
DMA0V1
DMA0V0
–
–
–
–
0
0
0
DMA1V2
DMA1V1
DMA1V0
0
0
0
DMA2V2
DMA2V1
DMA2V0
0
0
0
DMA3V2
DMA3V1
DMA3V0
0
0
0
R/W
80H
0
0
0
DMA0 start vector
DMA1V
DMA1
Start
Vector
–
–
–
–
–
–
DMA1V5
DMA1V4
DMA1V3
R/W
81H
0
0
0
DMA1 start vector
DMA2V
DMA2
Start
Vector
–
–
–
–
–
–
DMA2V5
DMA2V4
DMA2V3
R/W
82H
0
0
0
DMA2 start vector
DMA3V
DMA3
Start
Vector
–
–
–
–
–
–
DMA3V5
DMA3V4
DMA3V3
R/W
83H
0
0
0
DMA3 start vector
Page 43
2007-10-15
TMP91FW60
3.3.5
Micro DMA Burst Specification
Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register
reaches 0 after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB
registers mentioned below to “1” specifies a burst.
If other interrupts (maskable/nonmaskable is not concerned) are generated during burst transfer, interrupt is
executed after completed burst transfer.
Micro DMA Burst Request Registers (DMAR)
Symbol
Name
DMAR
DMA
Software
Request
Register
DMAB
DMA
Burst
Register
Address
7
6
5
4
3
2
1
0
89H
–
–
–
–
DMAR3
DMAR2
DMAR1
DMAR0
–
–
–
–
–
–
–
–
0
0
RMW
instructions
are prohibited.
R/W
0
0
1: DMA software request
–
–
–
–
–
–
–
–
–
–
–
–
DMAB3
DMAB2
DMAB1
DMAB0
0
0
R/W
8AH
0
0
1: DMA burst request
Page 44
2007-10-15
TMP91FW60
3.3.6
Attention Point
The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore,
immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding
interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (Note) between
accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the
interrupt vector address FFFF08H.
To avoid the above problem, place instructions that clear interrupt request flags after a DI instruction. And in
the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute
EI instruction after clearing and more than 1-instructions (ex. “NOP” * 1 times). If executed EI instruction
without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request
flag is cleared.
In the case of changing the value of the interrupt mask register <IFF2:0> by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction.
In addition, take care as the following 2 circuits are exceptional and demand special attention.
In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request
passes through the S input of the flip-flop and becomes the Q output. If the interrupt
input mode is changed from edge mode to level mode, the interrupt request flag is
cleared automatically.
INT0 level mode
INTRXn
If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to
1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1
from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is
necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to
0 before the halt state has been released.)
When the mode changes from level mode to edge mode, interrupt request flags which
were set in level mode will not be cleared. Interrupt request flags must be cleared
using the following sequence.
DI
LD (IIMC), 00H
; Switches interrupt input mode from level mode to edge mode.
LD (INTCLR), 0AH ; Clears interrupt request flag.
NOP
; Wait EI instruction
EI
The interrupt request flip-flop can only be cleared by reset or by reading the serial
channel receive buffer. It cannot be cleared by writing INTCLR register.
Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag.
INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode.
The pin input change from high to low after interrupt request has been generated in level mode. (H → L)
INTRXn: Instruction which reads the receive buffer.
Page 45
2007-10-15
TMP91FW60
4. Port Function
The TMP91FW60 features 83 bit settings which relate to the various I/O ports.
As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in
CPU and internal I/Os. Table 4-1 lists the functions of each port pin. Table 4-1 lists the functions of each port pin.
Table 4-2 lists I/O registers and their specifications.
Table 4-1 Port Functions (R: PU = with programmable pull-up resistor) (1/2)
Port Names
Pin Names
Number of
Pins
Direction
R
Direction
Setting Unit
Pin Names for Built-in Functions
Port0
P00 to P07
8
I/O
−
Bit
AD0 to AD7
Port1
P10 to P17
8
I/O
−
Bit
AD8 to AD15/A8 to A15
Port2
P20∼P27
8
I/O
−
Bit
A16 to A23/A0 to A7
P30
1
I/O
−
Bit
TB3IN0, INT3, SDA0
P31
1
I/O
−
Bit
TB3IN1, INT4, SCL0
P32
1
I/O
−
Bit
WAIT, TB3OUT0
P33
1
I/O
−
Bit
TB3OUT1
P40
1
I/O
PU
Bit
CS0, SCOUT
P41
1
I/O
PU
Bit
CS1, TXD2
P42
1
I/O
PU
Bit
CS2 RXD2
P43
1
I/O
PU
Bit
CS3, SCLK2, CTS2
P44
1
I/O
PU
Bit
ALE
P50
1
I/O
−
Bit
AN0
P51
1
I/O
−
Bit
AN1
P52
1
I/O
−
Bit
AN2
P53
1
I/O
−
Bit
AN3
P54
1
I/O
−
Bit
AN4
P55
1
I/O
−
Bit
AN5
P56
1
I/O
−
Bit
AN6
P57
1
I/O
−
Bit
AN7
P60
1
I/O
−
Bit
AN8
P61
1
I/O
−
Bit
AN9
P62
1
I/O
−
Bit
AN10
P63
1
I/O
−
Bit
AN11
P64
1
I/O
−
Bit
AN12
P65
1
I/O
−
Bit
AN13
P66
1
I/O
−
Bit
AN14
P67
1
I/O
−
Bit
AN15
Port3
Port4
Port5
Port6
Page 46
2007-10-15
TMP91FW60
Table 4-1 Port Functions (R: PU = with programmable pull-up resistor) (2/2)
Port Names
Number of
Pins
Direction
R
Direction
Setting Unit
P70
1
I/O
−
Bit
TA0IN
P71
1
I/O
−
Bit
TA1OUT
P72
1
I/O
−
Bit
TA3OUT
P73
1
I/O
−
Bit
TA4IN
P74
1
I/O
−
Bit
TA5OUT
P75
1
I/O
−
Bit
INT0
P80
1
I/O
−
Bit
TB0IN0, INT5
P81
1
I/O
−
Bit
TB0IN1, INT6
P82
1
I/O
−
Bit
TB0OUT0
P83
1
I/O
−
Bit
TB0OUT1
P84
1
I/O
−
Bit
TB1IN0, INT7
P85
1
I/O
−
Bit
TB1IN1, INT8
P86
1
I/O
−
Bit
TB1OUT0
P87
1
I/O
−
Bit
TB1OUT1
P90
1
I/O
−
Bit
TXD0
P91
1
I/O
−
Bit
RXD0
P92
1
I/O
−
Bit
SCLK0, CTS0
P93
1
I/O
−
Bit
TXD1
P94
1
I/O
−
Bit
RXD1
P95
1
I/O
−
Bit
SCLK1, CTS1
P96
1
I/O
−
Bit
XT1
P97
1
I/O
−
Bit
XT2
PA0
1
I/O
−
Bit
TB2IN0, INT1
PA1
1
I/O
−
Bit
TB2IN1, INT2
PA2
1
I/O
−
Bit
TB2OUT0
PA3
1
I/O
−
Bit
TB2OUT1
PB0
1
I/O
−
Bit
TB4IN0, INT9, SDA1
PB1
1
I/O
−
Bit
TB4IN1, INT10, SCL1
PB2
1
I/O
−
Bit
TB4OUT0
PB3
1
I/O
−
Bit
TB4OUT1
PZ0
1
Output
−
Bit
RD
PZ1
1
Output
−
Bit
WR
PZ2
1
I/O
PU
Bit
HWR
PZ3
1
I/O
PU
Bit
R/W
Pin Names
Port7
Port8
Port9
PortA
PortB
Pin Names for Built-in Functions
PortZ
Page 47
2007-10-15
TMP91FW60
Table 4-2
I/O Port Setting List(1/4)
I/O Register Setting Values
Ports
Port0
Port1
Port2
Pin Names
P00 to P07
Specifications
Pn
PnCR
PnFC
PnFC2
ODE
Input port
×
0
Output port
×
1
None
None
None
AD0 to AD7 bus#1
×
×
Input port
×
0
0
Output port
×
1
0
AD8 to AD15 bus
×
0
1
None
None
A8 to A15 output
×
1
1
Input port
×
0
0
Output port
×
1
0
A0 to A7 output
×
0
1
None
None
A16 to A23 output
×
1
1
Input port
×
0
0
0
−
Output port (CMOS output)
×
1
0
0
0
Output port (open drain output)
×
1
0
0
1
Input port
×
0
0
×
None
None
Output port
1
0
TB3IN0 Input, INT3 Input
×
0
1
0
−
SDA0 input/output (CMOS output)
×
1
0
1
0
SDA0 input/output (open drain output)#2
×
1
0
1
1
TB3IN1 Input, INT4 Input
×
0
1
0
−
SCL0 input/output (CMOS output)
×
1
0
1
0
SCL0 input/output (open drain output)#2
×
1
0
1
1
WAIT output
×
0
1
TB3OUT0 output
×
1
1
None
None
TB3OUT1 output
×
1
1
P10 to P17
P20 to P27
P30 to P31
P32 to P33
P30
Port3
P31
P32
P33
Page 48
2007-10-15
TMP91FW60
Table 4-2
I/O Port Setting List(2/4)
I/O Register Setting Values
Ports
Pin Names
P40, P43
P42, P44
Specifications
Pn
PnCR
PnFC
PnFC2
Input port (without pull up)
0
0
0
0
Input port (with pull up)
1
0
0
0
Output port
×
1
0
0
Input port (without pull up)
0
0
0
Input port (with pull up)
1
0
0
Output port
×
1
0
Input port (without pull up)
0
0
Input port (with pull up)
1
Output port (CMOS output)
None
0
0
−
0
0
0
−
×
1
0
0
0
Output port (open drain output)
×
1
0
0
1
CS0 output
×
1
1
0
SCOUT output
×
1
0
1
CS1 output (CMOS output)
×
1
1
0
0
CS1 output (open drain output)
×
1
1
0
1
TXD2 output (CMOS output)
×
1
0
1
0
TXD2 output (open drain output)#2
×
1
0
1
1
CS2 output
×
1
1
×
None
None
RXD2 Input
0
0
CS3 output
×
1
1
0
SCLK2 Input
×
0
0
0
SCLK2 output
×
1
0
1
CTS2 Input
×
0
0
0
ALE output
×
1
1
None
None
Input port
×
0
1
Output port
×
1
0
None
None
AN0 to AN7 Input #3
×
0
0
Input port
×
0
1
Output port
×
1
0
None
None
AN8 to AN15 Input #3
×
0
0
Input port
×
0
0
Output port
×
1
0
P70
TA0IN Input
×
0
None
P71
TA1OUT output
×
1
1
None
TA3OUT output
×
None
P72
1
1
P73
TA4IN Input
×
0
None
P74
TA5OUT output
×
1
1
P75
INT0 Input
×
0
1
P40
Port4
P41
P42
P43
P44
Port6
None
None
P41
Port5
ODE
P50 to P57
P60 to P67
P70 to P75
Port7
Page 49
None
None
2007-10-15
TMP91FW60
Table 4-2
I/O Port Setting List(3/4)
I/O Register Setting Values
Ports
Pin Names
Specifications
Pn
PnCR
PnFC
Input port
×
0
0
Output port
×
1
0
P80
TB0IN0, INT5 Input
×
0
1
P81
TB0IN1, INT6 Input
×
0
1
P82
TB0OUT0 output
×
1
1
P83
TB0OUT1 output
×
1
1
P84
TB1IN0, INT7 Input
×
0
1
P85
TB1IN1, INT8 Input
×
0
1
P86
TB1OUT0 output
×
1
1
P87
TB1OUT1 output
×
1
1
P91 to P92,
P94 to P95
Input port
×
0
0
Output port
×
1
0
Input port
×
0
0
−
Output port (CMOS output)
×
1
0
0
Output port (open drain output)
×
1
0
1
TXD0 output (CMOS output)
×
1
1
0
TXD0 output (open drain output)#2
×
1
1
1
RXD0 Input
×
0
None
None
SCLK0 Input
×
0
0
SCLK0 output
×
1
1
CTS0 Input
×
0
0
TXD1 output (CMOS output)
×
1
1
0
TXD1 output (open drain output)#2
×
1
1
1
RXD1 Input
×
0
None
None
SCLK1 Input
×
0
0
SCLK1 output
×
1
1
CTS1 Input
×
0
0
Input port
×
0
1
Output port
×
1
1
XT1 to XT2 #4
×
0
0
Input port
×
0
0
Output port
×
1
0
PA0
TB2IN0 Input, INT1 Input
×
0
1
PA1
TB2IN1 Input, INT2 Input
×
0
1
PA2
TB2OUT0
×
1
1
PA3
TB2OUT1
×
1
1
P80 to P87
Port8
P90, P93
P90
P91
P92
Port9
P93
P94
P95
P96 to P97
PA0 to PA3
PortA
Page 50
PnFC2
ODE
None
None
None
None
None
None
None
None
None
2007-10-15
TMP91FW60
Table 4-2
I/O Port Setting List(4/4)
I/O Register Setting Values
Ports
Pin Names
Specifications
Pn
PnCR
PnFC
PnFC2
ODE
Input port
×
0
0
0
−
Output port (CMOS output)
×
1
0
0
0
Output port (open drain output)
×
1
0
0
1
Input port
×
0
0
×
None
None
Output port
1
0
TB4IN0 Input, INT9 Input
×
0
1
0
−
×
1
0
1
0
SDA1 input/output (open drain output)
×
1
0
1
1
TB4IN1 Input, INT10 Input
×
0
1
0
−
SCL1 input/output (CMOS output)
×
1
0
1
0
SCL1 input/output (open drain output)#2
×
1
0
1
1
PB2
TB4OUT0 output
×
1
1
None
TB4OUT1 output
×
None
PB3
1
1
Output port
×
RD output only when accessing an external
1
Always RD output
0
Output port
×
None
None
PB0 to PB1
PB2 to PB3
PB0
PortB
SDA1 input/output (CMOS output)
#2
PB1
PZ0
PZ1
0
None
1
1
0
None
WR output only when accessing an external
×
Input port (without pull up)
0
0
0
Input port (with pull up)
1
0
0
Output port
×
1
0
PZ2
HWR output
×
1
1
PZ3
R/W output
×
0
1
1
PortZ
PZ2 to PZ3
#1
#2
#3
#4
There is not port setting for changing AD0 to AD7. When accessing external area, it changes automatically.
If using P30/P31/P41/P90/P93/PB0/PB1 as open-drain output in SDA0/SCL0/TXD2/TXD0/TXD1/SDA1/SCL1 output,
please set ODE.
If using P50 to P57,P60 to P67 as an analog input, please set ADCCR1<SAIN3:0>.
If using P96 to P97 as XT1-XT2, please set SYSCR0.
Note:
×:Don’t care
Page 51
2007-10-15
TMP91FW60
4.1 Port 0 (P00 to P07)
Port 0 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control
register P0CR. Reset operation initializes all bits of the control register P0CR to “0” and sets port 0 to input port.
In addition to functioning as a general-purpose I/O port, port 0 can also function as address data bus (AD0 to
AD7).
When accessing external area, port 0 functions as address data bus (AD0 to AD7) automatically, and P0CR is
cleared to “0”.
Reset
Direction
control
(on bit basis)
Internal data bus
P0CR write
Port 0
P00 to P07
(AD0 to AD7)
1WVRWV
NCVEJ
Output
buffer
P0 write
S
B
5GNGEVQT
A
P0 read
Figure 4-1 Port 0
Port 0 Register
Bit symbol
P0
(0000H)
6
5
4
3
2
1
0
P06
P05
P04
P03
P02
P01
P00
Read/Write
R/W
After reset
Data from external port (Output latch register is undefined.)
Port 0 Control Register
(Read-modify-write instructions are prohibited.)
Bit symbol
P0CR
(0002H)
7
P07
7
6
5
4
3
2
1
0
P07C
P06C
P05C
P04C
P03C
P02C
P01C
P00C
0
0
0
0
0
0
0
0
Read/Write
W
After reset
Function
access
0: Input 1: Output (When access to external, become AD7 to AD0 and this register is cleared to “0”.)
P0xC
P07
function
P06
function
P05
function
P04
function
P03
function
P02
function
P01
function
P00
function
0
input port
input port
input port
input port
input port
input port
input port
input port
1
output port
output port
output port
output port
output port
output port
output port
output port
cleared to
"0"
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
internal
external
Note: <P0xC> is bit X of each register P0CR.
Page 52
2007-10-15
TMP91FW60
4.2 Port 1 (P10 to P17)
Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control
register P1CR and function register P1FC. Reset operation initializes all bits of output latch P1, the control register
P1CR and function register P1FC to “0” and sets port 1 to input port.
In addition to functioning as a general-purpose I/O port, port 1 can also function as address data bus (AD8 to
AD15) and address bus (A8 to A15).
Reset
Direction
control
(on bit basis)
Internal data bus
P1CR write
Function
control
(on bit basis)
P1FC write
1WVRWVNCVEJ
1WVRWVDWHHGT
2QTV
P10 to P17
(AD8 to AD15/A8 to A15
P1 write
S
B
5GNGEVQT
A
P1 read
Figure 4-2 Port 1
Page 53
2007-10-15
TMP91FW60
Port 1 Register
Bit symbol
P1
(0001H)
7
6
5
4
P17
P16
P15
P14
3
2
1
0
P13
P12
P11
P10
Read/Write
R/W
After reset
Data from external port (Output latch register is cleared to “0”.)
Port 1 Control Register (Read-modify-write instructions are prohibited.)
Bit symbol
P1CR
(0004H)
7
6
5
4
P17C
P16C
P15C
P14C
Read/Write
After reset
3
2
1
0
P13C
P12C
P11C
P10C
0
0
0
0
3
2
1
0
P13F
P12F
P11F
P10F
0
0
0
0
W
0
0
0
0
Function
<<Refer to column of P1FC>>
Port 1 Function Register (Read-modify-write instructions are prohibited.)
Bit symbol
P1FC
(0005H)
7
6
5
4
P17F
P16F
P15F
P14F
Read/Write
After reset
W
0
0
Function
0
0
P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8
P17
function
P16
function
P15
function
P14
function
P13
function
P12
function
P11
function
P10
function
P1xF
P1xC
0
0
input port
input port
input port
input port
input port
input port
input port
input port
0
1
output port
output port
output port
output port
output port
output port
output port
output port
1
0
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
1
1
A15
A14
A13
A12
A11
A10
A9
A8
Note:<P1XF>/<P1XC> is bit X of each register P1FC/P1CR.
Page 54
2007-10-15
TMP91FW60
4.3 Port 2 (P20 to P27)
Port 2 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control
register P2CR and function register P2FC. Reset operation initializes all bits of output latch P2 to “1”, and the control register P2CR and function register P2FC to “0”, and sets port 2 to input port.
A16 to A23
B
A0 to A7
A
Selector
In addition to functioning as a general-purpose I/O port, port 2 can also function as address bus (A0 to A5) and
address bus (A16 to A23).
S
4GUGV
Direction
control
(on bit basis)
Function
control
(on bit basis)
P2FCYTKVG
S
B
1WVRWVNCVEJ
A
Selector
Internal data bus
P2CRYTKVG
1WVRWVDWHHGT
2QTV
P20~P27
(A0~A7/A16~A23)
P2YTKVG
S
B
5GNGEVQT
A
P2TGCF
Figure 4-3 Port 2
Page 55
2007-10-15
TMP91FW60
Port 2 Register
Bit symbol
P2
(0006H)
7
6
5
4
P27
P26
P25
P24
3
2
1
0
P23
P22
P21
P20
Read/Write
R/W
After reset
Data from external port (Output latch register is set to “1”.)
Port 2 Control Register (Read-modify-write instructions are prohibited.)
Bit symbol
P2CR
(0008H)
7
6
5
4
3
2
1
0
P27C
P26C
P25C
P24C
P23C
P22C
P21C
P20C
0
0
0
0
0
0
0
0
3
2
1
0
P23F
P22F
P21F
P20F
0
0
0
0
Read/Write
After reset
W
Function
<<Refer to column of P2FC>>
Port 2 Function Register (Read-modify-write instructions are prohibited.)
Bit symbol
P2FC
(0009H)
7
6
5
4
P27F
P26F
P25F
P24F
Read/Write
After reset
W
0
0
Function
0
0
P2FC/P2CR = 00: Input, 01: Output, 10: A7 to A0, 11: A23 to A16
P2xF
P2xC
P27
function
P26
function
P25
function
P24
function
P23
function
P22
function
P21
function
P20
function
0
0
input port
input port
input port
input port
input port
input port
input port
input port
0
1
output port
output port
output port
output port
output port
output port
output port
output port
1
0
A7
A6
A5
A4
A3
A2
A1
A0
1
1
A23
A22
A21
A20
A19
A18
A17
A16
Note: <P2XF>/<P2XC> is bit X of each register P2FC/P2CR. When setting to address bus A23 to A16, set P2FC after setting
P2CR. If P2CR is set after setting P2FC, A7 to A0 are outputted between setting P2FC and setting P2CR when P2CR is “0”.
Page 56
2007-10-15
TMP91FW60
4.4 Port3 (P30 to P33)
Port 3 is an 4-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register
P3 are set to “1”.
There are the following functions in addition to an I/O port. This function enable each function by writing “1” to
applicable bit of port 3 function register P3FC.
•The input function of wait control (WAIT)
•The input function of external interrupt (INT3, INT4)
•The input function of 16-bit timer 3 (TB3IN0, TB3IN1)
•The output function of 16-bit timer 3 (TB3OUT0, TB3OUT1)
•The I/O function of serial bus interface 0 (SDA0, SCL0)
Reset operation initializes, P3CR,P3FC and P3FC2 to “0”, all bits are set to input port.
And Port 30 and 31 have a programmable open-drain function which can be controlled by the ODE register.
4GUGV
Direction
control
(on bit basis)
P3CR write
Internal data bus
Function
control 2
(on bit basis)
P3FC2 write
S
1WVRWVNCVEJ
A
Open-drain
possible:
ODE<ODE30,31>
S
P30(TB3IN0,INT3,SDA0)
P31(TB3IN1,INT4,SCL0)
5GNGEVQT
P3 write
B
SDA0QWVRWV
SCL0QWVRWV
Function
control
(on bit basis)
P3FC write
S B
5GNGEVQT
P3TGCF
A
TB3IN0,INT3
TB3IN1,INT4
SDA0KPRWV
SCL0KPRWV
2(%
Figure 4-4 Port 30 and 31
Page 57
2007-10-15
TMP91FW60
4GUGV
Direction
control
(on bit basis)
P3CRYTKVG
Internal data bus
Function
control
(on bit basis)
P3FCYTKVG
S
1WVRWVNCVEJ
S
A
5GNGEVQT
P3YTKVG
P32( WAIT ,TB3OUT0)
B
TB3OUT0QWVRWV
S B
5GNGEVQT
A
P3TGCF
KPVGTPCN
WAIT
4GUGV
Direction
control
(on bit basis)
P3CRYTKVG
ᯏ⢻೙ᓮ
(ࡆ࠶࠻Ფ)
Internal data bus
P3FC write
S
1WVRWVNCVEJ
P3YTKVG
S
A
P33(TB3OUT1)
5GNGEVQT
B
TB3OUT1QWVRWV
S B
5GNGEVQT
P3TGCF
A
Figure 4-5 Port 32 and 33
Page 58
2007-10-15
TMP91FW60
Port 3 Register
P3
(000CH)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
−
P33
P32
P31
P30
Read/Write
−
−
−
−
R/W
After reset
−
−
−
−
Data from external port (Output latch register is set to “1”.)
Function
-
output mode
Port 3 Control Register (Read-modify-write instructions are prohibited.)
P3CR
(000EH)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
−
P33C
P32C
P31C
P30C
Read/Write
−
−
−
−
After reset
−
−
−
−
0
0
Function
W
0
0
-
0:Input 1:Output
Port 3 Function Register (Read-modify-write instructions are prohibited.)
P3FC
(000FH)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
−
P33F
P32F
P31F
P30F
Read/Write
−
−
−
−
After reset
−
−
−
−
0
0
0
0
W
Port 3 Function Register 2 (Read-modify-write instructions are prohibited.)
P3FC2
(000DH)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
−
−
−
P31F2
P30F2
Read/Write
−
−
−
−
−
−
After reset
−
−
−
−
−
−
P3xF2
P3xF
P3xC
P33
function
P32
function
P31
function
P30
function
0
0
0
input port
input port
input port
input port
0
0
1
output port
output port
output port
output port
0
1
0
reserved
WAIT
TB3IN1/INT4
TB3IN0/INT3
0
1
1
TB3OUT1
TB3OUT0
reserved
reserved
1
0
0
reserved
reserved
reserved
reserved
1
0
1
reserved
reserved
SCL0
SDA0
1
1
0
reserved
reserved
reserved
reserved
1
1
1
reserved
reserved
reserved
reserved
W
0
0
Note 1: <P3xF2>/<P3xF>/<P3xC> is bit X of each register P3FC2/P3FC/P3CR.
Note 2: Wen P32/WAIT pin is used as a WAIT pin, set P3CR<P32C> to "0" and Chip Select/WAIT control register <BnW2:0> to
"010".
Page 59
2007-10-15
TMP91FW60
4.5 Port 4 (P40 to P44)
Port 4 is an 5-bit general-purpose I/O port. Reset operation initializes to input port, and connects a pull-up resistor.
All bits of output latch register P4 are set to “1”.
There are the following functions in addition to an I/O port. This function enable each function by writing “1” to
applicable bit of port 4 function register P4FC.
•The output function of a chip select signal (CS0 to CS3)
•The I/O function of the serial channel 2 (RXD2, TXD2, SCLK2/CTS2)
•The output function of an Address latch enable signal (ALE)
•The output function of a system clock signal (SCOUT)
Reset operation initializes, P4CR,P4FC and P4FC2 to “0”, all bits are set to input port.
And Port 41 have a programmable open-drain function which can be controlled by the ODE register.
Reset
Direction control
(on bit basis)
P4CR write
Function
control
(on bit basis)
Function
control 2
(on bit basis)
P-ch
P4FC2 write
5
1WVRWV
NCVEJ $
%5
P4 write
5%176 %
(Programmable
pull up)
5 5 #
2
%55%176
Selector
Internal data bus
P4FC write
Output buffer
&
TGUGTXGF
P4 read
Figure 4-6 Port 40
Page 60
2007-10-15
TMP91FW60
Reset
Direction
control
(on bit basis)
P4CR write
P4FC write
Open-drain
possible:
ODE<ODE41>
Function
control 2
(on bit basis)
P-ch
(Programmable
pull up)
P4FC2 write
5 5 5
1WVRWV
NCVEJ 2
%5 6:&
$
%5 %
&
6:& 1WVRWVDWHHGT
P4 write
#
Selector
Internal data bus
Function
control
(on bit basis)
TGUGTXGF
P4 read
Figure 4-7 Port 41
Input
(internal signal)
<ODE41>=0
<ODE41>=1
Output buffer
pull-up
Output buffer
pull-up
<P41>=0,CS1=0, TXD2=0
L Level output
OFF
L Level output
OFF
<P41>=1, CS1=1, TXD2=1
H Level output
ON
Hi-z
ON
Page 61
2007-10-15
TMP91FW60
Reset
Direction control
(on bit basis)
P4CR write
Internal data bus
Function control
(on bit basis)
P-ch
P4FC write
(Programmable
pull up)
5
1WVRWV
NCVEJ #
$
Selector
5
2
%5 4:&
Output buffer P4 write
%5 P4 read
4:& Figure 4-8 Port 42
Page 62
2007-10-15
TMP91FW60
Reset
Direction
control
(on bit basis)
P4CR write
P4FC write
Internal data bus
Function
control
(on bit basis)
P-ch
(Programmable
pull up)
P4FC2 write
5 5
1WVRWV
NCVEJ
#
$
%
&
5%.- 2
%5 5%.- %65 Output buffer
%5 P4 write
5 Selector
Function
control 2
(on bit basis)
TGUGTXGF
P4 read
5%.-
%65 Figure 4-9 Port 43
Page 63
2007-10-15
TMP91FW60
Reset
Direction
control
(on bit basis)
Function
control
(on bit basis)
P-ch
P4FC write
(Programmable
pull up)
5
5
1WVRWV
NCVEJ #
$
Selector
Internal data bus
P4CR write
2
#.' Output buffer
P4 write
#.'
P4 read
Figure 4-10 Port 44
Page 64
2007-10-15
TMP91FW60
Port 4 Register
P4
(0010H)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
P44
P43
P42
P41
P40
Read/Write
−
−
−
R/W
−
Data from external port
(Output latch register is set to “1”.)
After reset
−
−
0 (Output latch register): Pull-up resistor OFF
1 (Output latch register): Pull-up resistor ON
Function
Port 4 Control Register (Read-modify-write instructions are prohibited.)
P4CR
(0012H)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
P44C
P43C
P42C
P41C
P40C
Read/Write
−
−
−
After reset
−
−
−
0
0
W
0
0
0
Function
0: Input 1: Output
Port 4 Function Register (Read-modify-write instructions are prohibited.)
P4FC
(0013H)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
P44F
P43F
P42F
P41F
P40F
Read/Write
−
−
−
After reset
−
−
−
0
0
0
0
W
0
Port 4 Function Register 2 (Read-modify-write instructions are prohibited.)
P4FC2
(0011H)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
−
P43F2
−
P41F2
P40F2
Read/Write
−
−
−
−
W
−
After reset
−
−
−
−
0
−
W
0
P4xF2
P4xF
P4xC
P44
function
P43
function
P42
function
P41
function
P40
function
0
0
0
input port
input port
(SCLK2/CTS2)
input port
(RXD2)
input port
input port
0
0
1
output port
output port
output port
output port
output port
0
1
0
reserved
reserved
reserved
reserved
reserved
0
1
1
ALE output
CS3
CS2
CS1
CS0
reserved
reserved
SCOUT
1
0
0
input port
reserved
input port
(RXD2)
1
0
1
output port
SCLK2
output port
TXD2
1
1
0
reserved
reserved
reserved
reserved
reserved
1
1
1
ALE output
reserved
CS2
reserved
reserved
0
Note 1: <P4xF2>/<P4xF>/<P4xC> is bit X of each register P4FC2/P4FC/P4CR.
Note 2: When port 4 is used as input mode, P4 register controls internal pull-up resistor. Read-modify-write instruction is prohibited in input mode or I/O mode. Setting the internal pull-up resistor may be depended on the states of the input pin.
Note 3: When outputting chip select signal (CS0 to CS3), set bit of control register (P4CR) to “1” after setting bit of function register (P4FC) to “1”. If P4FC is set after setting P4CR, value of P4 register is outputted between setting P4CR and setting
P4FC.
Note 4: When setting TXD2 pin to open-drain output, write “1” to bit2 of ODE register. P42/RXD2 pin does not have a register
which changes Port/Function. For example, when it is also used as an input port, the input signal is inputted to SIO as
serial receiving data.
Page 65
2007-10-15
TMP91FW60
4.6 Port 5 (P50 to P57)
Port 5 is an 8-bit general-purpose I/O port. By the reset action, it becomes Hi-Z and becomes analog input permission.All bits of output latch register P5 are set to “1”.
There are the following functions in addition to an I/O port.
•The input function of the Analog/Digital Converter (AN0 to AN7)
Reset operation initializes, P5CR,P5FC to “0”, all bits are set to input port.
Reset
Direction
control
(on bit basis)
Internal data bus
P5CR write
Function
control
(on bit basis)
P5FC write
Port 5
P50 to P57
(AN0 to AN7)
S
1WVRWV
NCVEJ
P5 write
S
B
5GNGEVQT
P5 read
AD read
A
#&
EQPXGTUKQP
TGUWNV
TGIKUVGT
AD
EQPXGTVQT
EJCPPGN
UGNGEVQT
Figure 4-11 Port 5
Page 66
2007-10-15
TMP91FW60
Port 5 Register
Bit symbol
P5
(0014H)
7
6
5
4
P57
P56
P55
P54
3
2
1
0
P53
P52
P51
P50
Read/Write
R/W
After reset
Data from external port (Output latch register is set to “1”.)
Port 5 Control Register (Read-modify-write instructions are prohibited.)
Bit symbol
7
6
5
4
3
2
1
0
P57C
P56C
P55C
P54C
P53C
P52C
P51C
P50C
0
0
0
0
0
0
0
0
3
2
1
0
P53F
P52F
P51F
P50F
Read/Write
P5CR
(0016H)
After reset
W
Function
0: Input 1: Output
Port 5 Function Register (Read-modify-write instructions are prohibited.)
Bit symbol
7
6
5
4
P57F
P56F
P55F
P54F
Read/Write
P5FC
(0017H)
After reset
W
0
P57 input
0:disable
1:enable
Function
0
P56 input
0:disable
1:enable
0
0
P55 input
0:disable
1:enable
P54 input
0:disable
1:enable
0
P53 input
0:disable
1:enable
0
P52 input
0:disable
1:enable
0
0
P51 input
0:disable
1:enable
P50 input
0:disable
1:enable
P5xF
P5xC
P57
function
P56
function
P55
function
P54
function
P53
function
P52
function
P51
function
P50
function
0
0
input disable
input disable
input disable
input disable
input disable
input disable
input disable
input disable
0
1
output port
output port
output port
output port
output port
output port
output port
output port
1
0
input enable
input enable
input enable
input enable
input enable
input enable
input enable
input enable
1
1
output port
output port
output port
output port
output port
output port
output port
output port
Note 1: <P5xF>/<P5xC> is bit X of each register P5FC/P5CR.
Note 2: The input channel selection of AD converter are set by AD converter mode register ADCCR1.
Page 67
2007-10-15
TMP91FW60
4.7 Port 6 (P60 to P67)
Port 6 is an 8-bit general-purpose I/O port. By the reset action, it becomes Hi-Z and becomes analog input permission.All bits of output latch register P6 are set to “1”.
There are the following functions in addition to an I/O port.
•The input function of the Analog/Digital Converter (AN8 to AN15)
Reset operation initializes, P6CR,P6FC to “0”, all bits are set to input port.
Reset
Direction
control
(on bit basis)
Function
control
(on bit basis)
Internal data bus
P6CR write
P6FC write
Port 6
P60 to P67
(AN8 to AN15)
S
1WVRWV
NCVEJ
S
P6 write
B
5GNGEVQT
P6 read
AD read
A
#&
EQPXGTUKQP
TGUWNV
TGIKUVGT
AD
EQPXGTVQT
EJCPPGN
UGNGEVQT
Figure 4-12 Port 6
Page 68
2007-10-15
TMP91FW60
Port 6 Register
Bit symbol
P6
(0018H)
7
6
5
4
P67
P66
P65
P64
3
2
1
0
P63
P62
P61
P60
Read/Write
R/W
After reset
Data from external port (Output latch register is set to “1”.)
Port 6 Control Register (Read-modify-write instructions are prohibited.)
Bit symbol
7
6
5
4
3
2
1
0
P67C
P66C
P65C
P64C
P63C
P62C
P61C
P60C
0
0
0
0
0
0
0
0
3
2
1
0
P63F
P62F
P61F
P60F
Read/Write
P6CR
(001AH)
After reset
W
Function
0: Input 1: Output
Port 6 Function Register (Read-modify-write instructions are prohibited.)
Bit symbol
7
6
5
4
P67F
P66F
P65F
P64F
Read/Write
P6FC
(001BH)
After reset
W
0
P67 input
0:disable
1:enable
Function
0
P66 input
0:disable
1:enable
0
0
P65 input
0:disable
1:enable
P64 input
0:disable
1:enable
0
P63 input
0:disable
1:enable
0
P62 input
0:disable
1:enable
0
0
P61 input
0:disable
1:enable
P60 input
0:disable
1:enable
P6xF
P6xC
P67
function
P66
function
P65
function
P64
function
P63
function
P62
function
P61
function
P60
function
0
0
input disable
input disable
input disable
input disable
input disable
input disable
input disable
input disable
0
1
output port
output port
output port
output port
output port
output port
output port
output port
1
0
input enable
input enable
input enable
input enable
input enable
input enable
input enable
input enable
1
1
output port
output port
output port
output port
output port
output port
output port
output port
Note 1: <P6xF>/<P6xC> is bit X of each register P6FC/P6CR.
Note 2: The input channel selection of AD converter are set by AD converter mode register ADCCR1.
Page 69
2007-10-15
TMP91FW60
4.8 Port 7 (P70 to P75)
Port 7 is an 6-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register
P7 are set to “1”.
There are the following functions in addition to an I/O port. This function enable each function by writing “1” to
applicable bit of port 7 function register P7FC.
•The I/O function of 8-bit timer 01 (TA0IN,TA1OUT)
•The output function of 8-bit timer 23 (TA3OUT)
•The I/O function of 8-bit timer 45 (TA4IN,TA5OUT)
•The input function of external interrupt (INT0)
Reset operation initializes, P7CR and P7FC to “0”, all bits are set to input port.
4GUGV
Direction
control
(on bit basis)
P7CRYTKVG
S
1WVRWVNCVEJ
P70 (TA0IN)
P73 (TA4IN)
P7YTKVG
S B
5GNGEVQT
A
P7TGCF
TA0IN
TA4IN
Internal data bus
4GUGV
Direction
control
(on bit basis)
P7CRYTKVG
Function
control
(on bit basis)
P7FC YTKVG
S
1WVRWVNCVEJ
A S
5GNGEVQT
B
P71 (TA1OUT)
P72 (TA3OUT)
P74 (TA5OUT)
P7YTKVG
6KOGTF/F OUT
TA1OUT: TMRA1
TA3OUT: TMRA3
TA5OUT: TMRA5
B
5GNGEVQT
S
P74GCF
Figure 4-13 Port 70 to 74
Page 70
2007-10-15
TMP91FW60
4GUGV
Direction
control
(on bit basis)
Internal data bus
P7CRYTKVG
Function
control
(on bit basis)
P7FC YTKVG
S
Output latch
P75(INT0)
P7YTKVG
S
B
Selector
P74GCF
+06
A
.GXGNGFIG
&
4KUKPIHCNNKPIFGVGEV
IIMC<I0LE,I0EDGE>
Figure 4-14 Port 75
Page 71
2007-10-15
TMP91FW60
Port 7 Register
P7
(001CH)
7
6
5
4
3
2
1
0
Bit symbol
−
−
P75
P74
P73
P72
P71
P70
Read/Write
−
−
R/W
After reset
−
−
Data from external port (Output latch register is set to “1”.)
Port 7 Control Register (Read-modify-write instructions are prohibited.)
P7CR
(001EH)
7
6
5
4
3
2
1
0
Bit symbol
−
−
P75C
P74C
P73C
P72C
P71C
P70C
Read/Write
−
−
After reset
−
−
0
0
0
0
0
0
W
Function
0: Input 1: Output
Port 7 Function Register (Read-modify-write instructions are prohibited.)
P7FC
(001FH)
7
6
5
4
3
2
1
0
Bit symbol
−
−
P75F
P74F
−
P72F
P71F
−
Read/Write
−
−
After reset
−
−
−
W
0
0: port
1: INT0
Function
−
0
0: port
1: TA5OUT
−
W
0
0: port
1: TA3OUT
0
−
0: port
1: TA1OUT
P75 INT0 setting
<P75F>
<IOLE>
<IOEDGE>
1
0
0
INT0
Rising edge detect INT
1
0
1
falling edge detect INT
1
1
0
H level INT
1
1
1
L level INT
P7xF
P7xC
P75
function
P74
function
P73
function
P72
function
P71
function
P70
function
0
0
input port
input port
input port
(TA4IN)
input port
input port
input port
(TA0IN)
0
1
output port
output port
output port
output port
output port
output port
1
0
INT0
reserved
reserved
reserved
reserved
reserved
1
1
reserved
TA5OUT
reserved
TA3OUT
TA1OUT
reserved
Note 1: <P7xF>/<P7xC> is bit X of each register P7FC/P7CR.
Note 2: P70/TA0IN, P73/TA4IN pin dose not have a register changing PORT/FUNCTION. For example, when it is used as an
input port, the input signal is inputted to 8bit Timer.
Page 72
2007-10-15
TMP91FW60
4.9 Port 8 (P80 to P87)
Port 8 is an 8-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register
P8 are set to “1”.
There are the following functions in addition to an I/O port. This function enable each function by writing “1” to
applicable bit of port 8 function register P8FC.
•The I/O function of 16-bit timer 0 (TB0IN0,TB0IN1,TB0OUT0,TB0OUT1)
•The I/O function of 16-bit timer 1 (TB1IN0,TB1IN1,TB1OUT0,TB1OUT1)
•The input function of external interrupt (INT5 to INT8)
Reset operation initializes, P8CR and P8FC to “0”, all bits are set to input port.
4GUGV
Direction
control
(on bit basis)
P8CRYTKVG
Function
control
(on bit basis)
P8FCYTKVG
S
1WVRWVNCVEJ
P80 (TB0IN0/INT5)
P81 (TB0IN1/INT6)
P84 (TB1IN0/INT7)
P85 (TB1IN1/INT8)
P8YTKVG
S B
5GNGEVQT
Internal data bus
A
P8TGCF
TB0IN0, INT5
TB0IN1, INT6
TB1IN0, INT7
TB1IN1, INT8
4GUGV
Direction
control
(on bit basis)
P8CRYTKVG
Function
control
(on bit basis)
P8FCYTKVG
S
1WVRWVNCVEJ
A S
5GNGEVQT
B
P82 (TB0OUT0)
P83 (TB0OUT1)
P86 (TB1OUT0)
P87 (TB1OUT1)
P8YTKVG
6KOGTF/F OUT
TB0OUT0: TMRB0
TB0OUT1: TMRB0
TB1OUT0: TMRB1
TB1OUT1: TMRB1
B
5GNGEVQT
S
P8TGCF
Figure 4-15 Port 8
Page 73
2007-10-15
TMP91FW60
Port 8 Register
Bit symbol
P8
(0020H)
7
6
5
4
P87
P86
P85
P84
3
2
1
0
P83
P82
P81
P80
Read/Write
R/W
After reset
Data from external port (Output latch register is set to “1”.)
Port 8 Control Register (Read-modify-write instructions are prohibited.)
Bit symbol
P8CR
(0022H)
7
6
5
4
3
2
1
0
P87C
P86C
P85C
P84C
P83C
P82C
P81C
P80C
0
0
0
0
0
0
0
0
3
2
1
0
P83F
P82F
P81F
P80F
Read/Write
After reset
W
Function
0: Input 1: Output
Port 8 Function Register (Read-modify-write instructions are prohibited.)
Bit symbol
P8FC
(0023H)
7
6
5
4
P87F
P86F
P85F
P84F
Read/Write
After reset
Function
W
0
0
0: port
1: TB1OUT1
0: port
1: TB1OUT0
0
0
0: port
1: TB1IN1,
INT8
0: port
1: TB1IN0,
INT7
0
0
0: port
1: TB0OUT1
0: port
1: TB0OUT0
0
0: port
1: TB0IN1,
INT6
0
0: port
1: TB0IN0,
INT5
P8xF
P8xC
P87
function
P86
function
P85
function
P84
function
P83
function
P82
function
P81
function
P80
function
0
0
input port
input port
input port
input port
input port
input port
input port
input port
0
1
output port
output port
output port
output port
output port
output port
output port
output port
TB1IN0/
INT7
reserved
reserved
TB0IN1/
INT6
TB0IN0/
INT5
reserved
TB0OUT1
TB0OUT0
reserved
reserved
1
0
reserved
reserved
TB1IN1/
INT8
1
1
TB1OUT1
TB1OUT0
reserved
Note: <P8xF>/<P8xC> is bit X of each register P8FC/P8CR.
Page 74
2007-10-15
TMP91FW60
4.10 Port 9 (P90 to P97)
• Port 90 to 95
Port 90 to 95 are a 6-bit general-purpose I/O port. Reset operation initializes to input port. All bits of
output latch register are set to “1”.
In addition to functioning as a I/O port, port 90 to 95 can also function as I/O of SIO0, SIO1. This function enable each function by writing “1” to applicable bit of port 9 function register P9FC.
Reset operation initializes P9CR and P9FC to “0”, all bits are set to input port.
• Port 96 to 97
Port 96 to 97 are a 2-bit general-purpose I/O port. In case of output port, this is open drain output. Reset
operation initializes output latch register and control register to “1”, and it is set to “High-Z” (High impedance).
In addition to functioning as a I/O port, port 96 to 97 can also function as low-frequency oscillator connection pin (XT1 and XT2) during using low speed clock function. Therefore, dual clock function can use
by setting of system clock control registers SYSCR0 and SYSCR1.
4.10.1 Port 90 and 93 (TXD0 and TXD1)
In addition to functioning as a I/O port, Port 90 and 93 can also function as TXD output pin of serial channel.
And Port 90 and 93 have a programmable open-drain function which can be controlled by the ODE register.
4GUGV
Direction
control
(on bit basis)
Internal data bus
P9CRYTKVG
Function
control
(on bit basis)
P9FCYTKVG
S
1WVRWVNCVEJ
Open-drain
possible:
ODE<ODE90,93>
AS
P90 (TXD0)
P93 (TXD1)
5GNGEVQT
B
1WVRWVDWHHGT
P9YTKVG
TXD0, TXD1
S B
5GNGEVQT
A
P9TGCF
Figure 4-16 Port 90 and 93
Page 75
2007-10-15
TMP91FW60
4.10.2 Port91(RXD0), 94 (RXD1)
In addition to functioning as a I/O port, port 91 and 94 can also function as RXD input pin of serial channel.
4GUGV
Direction
control
(on bit basis)
Internal data bus
P9CRYTKVG
S
1WVRWVNCVEJ
P91 (RXD0)
P94 (RXD1)
P9YTKVG
S B
5GNGEVQT
P9TGCF
A
RXD0, RXD1
Figure 4-17 Port 91 and 94
Page 76
2007-10-15
TMP91FW60
4.10.3 Port 92(CTS0/SCLK0), 95 (CTS1/SCLK1)
In addition to functioning as a I/O port, port 92 and 95 can also function as CTS input pin or SCLK I/O pin of
serial channel.
4GUGV
Direction
control
(on bit basis)
Internal data bus
P9CRYTKVG
Function
control
(on bit basis)
P9FCYTKVG
S
1WVRWVNCVEJ
AS
5GNGEVQT
B
P92 (SCLK0/CTS0)
P95 (SCLK1/CTS1)
P9YTKVG
SCLK0,
SCLK1QWVRWV
S B
5GNGEVQT
P9TGCF
A
CTS0, CTS1
SCLK0, SCLK1KPRWV
Figure 4-18 Port 92 and 95
Page 77
2007-10-15
TMP91FW60
4.10.4 Port 96 (XT1), 97 (XT2)
In addition to functioning as a I/O port, port 96 and 97 can also function as low frequency oscillator connection pins.
4GUGV
.QYHTGSWGPE[QUEKNNCVKQPGPCDNG
Function
control (on bit basis)
2 (% YTKVG Direction
control (on bit basis)
2%4 YTKVG
5
1WVRWVNCVEJ
1WVRWVDWHHGT
2 YTKVG 5
$
5GNGEVQT
; #
Internal data bus
2
:6
2 TGCF 1PCV
Function
control (on bit basis) 2 (% YTKVG
Direction
control (on bit basis)
2%4 YTKVG
5
1WVRWVNCVEJ
2
:6
1WVRWVDWHHGT
2 YTKVG .QYHTGSWGPE[ENQEM
HU
5
$
5GNGEVQT
; #
2TGCF
Figure 4-19 Port 96 and 97
Page 78
2007-10-15
TMP91FW60
Port 9 Register
Bit symbol
P9
(0024H)
7
6
5
4
P97
P96
P95
P94
3
2
1
0
P93
P92
P91
P90
Read/Write
R/W
After reset
Data from external port (Output latch register is set to “1”.)
Port 9 Control Register (Read-modify-write instructions are prohibited.)
Bit symbol
P9CR
(0026H)
7
6
5
4
P97C
P96C
P95C
P94C
Read/Write
After reset
3
2
1
0
P93C
P92C
P91C
P90C
0
0
0
0
2
1
0
P92F
–
P90F
–
W
W
1
1
0
0
Function
0: Input 1: Output
Port 9 Function Register (Read-modify-write instructions are prohibited.)
Bit Symbol
P9FC
(0027H)
7
6
5
4
3
P97F
P96F
P95F
–
P93F
Read/Write
After reset
W
0
Port
0: disable
1: enable
Function
P97
function
0
Port
0: disable
1: enable
P96
function
–
0
–
0: port
1: SCLK1
output
P95
function
W
0
0: port
1: TXD1 output
P94
function
P93
function
0
–
0: port
1: SCLK0
output
P92
function
0
0: port
1: TXD0 output
P91
function
P90
function
P9xF
P9xC
0
0
XT2
XT1
input port
input port
input port
input port
input port
input port
0
1
reserved
reserved
output port
output port
output port
output port
output port
output port
1
0
input port
input port
reserved
reserved
reserved
reserved
reserved
reserved
1
1
output port
output port
SCLK1
reserved
TXD1
SCLK0
reserved
TXD0
Note 1: <P9xF>/<P9xC> is bit X of each register P9FC/P9CR.
Note 2: When setting TXD pin to open-drain output, write “1” to bit3 of ODE register (for TXD0 pin), or bit4 (for TXD1 pin). P91/
RXD0 and P94/RXD1 pin does not have a register which changes Port/Function.
For example, when it is also used as an input port, the input signal is inputted to SIO as serial receiving data.
Note 3: Low frequency oscillation circuit
To connect a low frequency resonator to port 96 and 97, it is necessary to set a following procedure to reduce the consumption power supply.
(Case of resonator connection)
P9CR<P96C, P97C> = “11”, P9<P96:97> = “00”
(Case of external clock input)
P9CR<P96C, P97C> = “11”, P9<P96:97> = “10”
Page 79
2007-10-15
TMP91FW60
4.11 Port A (PA0 to PA3)
Port A is an 4-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register
PA are set to “1”.
There are the following functions in addition to an I/O port. This function enable each function by writing “1” to
applicable bit of port A function register PAFC.
•The I/O function of 16-bit timer 2 (TB2IN0,TB2IN1,TB2OUT0,TB2OUT1)
•The input function of external interrupt (INT1, INT2)
Reset operation initializes, PACR and PAFC to “0”, all bits are set to input port.
4GUGV
Direction
control
(on bit basis)
PACRYTKVG
Function
control
(on bit basis)
PAFCYTKVG
S
1WVRWVNCVEJ
PA0 (TB2IN0/INT1)
PA1 (TB2IN1/INT2)
PAYTKVG
S B
5GNGEVQT
Internal data bus
A
PATGCF
TB2IN0, INT1
TB2IN1, INT2
4GUGV
Direction
control
(on bit basis)
PACRYTKVG
Function
control
(on bit basis)
PAFCYTKVG
S
1WVRWVNCVEJ
A S
5GNGEVQT
PA2 (TB2OUT0)
PA3 (TB2OUT1)
B
PAYTKVG
6KOGTF/F OUT
TB02UT0: TMRB2
TB02UT1: TMRB2
B
5GNGEVQT
S
PATGCF
Figure 4-20 Port A
Page 80
2007-10-15
TMP91FW60
Port A Register
7
PA
(0028H)
6
5
4
3
2
PA3
PA2
1
0
PA1
PA0
Bit symbol
–
–
–
–
Read/Write
–
–
–
–
R/W
After reset
–
–
–
–
Data from external port (Output latch register is set to “1”.)
Port A Control Register (Read-modify-write instructions are prohibited.)
7
PACR
(002AH)
6
5
4
3
2
PA3C
PA2C
Bit symbol
–
–
–
–
Read/Write
–
–
–
–
After reset
–
–
–
–
Function
–
–
–
–
1
0
PA1C
PA0C
0
0
W
0
0
0: Input 1: Output
Port A Function Register (Read-modify-write instructions are prohibited.)
7
PAFC
(002BH)
6
5
4
3
2
PA3F
PA2F
Bit symbol
–
–
–
–
Read/Write
–
–
–
–
After reset
–
–
–
–
Function
–
PA3
function
–
–
–
PA2
function
PA1
function
1
0
PA1F
PA0F
W
0
0: port
1: TB2OUT1
0
0:port
1: TB2OUT0
0
0: port
1: TB2IN1,
INT2
0
0: port
1: TB2IN0,
INT1
PA0
function
PAxC
PAxF
0
0
input port
input port
input port
input port
0
1
output port
output port
output port
output port
1
0
reserved
reserved
TB2IN1/ INT2
TB2IN0/INT1
1
1
TB2OUT1
TB2OUT0
reserved
reserved
Note: <PAxF>/<PAxC> is bit X of each register PAFC/PACR.
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2007-10-15
TMP91FW60
4.12 Port B (PB0 to PB3)
Port B is an 4-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register
PB are set to “1”.
There are the following functions in addition to an I/O port. This function enable each function by writing “1” to
applicable bit of port B function register PBFC.
•The I/O function of 16-bit timer 4 (TB4IN0,TB4IN1,TB4OUT0,TB4OUT1)
•The input function of external interrupt (INT9, INT10)
•The I/O function of serial bus interface 1 (SDA1, SCL1)
Reset operation initializes, PBCR and PBFC to “0”, all bits are set to input port.
4GUGV
Direction
control
(on bit basis)
PBCR write
Internal data bus
Function
control 2
(on bit basis)
PBFC2 write
S
1WVRWVNCVEJ
A
Open-drain
possible:
ODE<ODEB0,B1>
S
PB0(TB4IN0,INT9,SDA1)
PB1(TB4IN1,INT10,SCL1)
5GNGEVQT
PB write
B
SDA1QWVRWV
SCL1QWVRWV
Function
control
(on bit basis)
PBFC write
S B
5GNGEVQT
PBTGCF
A
TB4IN0,INT9
TB4IN1,INT10
SDA1KPRWV
SCL1KPRWV
2$(%
Figure 4-21 Port B0 and B1
Page 82
2007-10-15
TMP91FW60
4GUGV
Direction
control
(on bit basis)
Internal data bus
PBCR write
Function
control
(on bit basis)
PBFC write
S
1WVRWVNCVEJ
PB write
A
S
PB2(TB4OUT0)
PB3(TB4OUT1)
5GNGEVQT
B
TB4OUT0QWVRWV
TB4OUT1QWVRWV
S B
5GNGEVQT
PBTGCF
A
Figure 4-22 Port B2 and B3
Page 83
2007-10-15
TMP91FW60
Port B Register
7
PB
(002CH)
6
5
4
3
2
PB3
PB2
1
0
PB1
PB0
Bit symbol
–
–
–
–
Read/Write
–
–
–
–
R/W
After reset
–
–
–
–
Data from external port (Output latch register is set to “1”.)
Port B Control Register (Read-modify-write instructions are prohibited.)
7
PBCR
(002EH)
6
5
4
3
2
PB3C
PB2C
Bit symbol
–
–
–
–
Read/Write
–
–
–
–
After reset
–
–
–
–
Function
–
–
–
–
1
0
PB1C
PB0C
0
0
W
0
0
0: Input 1: Output
Port B Function Register (Read-modify-write instructions are prohibited.)
7
PBFC
(002FH)
6
5
4
3
2
PB3F
PB2F
Bit symbol
–
–
–
–
Read/Write
–
–
–
–
After reset
–
–
–
–
1
0
PB2F
PB0F
W
0
0
0
0
0
Port B Function Register 2 (Read-modify-write instructions are prohibited.)
PBFC2
(002DH)
7
6
5
4
3
2
1
Bit symbol
–
–
–
–
–
–
PB1F2
Read/Write
–
–
–
–
–
–
After reset
–
–
–
–
–
–
PB3
function
PB2
function
PB1
function
PB0F2
W
0
0
PB0
function
PBxC
PBxF
PBxF2
0
0
0
input port
input port
input port
input port
1
0
0
output port
output port
output port
output port
0
1
0
reserved
reserved
TB4IN1/INT10
TB4IN0/INT9
1
1
0
TB4OUT1
TB4OUT0
reserved
reserved
0
0
1
reserved
reserved
reserved
reserved
1
0
1
reserved
reserved
SCL1
SDA1
0
1
1
reserved
reserved
reserved
reserved
1
1
1
reserved
reserved
reserved
reserved
Note: <PBxF>/<PBxC> is bit X of each register PBFC/PBCR.
Page 84
2007-10-15
TMP91FW60
4.13 Port Z (PZ0 to PZ3)
Port Z is a 4-bit general-purpose I/O port (however PZ0 and PZ1 are only output port). Each bit can be set individually for input or output using the control register PZCR and function register PZFC. Reset operation initializes all
bits of output latch PZ to “1”, and the control register PZCR and function register PZFC to “0”. And PZ0 and PZ1
output “High”, and sets PZ2 and PZ3 to input port with pull-up resister.
In addition to functioning as a general-purpose I/O port, port Z can also function as the output for the CPU’s control/status signal.
If PZ0 is defined as RD signal output mode (<PZ0F> = “1”) and the output latch register <PZ0> is cleared to “0”,
RD strobe of PZ0 is outputted (for pseudo static RAM) even when accessing internal address.
If <PZ0 > remains “1”, RD strobe signal is output only when external address area is accessed.
4GUGV
Direction
control
(on bit basis)
PZFCYTKVG
S
1WVRWVNCVEJ
S
A
B
Selector
‫ޓ‬
PZ0 (RD)
PZ1 (WR)
Output buffer
PZYTKVG
RD, WR
PZTGCF
Figure 4-23 Port Z0 and Z1
Page 85
2007-10-15
TMP91FW60
Reset
Direction
control
(on bit basis)
Internal data bus
PZCR write
Function
control
(on bit basis)
PZFC write
P-ch
(Programmable
pull up)
S
A
Selector
S
1WVRWVNCVEJ
B
PZ2( HWR )
Output buffer
PZ write
HWR
PZ read
Reset
Direction
control
(on bit basis)
PZCR write
Internal data bus
Function
control
(on bit basis)
P-ch
PZFC write
(Programmable
pull up)
S
1WVRWVNCVEJ
A
B
Selector
S
PZ3(R/ W )
Output buffer
PZ write
R/ W
PZ read
Figure 4-24 Port Z2 and Z3
Page 86
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TMP91FW60
Port Z Register
7
PZ
(007DH)
6
5
4
3
2
PZ3
PZ2
Bit symbol
–
–
–
–
Read/Write
–
–
–
–
After reset
–
–
–
–
1
0
PZ1
PZ0
1
1
R/W
Data from external port
(Output latch register is set
to “1”.)
Function
0 (Output latch register):
Pull-up resistor OFF
1 (Output latch register):
Pull-up resistor ON
–
output mode
Port Z Control Register (Read-modify-write instructions are prohibited.)
Bit symbol
PZCR
(007EH)
7
6
5
4
3
2
1
0
–
–
–
–
PZ3C
PZ2C
–
–
–
–
0
–
–
Read/Write
–
–
–
–
After reset
–
–
–
–
Function
W
0
–
0:Input 1:Output
Port Z Function Register (Read-modify-write instructions are prohibited.)
Bit symbol
PZFC
(007FH)
7
6
5
4
3
2
1
0
–
–
–
–
PZ3F
PZ2F
PZ1F
PZ0F
0
0
0
Read/Write
–
–
–
–
After reset
–
–
–
–
0
W
Function
–
–
–
–
0: port
1:R/ W
0: port
1: HWR
0: port
1: WR
PZxF
PZxC
PZx
PZ3
function
PZ2
function
PZ1
function
PZ0
function
0
0
0
input port
input port
Output “0”.
Output “0”.
0
0
1
input port
input port
Output “1”.
Output “1”.
0
1
0
output port
output port
Output “0”.
Output “0”.
0
1
1
output port
output port
Output “1”.
Output “1”.
1
0
0
R/W
reserved
WR is output only during
external accesses.
Always output RD.(Correspond to pseudo SRAM)
1
0
1
R/W
reserved
WR is output only during
external accesses.
RD is output only during
external accesses.
1
1
0
reserved
HWR
WR is output only during
external accesses.
Always output RD.(Correspond to pseudo SRAM)
1
1
1
reserved
HWR
WR is output only during
external accesses.
RD is output only during
external accesses.
0: port
1: RD
Note 1: <PZxF>/<PZxC> is bit X of each register PZFC/PZCR.
Note 2: When port Z is used as input mode, PZ register controls internal pull-up resistor. Read-modify-write instruction is prohibited in input mode or I/O mode. Setting the internal pull-up resistor may be depended on the states of the input pin.
Page 87
2007-10-15
TMP91FW60
4.14 Open-drain Control
P30,P31,P41,P90,P93,PB0,PB1 can perform selection of an open-drain output per bit. Reset operation initializes
all bits of the control register ODE to “0” and sets to CMOS output.
Open-drain Control Register
ODE
(003FH)
7
6
5
4
3
2
1
0
Bit symbol
−
ODEB1
ODEB0
ODE93
ODE90
ODE41
ODE31
ODE30
Read/Write
−
After reset
−
0
0
0
0
0
0
R/W
0
0: CMOS output
1:Open drain output
Function
Page 88
2007-10-15
TMP91FW60
5. Chip Select/Wait Controller
On the TMP91FW60, four user specifiable address areas (CS0 to CS3) can be set. The data bus width and the
number of waits can be set independently for each address area (CS0 to CS3 and others).
The pins CS0 to CS3 (which can also function as port pins P40 to P43) are the respective output pins for the areas
CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the
chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to
be output, the port 6 function register P4FC,P4FC2 must be set.
The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the
memory address mask registers MAMR0 to MAMR3.
The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area.
The input pin controlling these states is the bus wait request pin (WAIT).
5.1 Specifying an Address Area
The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and memory
address mask registers (MAMR0 to MAMR3).
At each bus cycle, a compare operation is performed to determine if the address on the specified a location in the
CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the corresponding CS area. In
this case, the CS0 to CS3 pin outputs the chip select signal and the bus cycle operates in accordance with the settings
in chip select/wait control registers B0CS to B3CS. (See" 5.2 Chip Select/Wait Control Registers ".)
5.1.1
Memory start address registers
The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set
the upper 8 bits (A23 to A16) of the start address in <S23:16>. The lower 16 bits of the start address (A15 to
A0) are permanently set to 0. Accordingly, the start address can only be set in 64-Kbyte increments, starting
from 000000H. Figure 5-1 shows the relationship between the start address and the start address register value.
Memory Start Address Registers (for areas CS0 to CS3)
MSAR0
(00C8H)
Bit symbol
MSAR1
(00CAH)
After reset
MSAR2
(00CCH)
7
6
5
4
S23
S22
S21
S20
Read/Write
Function
3
2
1
0
S19
S18
S17
S16
1
1
1
1
R/W
1
1
1
1
Determine A23 to A16 of start address
(Set start addresses for areas CS0 to CS3.)
MSAR3
(00CEH)
Page 89
2007-10-15
TMP91FW60
Start address
Address
000000H
64 Kbytes
Value in start address register
(MSAR0 to MSAR3)
000000H
00H
010000H
01H
020000H
02H
030000H
03H
040000H
04H
050000H
05H
060000H
06H
to
to
FF0000H
FFH
FFFFFFH
Figure 5-1 Relationship between Start Address and Start Address Register Value
5.1.2
Memory address mask registers
Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by
specifying a mask for each bit of the start address set in memory start address registers MAMR0 to MAMR3.
The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus
address bits corresponding to bits set to “0” in these registers. Also, the address bits that can be masked by
MAMR0 to MAMR3 differ between CS0 to CS3 areas. Accordingly, the size that can be each area is different.
Memory Address Mask Register (for CS0 area)
Bit symbol
MAMR0
(00C9H)
7
6
5
4
3
2
1
0
V20
V19
V18
V17
V16
V15
V14 to V9
V8
1
1
1
1
1
1
1
1
Read/Write
After reset
R/W
Function
Set size of CS0 area
0: Used for address compare
Note: Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes.
Memory Address Mask Register (CS1)
Bit symbol
MAMR1
(00CBH)
7
6
5
4
3
2
1
0
V21
V20
V19
V18
V17
V16
V15 to V9
V8
1
1
1
1
1
1
1
1
Read/Write
After reset
R/W
Function
Set size of CS1 area
0: Used for address compare
Note: Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes.
Memory Address Mask Register (CS2, CS3)
MAMR2
(00CDH)
Bit symbol
MAMR3
(00CFH)
After reset
7
6
5
4
3
2
1
0
V22
V21
V20
V19
V18
V17
V16
V15
1
1
1
1
1
1
1
1
Read/Write
Function
R/W
Set size of CS1 area
0: Used for address compare
Note: Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes.
Page 90
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TMP91FW60
5.1.3
Setting memory start addresses and address areas
Figure 5-2 shows an example of specifying a 64-Kbyte address area starting from 010000H using the CS0
areas.
Set “01H” in memory start address register MSAR0<S23:16> (Corresponding to the upper 8 bits of the start
address). Next, calculate the difference between the start address and the anticipated end address (01FFFFH).
Bits 20 to 8 of the result correspond to the mask value to be set for the CS0 area. Setting this value in memory
address mask register MAMR0<V20:8> sets the area size.
This example sets “07H” in MAMR0 to specify a 64-Kbyte area.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
F
1
1
1
1
F
1
1
1
1
F
1
1
F
ࡔࡕ࡝⚳ੌ
H ࠕ࠼࡟ࠬ
S23 S22 S21 S20 S19 S18 S17 S16
MSAR0
0
0
0
0
0
0
0
0
ࡔࡕ࡝
ࠬ࠲࡯࠻
ࠕ࠼࡟ࠬ
1
1
H
V14 ~ V9
V20 V19 V18 V17 V16 V15
MSMR0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
V8
1
1
1
7
1
1
1
1
1
1
1
1
CS0ⓨ㑆
ࠨࠗ࠭
(64 Kࡃࠗ࠻)
ࡔࡕ࡝ࠕ࠼࡟ࠬ
ࡑࠬࠢ࡟ࠫࠬ࠲
⸳ቯ୯
H
"07H"ࠍ⸳ቯߔࠆߎߣߢ64 Kࡃࠗ࠻ⓨ㑆ࠍᜰቯߢ߈߹ߔ‫ޕ‬
Figure 5-2 Example Showing How to Set the CS0 Area
After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to “FFH”. B0CS<B0E>, B1CS<B1E>
and B3CS<B3E> are reset to “0”. This disables the CS0, CS1 and CS3 areas. However, as B2CS<B2M> to “0”
and B2CS<B2E> to “1”, CS2 is enabled “002000 to FDFFFF” in TMP91FW60. Also, the bus width and number of waits specified in BEXCS are used for accessing addresses outside the specified CS0 to CS3 area.
Page 91
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TMP91FW60
5.1.4
Address area size specification
Table 5-1 shows the relationship between CS area and area size. “Δ” indicates areas that cannot be set by
memory start address register and address mask register combinations. When setting an area size using a combination indicated by “Δ”, set the start address mask register in the desired steps starting from 000000H.
If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the smaller CS area number has the higher
priority.
5.1.4.1
To set the area size for CS0 to 128 Kbytes:
Example: Valid
start addresses
000000H
↓ (128 Kbytes)
020000H
↓ (128 Kbytes)
Any of these addresses may be set as the start address.
040000H
↓
(128 Kbytes)
060000H
:
Example: Invalid
start addresses
000000H
↓
(64 Kbytes)
010000H
This is not an integer multiple of the desired area size setting.
Hence, none of these addresses can be set as the start address.
↓ (128 Kbytes)
030000H
↓ (128 Kbytes)
050000H
:
Table 5-1
Valid Area Sizes for Each CS Area
CS area
Size (Bytes)
256
512
32 K
64 K
128 K
256 K
512 K
1M
2M
4M
CS0
Ο
Ο
Ο
Ο
Δ
Δ
Δ
Δ
Δ
CS1
Ο
Ο
Ο
Δ
Δ
Δ
Δ
Δ
Δ
8M
CS2
Ο
Ο
Δ
Δ
Δ
Δ
Δ
Δ
Δ
CS3
Ο
Ο
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Note: “Δ” indicates areas that cannot be set by memory start address register and address mask register combinations.
Page 92
2007-10-15
TMP91FW60
5.2 Chip Select/Wait Control Registers
The master enable/disable, chip select output waveform, data bus width and number of wait states for each
address area (CS0 to CS3 and others) are set in their respective chip select/wait control registers, B0CS to B3CS and
BEXCS.
Chip Select/Wait Control Registers
7
B0CS
(00C0H)
RMW
instructions
are prohibited.
B1CS
(00C1H)
RMW
instructions
are prohibited.
B2CS
(00C2H)
RMW
instructions
are prohibited.
B3CS
(00C3H)
RMW
instructions
are prohibited.
6
5
4
3
B0OM1
B0OM0
B0BUS
Bit symbol
B0E
-
Read/Write
W
-
After reset
0
-
Function
Bit symbol
B1E
Read/Write
W
-
After reset
0
-
Function
B2E
Read/Write
W
After reset
1
0: Disable
1: Enable
B2M
0
CS2 area
selection
0: 16-Mbyte
area
1: CS area
B3E
Read/Write
W
-
After reset
0
-
0
B0W1
B0W0
0
0
0
Number of waits
Data bus
width
0: 16 bits
1: 8 bits
B1OM0
B1BUS
0
0
0
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
B1W2
B1W1
B1W0
0
0
0
W
B2OM1
B2OM0
-
0
Number of waits
Data bus
width
0: 16 bits
1: 8 bits
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
B2BUS
0
Chip select output waveform
selection
00: For ROM/SRAM
01: Don’t care
10: Don’t care
11: Don’t care
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
B2W2
B2W1
B2W0
0
0
0
Number of waits
Data bus
width
0: 16 bits
1: 8 bits
B3OM0
B3BUS
0
0
0
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
B3W2
B3W1
B3W0
0
0
0
W
Chip select output waveform
selection
00: For ROM/SRAM
01: Don’t care
10: Don’t care
11: Don’t care
0: Disable
1: Enable
0
B3OM1
Number of waits
Data bus
width
0: 16 bits
1: 8 bits
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
CS2 area selection
0
Disable
0
16-Mbyte area
1
Specified address area
B2M
1
Enable
Chip select output waveform selection
00
BnOM1:0
(n = 0 to 3)
B0W2
0
B1OM1
Master enable bit
BnE
(n = 0 to 3)
0
W
Bit symbol
Function
0
Chip select output waveform
selection
00: For ROM/SRAM
01: Don’t care
10: Don’t care
11: Don’t care
0: Disable
1: Enable
Bit symbol
Function
-
1
W
Chip select output waveform
selection
00: For ROM/SRAM
01: Don’t care
10: Don’t care
11: Don’t care
0: Disable
1: Enable
2
Data bus width selection
for ROM/SRAM
BnBUS
(n = 0 to EX)
01
10
0
16-bit data bus
1
8-bit data bus
Don’t care
11
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2007-10-15
TMP91FW60
BEXCS
(00C7H)
RMW
instructions
are prohibited.
7
6
5
4
3
2
Bit symbol
–
–
–
–
BEXBUS
BEXW2
Read/Write
–
–
–
–
After reset
–
–
–
–
1
0
BEXW1
BEXW0
0
0
W
0
0
Number of waits
Data bus
width
0: 16 bits
1: 8 bits
Function
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
Number of address area waits
BnW2:0
(n = 0 to EX)
5.2.1
See" 5.2.3 Wait control "
Master enable bits
Bit7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the master bit which is used
to enable or disable settings for the corresponding address area. Writing “1” to this bit enables the settings.
Reset disables (Sets to “0”) <B0E>, <B1E> and <B3E>, and enabled (Sets to “1”) <B2E>. This enables area
CS2 only.
5.2.2
Data bus width selection
Bit3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip select/wait control register
specifies the width of the data bus. This bit should be set to “0” when memory is to be accessed using a 16-bit
data bus and to “1” when an 8-bit data bus is to be used.
This process of changing the data bus width according to the address being accessed is known as “Dynamic
bus sizing”. For details of this bus operation see Table 5-2.
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TMP91FW60
Table 5-2 Dynamic Bus Sizing
Operand Data
Bus Width
CPU Data
Operand Start
Address
Memory Data
Bus Width
CPU Address
2n + 0
(Even number)
8 bits
D15 to D8
D7 to D0
2n + 0
xxxxx
b7 to b0
16 bits
2n + 0
xxxxx
b7 to b0
8 bits
2n + 1
xxxxx
b7 to b0
16 bits
2n + 1
b7 to b0
xxxxx
8 bits
2n + 0
2n + 1
xxxxx
xxxxx
b7 to b0
b15 to b8
16 bits
2n + 0
b15 to b8
b7 to b0
8 bits
2n + 1
2n + 2
xxxxx
xxxxx
b7 to b0
b15 to b8
16 bits
2n + 1
2n + 2
b7 to b0
xxxxx
xxxxx
b15 to b8
8 bits
2n + 0
2n + 1
2n + 2
2n + 3
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b15 to b8
b23 to b16
b31 to b24
16 bits
2n + 0
2n + 2
b15 to b8
b31 to b24
b7 to b0
b23 to b16
8 bits
2n + 1
2n + 2
2n + 3
2n + 4
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b15 to b8
b23 to b16
b31 to b24
16 bits
2n + 1
2n + 2
2n + 4
b7 to b0
b23 to b16
xxxxx
xxxxx
b15 to b8
b31 to b24
8 bits
2n + 1
(Odd number)
2n + 0
(Even number)
16 bits
2n + 1
(Odd number)
2n + 0
(Even number)
32 bits
2n + 1
(Odd number)
Note:“xxxxx” indicates that the input data from these bits are ignored during a read. During a write, indicates that
the bus for these bits goes too high impedance; also, that the write strobe signal for the bus remains inactive.
5.2.3
Wait control
Bits 0 to 2 (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, <BEXW0:2>) of a chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed.
The following types of wait operation can be specified using these bits. Bit settings other than those listed in
the table should not be made. A reset sets these bit to “000” (2 waits).
Table 5-3
Wait Operation Settings
<BxW2:0>
Number of Waits
Wait Operation
000
2 waits
Inserts a wait of 2 states, irrespective of the WAIT pin state.
001
1 wait
Inserts a wait of 1 state, irrespective of the WAIT pin state.
010
(1 + N) waits
011
0 waits
100
Reserved
101
3 waits
Inserts a wait of 3 state, irrespective of the WAIT pin state.
110
4 waits
Inserts a wait of 4 state, irrespective of the WAIT pin state.
111
8 waits
Inserts a wait of 8 state, irrespective of the WAIT pin state.
Samples the state of the WAIT pin after inserting a wait of one state. If the WAIT pin is
low, the waits continue and the bus cycle is extended until the pin goes high.
Ends the bus cycle without a wait, regardless of the WAIT pin state.
Invalid setting
Page 95
2007-10-15
TMP91FW60
5.2.4
Bus width and wait control for an area other than CS0 to CS3
The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3.
5.2.5
Selecting 16-Mbyte area/specified address area
Setting B2CS<B2M> (Bit6 of the chip select/wait control register for CS2) to “0” designates the 16-Mbyte
area “002000 to FDFFFF” as the CS2 area. Setting B2CS<B2M> to “1” designates the address area specified
by the start address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if B2CS<B2M> = 1,
CS2 is specified in the same manner as CS0, CS1 and CS3 are).
A reset clears this bit to “0”, specifying CS2 as a 16-Mbyte address area.
5.2.6
Procedure for setting chip select/wait control
When using the chip select/wait control function, set the registers in the following order:
1. Set the memory start address registers MSAR0 to MSAR3.
Set the start addresses for CS0 to CS3.
2. Set the memory address mask registers MAMR0 to MAMR3.
Set the sizes of CS0 to CS3.
3. Set the chip select/wait control registers B0CS to B3CS.
Set the chip select output waveform, data bus width, number of waits and master enable/disable status for
CS0 to CS3.
The CS0 to CS3 pins can also function as pins P40 to P43. To output a chip select signal using one of these
pins, set the corresponding bit in the port 6 function register P4FC/P4FC2 to “1”.
If a CS0 to CS3 address is specified which is actually an internal I/O and RAM area address, the CPU
accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins.
Example :In this example CS0 is set to the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the
number of waits is set to 0.
LD
(MSAR0), 01H
; Start address: 010000H
LD
(MAMR0), 07H
; Address area: 64 Kbytes
LD
(B0CS), 83H
; ROM/SRAM, 16-bit data bus, 0 waits, CS0 area settings enabled
Page 96
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TMP91FW60
5.3 Connecting External Memory
Figure 5-3 shows an example of how to connect external memory to TMP91FW60.
In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus.
TMP91FW60
CS0
74AC573
D Q
CS1
CS2
ALE
Address bus
LE
D Q
LE
CS
CS
CS
OE
OE
OE WE
Upper byte
ROM
Lower byte
ROM
8-bit bus
RAM
CS
8-bit bus
I/O
OE WE
AD8~AD15
AD0~AD7
RD
WR
Figure 5-3 Example of External Memory Connection
(ROM uses 16-bit bus, RAM and I/O use 8-bit bus.
A reset clears all bits of the port 4 control register P4CR and the port 4 function register P4FC/P4FC2 to “0” and
disables output of the CS signal. To output the CS signal, the appropriate bit must be set to “1”.
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TMP91FW60
6. 8-Bit Timers (TMRA)
The TMP91FW60 features 6 channels (TMRA0 to TMRA5) built-in 8-bit timers.
These timers are paired into 3 modules: TMRA01, TMRA23 and TMRA45. Each module consists of 2 channels
and can operate in any of the following 4 operating modes.
• 8-bit interval timer mode
• 16-bit interval timer mode
• 8-bit programmable square wave pulse generation output mode (PPG – Variable duty cycle with variable
period)
• 8-bit pulse width modulation output mode (PWM – Variable duty cycle with constant period)
Figure 6-1 to Figure 6-3 show block diagrams for TMRA01, TMRA23 and TMRA45.
Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer
flip-flop and a prescaler are provided for each pair of channels.
The operation mode and timer flip-flops are controlled by 5-byte registers SFRs (Special function registers).
Each of the three modules (TMRA01, TMRA23 and TMRA45) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here.
Table 6-1
Registers and Pins for Each Module
Module
TMRA01
Specification
TMRA23
TMRA45
Input pin for external clock
TA0IN
(Shared with P70)
None
TA4IN
(Shared with P73)
Output pin for timer flip-flop
TA1OUT
(Shared with P71)
TA3OUT
(Shared with P72)
TA5OUT
(Shared with P74)
Timer run register
TA01RUN
(0100H)
TA23RUN
(0108H)
TA45RUN
(0110H)
Timer register
TA0REG
(0102H)
TA1REG
(0103H)
TA2REG
(010AH)
TA3REG
(010BH)
TA4REG
(0112H)
TA5REG
(0113H)
Timer mode register
TA01MOD
(0104H)
TA23MOD
(010CH)
TA45MOD
(0114H)
Timer flip-flop control register
TA1FFCR
(0105H)
TA3FFCR
(010DH)
TA5FFCR
(0115H)
External pin
SFR
(Address)
Page 98
2007-10-15
External input
clock: TA0IN
Prescaler
clock: T0
Page 99
Prescaler
T4
T16
n
Internal data bus
Register buffer 0
8-bit timer register
TA0REG
8-bit comparator
(CP0)
T1
T16
T256
TA01MOD
<TA1CLK1:0>
Selector
TMRA0
match output:
TA0TRG
TA01MOD
<TA01M1:0>
TA0TRG
TMRA0
interrupt output:
INTTA0
Match
detect
2
overflow
TA01MOD
<PWM01:00>
8-bit up counter
(UC0)
<TA01PRUN>
Run/clear TA01RUN
T256
8 16 32 64 128 256 512
TA01MOD
<TA0CLK1:0>
TA01RUN
<TA0RDE>
T1
T4
T16
4
Selector TA01RUN<TA0RUN>
T1
2
Internal data bus
8-bit timer register
TA1REG
TA1FFCR
TMRA1
interrupt output:
INTTA1
Match
detect
8-bit comparator
(CP1)
8-bit up counter
(UC1)
TA01RUN
<TA1RUN>
Timer
flip-flop
TA1FF
Timer flip-flop
output:
TA1OUT
TMP91FW60
6.1 Block Diagrams
Figure 6-1 TMRA01 Block Diagram
2007-10-15
Prescaler
clock: T0
Page 100
Prescaler
T4
T16
2n
Internal data bus
Register buffer 2
8-bit timer register
TA2REG
8-bit comparator
(CP2)
T1
T16
T256
TA23MOD
<TA3CLK1:0>
Selector
TMRA2
match output:
TA2TRG
TA23MOD
<TA23M1:0>
TA2TRG
TMRA2
interrupt output:
INTTA2
Match
detect
overflow
TA23MOD
<PWM21:20>
8-bit up counter
(UC2)
<TA23PRUN>
Run/clear TA23RUN
T256
8 16 32 64 128 256 512
TA23MOD
<TA2CLK1:0>
TA23RUN
<TA2RDE>
T1
T4
T16
4
Selector TA23RUN<TA2RUN>
T1
2
Internal data bus
8-bit timer register
TA3REG
TA3FFCR
TMRA3
interrupt output:
INTTA3
Match
detect
8-bit comparator
(CP3)
8-bit up counter
(UC3)
TA23RUN
<TA3RUN>
Timer
flip-flop
TA3FF
Timer flip-flop
output:
TA3OUT
TMP91FW60
Figure 6-2 TMRA23 Block Diagram
2007-10-15
External input
clock: TA4IN
Prescaler
clock: T0
Page 101
Prescaler
T4
T16
n
Internal data bus
Register buffer 4
8-bit timer register
TA4REG
8-bit comparator
(CP4)
T1
T16
T256
TA45MOD
<TA5CLK1:0>
Selector
TMRA4
match output:
TA4TRG
TA45MOD
<TA45M1:0>
TA4TRG
TMRA4
interrupt output:
INTTA4
Match
detect
2
overflow
TA45MOD
<PWM41:40>
8-bit up counter
(UC4)
<TA45PRUN>
Run/clear TA45RUN
T256
8 16 32 64 128 256 512
TA45MOD
<TA4CLK1:0>
TA45RUN
<TA4RDE>
T1
T4
T16
4
Selector TA45RUN<TA4RUN>
T1
2
Internal data bus
8-bit timer register
TA5REG
TA5FFCR
TMRA5
interrupt output:
INTTA5
Match
detect
8-bit comparator
(CP5)
8-bit up counter
(UC5)
TA45RUN
<TA5RUN>
Timer
flip-flop
TA5FF
Timer flip-flop
output:
TA5OUT
TMP91FW60
Figure 6-3 TMRA45 Block Diagram
2007-10-15
TMP91FW60
6.2 Operation of Each Circuit
6.2.1
Prescalers
A 9-bit prescaler generates the input clock to TMRA01.
The “φT0” as the input clock to prescaler is a clock divided by 4 which is selected using the prescaler clock
selection register SYSCR0<PRCK1>.
The prescaler’s operation can be controlled using TA01RUN<TA01PRUN> in the timer control register. Setting <TA01PRUN> to “1” starts the count; setting <TA01PRUN> to “0” clears the prescaler to “0” and stops
operation. Table 6-2 shows the various prescaler output clock resolutions.
Table 6-2 Prescaler Output Clock Resolution
@ fc = 20 MHz, fs = 32.768 kHz
System Clock
Selection
SYSCR1<SYSCK>
Gear Value
SYSCR1<GEAR2:0>
1 (fs)
Prescaler Output Clock Resolution
φT1
(1/2)
φT4
(1/8)
φT16
(1/32)
φT256
(1/512)
XXX
23/fs (244 μs)
25/fs (977 μs)
27/fs (3.9 ms)
211/fs (62.5 ms)
000 (fc)
23/fc (0.4 μs)
25/fc (1.6 μs)
27/fc(6.4 μs)
211/fc (102.4 μs)
24/fc (0.8 μs)
26/fc (3.2 μs)
28/fc (12.8 μs)
212/fc (204.8 μs)
25/fc (1.6 μs)
27/fc (6.4 μs)
29/fc (25.6 μs)
213/fc (409.6 μs)
011 (fc/8)
26/fc (3.2 μs)
28/fc (12.8 μs)
210/fc (51.2 μs)
214/fc (819.2 μs)
100 (fc/16)
27/fc (6.4 μs)
29/fc (25.6 μs)
211/fc (102.4 μs)
215/fc (1638.4 μs)
27/fc (6.4 μs)
29/fc (25.6 μs)
211/fc (102.4 μs)
215/fc (1638.4 μs)
001 (fc/2)
010 (fc/4)
0 (fc)
Prescaler Clock
Selection
SYSCR0<PRCK1>
XXX
0 (1/1)
fFPH
1 (1/16)
fc/16 CLOCK
Note: xxx: Don’t care
6.2.2
Up counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD.
The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of
the three internal clocks φT1, φT4, or φT16. The clock setting is specified by the value set in
TA01MOD<TA01CLK1:0>.
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the overflow output from
UC0 is used as the input clock. In any mode other than 16-bit timer mode, the input clock is selectable and can
either be one of the internal clocks φT1, φT16 or φT256, or the comparator output (The match detection signal)
from TMRA0.
For each interval timer the timer operation control register bits TA01RUN<TA0RUN> and
TA01RUN<TA1RUN> can be used to stop and clear the up counters and to control their count. A reset clears
both up counters, stopping the timers.
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TMP91FW60
6.2.3
Timer registers (TA0REG and TA1REG)
These are 8-bit registers which can be used to set a time interval. When the value set in the timer register
TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal
goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows.
The TA0REG are double buffer structure, each of which makes a pair with register buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double buffer structure is
enabled or disabled. It is disabled if <TA0RDE> = “0” and enabled if <TA0RDE> = “1”.
When the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2n
overflow occurs in PWM mode, or at the start of the PPG cycle in PPG mode. Hence the double buffer cannot
be used in timer mode.
A reset initializes <TA0RDE> to “0”, disabling the double buffer. To use the double buffer, write data to the
timer register, set <TA0RDE> to “1”, and write the following data to the register buffer. Figure 6-4 shows the
configuration of TA0REG.
Timer registers 0 (TA0REG)
B
Y
Shift trigger
Register buffers 0
Selector A
Matching detection in PPG cycle
2n overflow PWM
Write to TA0REG
S
Write
Internal data bus
TA01RUN<TA0RDE>
Figure 6-4 Configuration of TA0REG
Note:The same memory address is allocated to the timer register TA0REG and the register buffer 0. When
<TA0RDE> = 0, the same value is written to the register buffer 0 and the timer register TA0REG; when
<TA0RDE> = 1, only the register buffer 0 is written to.
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TMP91FW60
6.2.4
Comparator (CP0 and CP1)
The comparator compares the value in an up counter with the value set in a timer register. If they match, the
up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion
is enabled, the timer flip-flop is inverted at the same time.
Note:If a value smaller than the up-counter value is written to the timer register while the timer is counting up, this
will cause the timer to overflow and an interrupt cannot be generated at the expected time. (The value in the
timer register can be changed without any problem if the new value is larger than the up-counter value.) In 16bit interval timer mode, be sure to write to both TA0REG and TA1REG in this order (16 bits in total), The compare circuit will not function if only the lower 8 bits are set.
6.2.5
Timer flip-flop (TA1FF)
The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of
each interval timer.
Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR<TA1FFIE> in the
timer flip-flop control register.
A reset clears the value of TA1FF1 to “0”.
Writing “01” or “10” to TA1FFCR<TA1FFC1:0> sets TA1FF to 0 or 1. Writing “00” to these bits inverts the
value of TA1FF (This is known as software inversion).
The TA1FF signal is output via the TA1OUT pin (Concurrent with P71). When this pin is used as the timer
output, the timer flip-flop should be set beforehand using the port 7 function registers P7CR, P7FC.
The condition for TA1FF inversion varies with mode as shown below
8-bit interval timer mode
: UC0 matches TA0REG or UC1 matches TA1REG
(Select either one of the two)
16-bit interval timer mode
: UC0 matches TA0REG or UC1 matches TA1REG
8 bit PWM mode
: UC0 matches TA0REG or a 2n overflow occurs
8 bit PPG mode
: UC0 matches TA0REG or UC0 matches TA1REG
Note: If an inversion by the match-detect signal and a setting change via the TMRA1 flip-flop control register occur simultaneously, the resultant operation varies depending on the situation, as shown below.
• If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the flip-flop will be
inverted only once.
• If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur
simultaneously, the timer flip-flop will be set to 1.
• If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur
simultaneously the flip-flop will be cleared to 1.
Be sure to stop the timer before changing the flip-flop insertion setting.
If the setting is changed while the timer is counting, proper operation cannot be obtained.
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TMP91FW60
6.3 SFR
TMRA01 Run Register
TA01RUN
(0100H)
7
6
5
4
3
2
1
0
Bit symbol
TA0RDE
–
–
–
I2TA01
TA01PRUN
TA1RUN
TA0RUN
Read/Write
R/W
–
–
–
After Reset
0
–
–
–
0
0
Function
Double
buffer
0: Disable
1: Enable
R/W
0
IDLE2
0: Stop
1: Operate
Count operation
0
TMRA01
prescaler
Up counter
(UC1)
Up counter
(UC0)
0: Stop and clear
1: Run (count up)
TA0REG double buffer control
TA01PRUN
TA1RUN / TA0RUN
0
Stop and clear
0
Disable
1
Enable
TA0RDE
1
Run (Count up)
Note: The values of bits 4 to 6 of TA01RUN are "1" when read.
TMRA23 Run Register
TA23RUN
(0108H)
7
6
5
4
3
2
1
0
Bit symbol
TA2RDE
–
–
–
I2TA23
TA23PRUN
TA3RUN
TA2RUN
Read/Write
R/W
–
–
–
After Reset
0
–
–
–
0
0
Function
Double
buffer
0: Disable
1: Enable
R/W
0
IDLE2
0: Stop
1: Operate
Count operation
0
TMRA23
prescaler
Up counter
(UC3)
Up counter
(UC2)
0: Stop and clear
1: Run (count up)
TA2REG double buffer control
TA23PRUN
TA3RUN / TA2RUN
0
Stop and clear
0
Disable
1
Enable
TA2RDE
1
Run (Count up)
Note: The values of bits 4 to 6 of TA23RUN are "1" when read.
TMRA45 Run Register
TA45RUN
(0110H)
7
6
5
4
3
2
1
0
Bit symbol
TA4RDE
–
–
–
I2TA45
TA45PRUN
TA5RUN
TA4RUN
Read/Write
R/W
–
–
–
After Reset
0
–
–
–
0
0
Function
Double
buffer
0: Disable
1: Enable
0
IDLE2
0: Stop
1: Operate
Count operation
TA45PRUN
TA5RUN / TA4RUN
R/W
0
TMRA45
prescaler
Up counter
(UC5)
Up counter
(UC4)
0: Stop and clear
1: Run (count up)
TA4REG double buffer control
0
Stop and clear
0
Disable
1
Enable
TA4RDE
1
Run (Count up)
Note: The values of bits 4 to 6 of TA45RUN are "1" when read.
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TMP91FW60
TMRA01 Mode Register
Bit symbol
TA01MOD
(0104H)
7
6
5
4
3
2
1
0
TA01M1
TA01M0
PWM01
PWM00
TA1CLK1
TA1CLK0
TA0CLK1
TA0CLK0
0
0
0
0
Read/Write
After reset
Function
R/W
0
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
0
0
PWM cycle
00: Reserved
Input clock for TMRA1
00: TA0TRG
01: φT1
10: φT16
11: φT256
01: 26
10: 27
11: 28
Input clock for TMRA0
00: TA0IN pin
01: φT1
10: φT4
11: φT16
TMRA0 input clock selection
00
TA0INì¸óÕ
01
φT1
10
φT4
11
φT16
<TA0CLK1:0>
TMRA1 input clock selection
TA01MOD<TA01M1:0> ≠ 01
<TA1CLK1:0>
00
Comparator output from
TMRA0
01
φT1
10
φT16
11
φT256
TA01MOD<TA01M1:0> = 01
Overflow output from TMRA0
(16-bit timer mode)
PWM cycle selection
00
Reserved
01
26 × Clock source
10
27 × Clock source
11
28 × Clock source
<PWM01:00>
TMRA01 operation mode selection
00
8-bit timers 2ch
01
16-bit timer
10
8-bit PPG
11
8-bit PWM (TMRA0) + 8-bit timer (TMRA1)
<TA01M1:0>
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TMP91FW60
TMRA23 Mode Register
Bit symbol
TA23MOD
(010CH)
7
6
5
4
TA23M1
TA23M0
PWM21
PWM20
Read/Write
After reset
Function
3
2
1
0
TA3CLK1
TA3CLK0
TA2CLK1
TA2CLK0
0
0
0
0
R/W
0
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
0
0
PWM cycle
00: Reserved
Input clock for TMRA3
00: TA2TRG
01: φT1
10: φT16
11: φT256
01: 26
10: 27
11: 28
Input clock for TMRA2
00: Reserved
01: φT1
10: φT4
11: φT16
TMRA2 input clock selection
00
Reserved
01
φT1
10
φT4
11
φT16
<TA2CLK1:0>
TMRA3 input clock selection
TA23MOD<TA23M1:0> ≠ 01
<TA3CLK1:0>
00
Comparator output from
TMRA2
01
φT1
10
φT16
11
φT256
TA23MOD<TA23M1:0> = 01
Overflow output from TMRA2
(16-bit timer mode)
PWM cycle selection
00
Reserved
01
26 × Clock source
10
27 × Clock source
11
28 × Clock source
<PWM21:20>
TMRA23 operation mode selection
00
8-bit timers 2ch
01
16-bit timer
<TA23M1:0>
10
8-bit PPG
11
8-bit PWM (TMRA2) + 8-bit timer (TMRA3)
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TMP91FW60
TMRA45 Mode Register
Bit symbol
TA45MOD
(0114H)
7
6
5
4
TA45M1
TA45M0
PWM41
PWM40
Read/Write
After reset
Function
3
2
1
0
TA5CLK1
TA5CLK0
TA4CLK1
TA4CLK0
0
0
0
0
R/W
0
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
0
0
PWM cycle
00: Reserved
Input clock for TMRA5
00: TA4TRG
01: φT1
10: φT16
11: φT256
01: 26
10: 27
11: 28
Input clock for TMRA4
00: TA4IN pin
01: φT1
10: φT4
11: φT16
TMRA4 input clock selection
00
TA4IN
01
φT1
10
φT4
11
φT16
<TA4CLK1:0>
TMRA5 input clock selection
TA45MOD<TA45M1:0> ≠ 01
<TA5CLK1:0>
00
Comparator output from
TMRA4
01
φT1
10
φT16
11
φT256
TA45MOD<TA45M1:0> = 01
Overflow output from TMRA4
(16-bit timer mode)
PWM cycle selection
00
Reserved
01
26 × Clock source
10
27 × Clock source
11
28 × Clock source
<PWM41:40>
TMRA45 operation mode selection
00
8-bit timers 2ch
01
16-bit timer
<TA45M1:0>
10
8-bit PPG
11
8-bit PWM (TMRA4) + 8-bit timer (TMRA5)
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TMP91FW60
TMRA1 Flip-Flop Control Register
TA1FFCR
(0105H)
7
6
5
4
3
Bit symbol
–
–
–
–
TA1FFC1
Read/Write
–
–
–
–
After reset
–
–
–
–
2
1
TA1FFC0
TA1FFIE
R/W
1
TA1FFIS
R/W
1
0
TA1FF
control for
inversion
0: Disable
1: Enable
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don’t care
Function
0
0
TA1FF
inversion
select
0: TMRA0
1:TMRA1
Inverse signal for timer flip-flop 1 (TA1FF) (Don’t care except in 8-bit timer mode)
0
Inversion by TMRA0
1
Inversion by TMRA1
TA1FFIS
Inversion of TA1FF
0
Disabled
1
Enabled
TA1FFIE
Control of TA1FF
00
Inverts the value of TA1FF (Software inversion)
01
Sets TA1FF to “1”
10
Clears TA1FF to “0”
11
Don’t care
<TA1FFC1:0>
Note: The values of bits 4 to 7 of TA1FFCR are "1" when read.
TMRA3 Flip-Flop Control Register
TA3FFCR
(010DH)
7
6
5
4
3
2
1
0
Bit symbol
–
–
–
–
TA3FFC1
TA3FFC0
TA3FFIE
TA3FFIS
Read/Write
–
–
–
–
After reset
–
–
–
–
R/W
1
R/W
1
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don’t care
Function
0
TA3FF
control for
inversion
0: Disable
1: Enable
0
TA3FF
inversion
select
0: TMRA2
1:TMRA3
Inverse signal for timer flip-flop 3 (TA3FF) (Don’t care except in 8-bit timer mode)
0
Inversion by TMRA2
1
Inversion by TMRA3
TA3FFIS
Inversion of TA3FF
0
Disabled
1
Enabled
TA3FFIE
Control of TA3FF
00
Inverts the value of TA3FF (Software inversion)
01
Sets TA3FF to “1”
10
Clears TA3FF to “0”
11
Don’t care
<TA3FFC1:0>
Note: The values of bits 4 to 7 of TA3FFCR are "1" when read.
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TMP91FW60
TMRA5 Flip-Flop Control Register
TA5FFCR
(0115H)
7
6
5
4
3
2
1
0
Bit symbol
–
–
–
–
TA5FFC1
TA5FFC0
TA5FFIE
TA5FFIS
Read/Write
–
–
–
–
After reset
–
–
–
–
R/W
1
R/W
1
TA5FF
control for
inversion
0: Disable
1: Enable
00: Invert TA5FF
01: Set TA5FF
10: Clear TA5FF
11: Don’t care
Function
0
0
TA5FF
inversion
select
0: TMRA4
1:TMRA5
Inverse signal for timer flip-flop 5 (TA5FF) (Don’t care except in 8-bit timer mode)
0
Inversion by TMRA4
1
Inversion by TMRA5
TA5FFIS
Inversion of TA5FF
0
Disabled
1
Enabled
TA5FFIE
Control of TA5FF
00
Inverts the value of TA5FF (Software inversion)
01
Sets TA5FF to “1”
10
Clears TA5FF to “0”
11
Don’t care
<TA5FFC1:0>
Note: The values of bits 4 to 7 of TA5FFCR are "1" when read.
Timer Register
7
TA0REG
(0102H)
TA1REG
(0103H)
TA2REG
(010AH)
TA3REG
(010BH)
TA4REG
(0112H)
TA5REG
(0113H)
6
5
4
3
Bit symbol
–
Read/Write
W
After Reset
0
Bit symbol
–
Read/Write
W
After Reset
0
Bit symbol
–
Read/Write
W
After Reset
0
Bit symbol
–
Read/Write
W
After Reset
0
Bit symbol
–
Read/Write
W
After Reset
0
Bit symbol
–
Read/Write
W
After Reset
0
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6.4 Operation in Each Mode
6.4.1
8-bit timer mode
Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers.
Set its function or counter data for TMRA0 and TMRA1 after stop these registers.
6.4.1.1
Generating interrupts at a fixed interval (Using TMRA1)
To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the
operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable
the interrupt INTTA1 and start TMRA1 counting.
Example: To generate an INTTA1 interrupt every 12 μs at fc = 20 MHz, set each register as follows:
* Clock state
System clock
: High frequency (fc)
Prescaler clock
: fFPH
Clock gear
: 1 (fc)
MSB
LSB
7
6
5
4
3
2
1
0
TA01RUN
–
X
X
X
–
–
0
–
Stop TMRA1 and clear it to 0.
TA01MOD
0
0
X
X
0
1
X
X
Select 8-bit timer mode and select φT1 (0.4 μs at fc = 20 MHz) as the
input clock.
TA1REG
0
0
0
1
1
1
1
0
Set TA1REG to 12 μs ÷ φT1 = 30 = 1EH
INTETA01
X
1
0
1
X
–
–
–
Enable INTTA1 and set it to level 5.
TA01RUN
–
X
X
X
–
1
1
–
Start TMRA1 counting.
Note: X: Don’t care, –: No change
Select the input clock using Table 6-2.
Note: The input clocks for TMRA0 and TMRA1 are different from as follows.
TMRA0: TA0IN input, φT1, φT4 or φT16
TMRA1: Match output of TMRA0, φT1, φT16, φT256
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6.4.1.2
Generating a 50% duty ratio square wave pulse
The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the
timer output pin (TA1OUT).
Example: To output a 2.4 μs square wave pulse from the TA1OUT pin at fc = 20 MHz, use the following
procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0
or TMRA1 may be used.
* Clock state
System clock
: High frequency (fc)
Prescaler clock
: fFPH
Clock gear
: 1 (fc)
MSB
LSB
7
6
5
4
3
2
1
0
TA01RUN
–
X
X
X
–
–
0
–
Stop TMRA1 and clear it to 0.
TA01MOD
0
0
X
X
0
1
–
–
Select 8-bit timer mode and select φT1 (0.4 μs at fc = 20 MHz) as
the input clock.
TA1REG
0
0
0
0
0
0
1
1
Set the timer register to 2.4 μs ÷ φT1 ÷ 2 = 03H
TA1FFCR
X
X
X
X
1
0
1
1
Clear TA1FF to “0” and set it to invert on the match detects signal
from TMRA1.
P7CR
X
X
X
–
–
–
1
–
P7FC
X
X
X
–
–
–
1
–
TA01RUN
–
X
X
X
–
1
1
–
Set P71 to function as the TA1OUT pin.
Start TMRA1 counting.
Note: X: Don’t care, –: No change
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TMP91FW60
ǾT1
TA01RUN
<TA1RUN>
Bits 7 to 2
Up counter Bit1
0
Bit0
1
2
3
0
1
2
3
0
1
2
3
0
Comparator
timig
Comparator output
(Match detect)
INTTA1
UC1 clear
TA1FF
TA1OUT
0.9 Ǵs at fc = 20 MHz
Figure 6-5 Square Wave Output Timing Chart (50% duty)
6.4.1.3
Making TMRA1 count up on the match signal from the TMRA0 comparator
Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1.
Comparator output
(TMRA0 match)
TMRA0 up counter
(when TA0REG = 5)
TMRA1 up counter
(when TA1REG = 2)
1
2
3
4
5
1
1
2
3
2
4
5
1
2
3
1
TMRA1 match output
Figure 6-6 TMRA1 Count Up on Signal from TMRA0
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TMP91FW60
6.4.2
16-bit timer mode
A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1.
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set
TA01MOD<TA01M1:0> to 01.
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for TMRA1, regardless of
the value set in TA01MOD<TA1CLK1:0>. Table 6-2 shows the cycle of the input clock for TMRA0.
LSB 8-bit set to TA0REG and MSB 8-bit is for TA1REG. Please keep setting TA0REG first because setting
data for TA0REG inhibit its compare function and setting data for TA1REG permit it.
Example: To generate an INTTA1 interrupt every 0.4 [s] at fc = 20 MHz, set the timer registers TA0REG
and TA1REG as follows:
* Clock state
System clock
: High frequency (fc)
Prescaler clock
: fFPH
Clock gear
: 1 (fc)
If φT16 (27/fc μs at fc = 20 MHz) is used as the input clock for counting, set the following value in the registers: 0.4 s/(27/fc) μs ≒ 62500 = F424H (e.g., set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1
interrupt can be generated every 0.4 [s].
The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG,
though the up counter UC0 is not cleared and also INTTA0 is not generated.
In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which
the values in the up counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the
up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled,
the value of the timer flip-flop TA1FF is inverted.
Example: When TA1REG = 04H and TA0REG = 80H
Value of up counter
(UC1, UC0)
0080H
0180H
0280H
0380H
0480H
0080H
TMRA0 comparator
match detect signal
TMRA1 comparator
match detect signal
Interrupt INTTA0
Interrupt INTTA1
Inversion
Timer output TA1OUT
Figure 6-7 Timer Output by 16-Bit Timer Mode
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TMP91FW60
6.4.3
8-bit PPG (Programmable pulse generation) output mode
Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be
active low or active high. In this mode TMRA1 cannot be used.
TMRA0 outputs pulses on the TA1OUT pin.
tH
tL
<TA1FFC1:0> = "10"
t
tL
tH
<TA1FFC1:0> = "01"
t
Example: <TA1FFC1:0> = "01"
TA0REG and UC0 match
(Interrupt INTTA0)
TA1REG and UC0 match
(Interrupt INTTA1)
TA1OUT
TA0REG
TA1REG
Figure 6-8 8-Bit PPG Output Waveforms
In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up
counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG.
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN> should be set to
“1”, so that UC1 is set for counting.
Figure 6-9 shows a block diagram representing this mode.
TA1OUT
TA01RUN<TA0RUN>
Selector
TA1FF
TA0IN
T1
T4
T16
8-bit up counter
(UC0)
TA1FFCR<TA1FFIE>
Inversion
TA01MOD<TA0CLK1:0>
INTTA0
Comparator
Selector
Comparator
INTTA1
TA0REG
Shift trigger
TA0REG-WR
Register buffer
TA1REG
TA01RUN<TA0RDE>
Internal data bus
Figure 6-9 Block Diagram of 8-Bit PPG Output Mode
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TMP91FW60
If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into
TA0REG each time TA1REG matches UC0.
Use of the double buffer facilitates the handling of low-duty waves (when duty is varied).
Match with TA0REG
and up counter
(Up counter = Q1)
(Up counter = Q2)
Match wiht TA1REG
Shift from register buffer 0
Q1
TA0REG
(Value to be compared)
Q2
Q2
Register buffer
Q3
TA0REG (Register buffer 0)
write
Figure 6-10 Operation of Register Buffer 0
Note:The values that can be set in TAxREG range from 01h to 00h (equivalent to 100h). If the maximum value 00h
is set, the match-detect signal goes active when the up-counter overfolws.
Example: To generate 1/4-duty 50-kHz pulses (at fc = 20 MHz):
20Ǵs
* Clock state
System clock
: High frequency (fc)
Prescaler clock
: fFPH
Clock gear
: 1 (fc)
Calculate the value which should be set in the timer register.
To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 μs
φT1 = 23/fc μs (at fc = 20 MHz);
20 μs/(23/fc) μs = 50
Therefore set TA1REG to 50 (32H), and 50-kHz pulses can be obtained.
The duty is to be set to 1/4: t × 1/4 = 20 μs × 1/4 = 5 μs
5 μs/(23/fc) μs ≒ 13
Therefore, set TA0REG = 13 = 0DH.
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TMP91FW60
7
6
5
4
3
2
1
0
TA01RUN
0
X
X
X
–
–
0
0
Stop TMRA0 and TMRA01 and clear it to “0”.(Double buffer disable)
TA01MOD
1
0
X
X
X
X
0
1
Set the 8-bit PPG mode, and select φT1 as input clock.
TA0REG
0
0
0
0
1
1
0
1
Write 0DH.
TA1REG
0
0
1
1
0
0
1
0
Write 32H.
TA1FFCR
X
X
X
X
0
1
1
X
Set TA1FF, enabling both inversion and the double buffer.
Writing “10” provides negative logic pulse.
P7CR
X
X
X
–
–
–
1
–
P7FC
X
X
X
–
–
–
1
–
TA01RUN
1
X
X
X
–
1
1
1
Set P71 as the TA1OUT pin.
Start TMRA0 and TMRA01 counting.(Double buffer enable)
Note:X : Don't Care – : No change
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TMP91FW60
6.4.4
8-bit PWM output mode
This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can
be output.
When TMRA0 is used the PWM pulse is output on the TA1OUT pin. TMRA1 can also be used as an 8-bit
timer.
The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG
or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD<PWM01:00>). The up counter
UC0 is cleared when 2n counter overflow occurs.
The following conditions must be satisfied before this PWM mode can be used.
Value set in TA0REG < Value set for 2n counter overflow
Value set in TA0REG ≠ 0
TA0REG and
UC0 match
2n
overflow
(INTTA0 interrupt)
TA1OUT
tPWM
(PWM cycle)
Figure 6-11 8-Bit PWM Waveforms
Figure 6-12 shows a block diagram representing this mode.
TA0IN
T1
T4
T16
TA1OUT
TA01RUN<TA0RUN>
Selector
8-bit up counter
TA1FF
Clear
(UC0)
2n
overflow
control
TA01MOD<TA0CLK1:0>
TA1FFCR
<TA1FFIE>
Invert
TA01MOD
<PWM01:00>
Overflow
Comparator
INTTA0
Selector
TA0REG
Shift trigger
TA0REG-WR
Register buffer0
TA01RUN<TA0RDE>
Internal data bus
Figure 6-12 Block Diagram of 8-Bit PWM Mode
In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the
TA0REG double buffer is enabled.
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TMP91FW60
Use of the double buffer facilitates the handling of low duty ratio waves.
Match with TA0REG
(Up counter = Q1)
(Up counter = Q2)
2n overflow
Shift into TA0REG
Q1
TA0REG
(Value to be compared)
Q2
Q2
Register buffer 0
Q3
TA0REG (Register buffer 0)
write
Figure 6-13 Operation of Register Buffer 0
Example: To output the following PWM waves on the TA1OUT pin at fc = 20 MHz:
* Clock state
System clock
: High frequency (fc)
Prescaler clock
: fFPH
Clock gear
: 1 (fc)
To achieve a 51.2 μs PWM cycle by setting φT1 to 23/fc μs (at fc = 20 MHz):
51.2 μs/(23/fc) μs ≒ 128 = 2n
Therefore n should be set to 7.
Since the low-level period is 29.6 μs when φT1 = 23/fc μs (at fc = 20 MHz), set the following value for
TA0REG:
29.6 μs/(23/fc) μs ≒ 74 = 4AH
MSB
LSB
7
6
5
4
3
2
1
0
TA01RUN
–
X
X
X
–
–
–
0
Stop TMRA0 and clear it to 0.
TA01MOD
1
1
1
0
–
–
0
1
Select 8-bit PWM mode (Cycle: 27) and select φT1 as the input
clock.
TA0REG
0
1
0
0
1
0
1
0
Write 4AH.
TA1FFCR
X
X
X
X
1
0
1
X
Clear TA1FF to 0, enable the inversion and double buffer.
P7CR
X
X
X
–
–
–
1
–
P7FC
X
X
X
–
–
–
1
–
TA01RUN
1
X
X
X
–
1
–
1
Set P71 and the TA1OUT pin.
Start TMRA0 counting.
Note:X : Don't Care – : No change
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TMP91FW60
Table 6-3 PWM Cycle
Select System Clock
SYSCR1
<SYSCK>
Gear Value
SYSCR1
<GEAR2:0>
1 (fs)
PWM cycle
Select Prescaler
Clock
SYSCR0
<PRCK1>
26
27
φT4
XXX
15.6 ms
62.5 ms
250 ms
31.3 ms
125 ms
500 ms
62.5 ms
250 ms
1000 ms
000 (fc)
25.6 μs
102.4 μs
409.6 μs
51.2 μs
204.8 μs
819.2 μs
102.4 μs
409.6 μs
1638 μs
51.2 μs
204.8 μs
819.2 μs
102.4 μs
409.6 μs
1638 μs
204.8 μs
819.2 μs
3277 μs
102.4 μs
409.6 μs
1638 μs
204.8 μs
810.2 μs
3277 μs
409.6 μs
1638 μs
6554 μs
011 (fc/8)
204.8 μs
819.2 μs
3277 μs
409.6 μs
1638 μs
6554 μs
819.2 μs
3277 μs
13107 μs
100 (fc/16)
409.6 μs
1638 μs
6554 μs
819.2 μs
3277 μs
13107 μs
1638 μs
6554 μs
26214 μs
409.6 μs
1638 μs
6554 μs
819.2 μs
3277 μs
13107 μs
1638 μs
6554 μs
26214 μs
010 (fc/4)
XXX
0 (1/1)
fFPH
1 (1/16)
fc/16 clock
φT16
φT1
φT4
28
φT1
001 (fc/2)
0 (fc)
@ fc = 20 MHz, fs = 32.768 kHz
φT16
φT1
φT4
φT16
Note: xxx: Don't care
6.4.5
Settings for each mode
Table 6-4 shows the SFR settings for each mode.
Table 6-4 Timer Mode Setting Registers
Register Name
TA01MOD
TA1FFCR
<Bit Symbol>
<TA01M1:0>
<PWM01:00>
<TA1CLK1:0>
<TA0CLK1:0>
TA1FFIS
Function
Timer Mode
PWM Cycle
Upper Timer
Input Clock
Lower Timer
Input Clock
Timer F/F Invert
Signal Select
8-bit timer × 2 channels
00
–
Lower timer match
φT1, φT16, φT256
(00, 01, 10, 11)
External clock
φT1 φT4, φT16
(00, 01, 10, 11)
0: Lower timer output
1: Upper timer output
16-bit timer mode
01
–
–
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
–
8-bit PPG × 1 channel
10
–
–
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
–
8-bit PWM × 1 channel
11
26, 27, 28
(01, 10, 11)
–
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
–
8-bit timer × 1 channel
11
–
φT1, φT16, φT256
(01, 10, 11)
–
Output disabled
Note: – : Don’t care
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TMP91FW60
7. 16-Bit Timer/Event Counters (TMRB)
The TMP91FW60 incorporates five multifunctional 16-bit timer/event counters (TMRB0, TMRB1, TMRB2,
TMRB3, TMRB4) which have the following operation modes:
• 16-bit interval timer mode
• 16-bit event counter mode
• 16-bit programmable pulse generation (PPG) output mode
The capture function enables selection of the following modes:
• Frequency measurement mode
• Pulse width measurement mode
• Time differential measurement
Figure 7-1 show block diagrams for TMRB0, TMRB1, TMRB2, TMRB3 and TMRB4.
Each timer/event counter channel consists of a 16-bit up-counter, two 16-bit timer registers (one of them with a
double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, two timer flipflops and a timer flip-flop controller.
Each timer/event counter is controlled by an 11-byte SFR (special-function register).
Each of the five channels (TMRB0, TMRB1, TMRB2, TMRB3, TMRB4) can be used independently. Each channel features the same operations except for those described in Table 7-1. Hence, only the operation of TMRB0 is
explained below.
Table 7-1
Registers and Pins for TMRB
Channel
TMRB0
TMRB1
TMRB2
TMRB3
TMRB4
Specification
TB0IN0
(also used as P80)
TB1IN0
(also used as P84)
TB2IN0
(also used as PA0)
TB3IN0
(also used as P30)
TB4IN0
(also used as PB0)
TB0IN1
(also used as P81)
TB1IN1
(also used as P85)
TB2IN1
(also used as PA1)
TB3IN1
(also used as P31)
TB4IN1
(also used as PB1)
TB0OUT0
(also used as P82)
TB1OUT0
(also used as P86)
TB2OUT0
(also used as PA2)
TB3OUT0
(also used as P32)
TB4OUT0
(also used as PB2)
TB0OUT1
(also used as P83)
TB1OUT1
(also used as P87)
TB2OUT1
(also used as PA3)
TB3OUT1
(also used as P33)
TB4OUT1
(also used as PB3)
Timer run register
TB0RUN (0180H)
TB1RUN (0190H)
TB2RUN (01A0H)
TB3RUN (01B0H)
TB4RUN (01C0H)
Timer mode register
TB0MOD (0182H)
TB1MOD (0192H)
TB2MOD (01A2H)
TB3MOD (01B2H)
TB4MOD (01C2H)
Timer flip-flop control
register
TB0FFCR (0183H)
TB1FFCR (0193H)
TB2FFCR (01A3H)
TB3FFCR (01B3H)
TB4FFCR (01C3H)
TB0RG0L (0188H)
TB1RG0L (0198H)
TB2RG0L (01A8H)
TB3RG0L (01B8H)
TB4RG0L (01C8H)
TB0RG0H (0189H)
TB1RG0H (0199H)
TB2RG0H (01A9H)
TB3RG0H (01B9H)
TB4RG0H (01C9H)
TB0RG1L (018AH)
TB1RG1L (019AH)
TB2RG1L (01AAH)
TB3RG1L (01BAH)
TB4RG1L (01CAH)
TB0RG1H (018BH)
TB1RG1H (019BH)
TB2RG1H (01ABH)
TB3RG1H (01BBH)
TB4RG1H (01CBH)
TB0CP0L (018CH)
TB1CP0L (019CH)
TB2CP0L (01ACH)
TB3CP0L (01BCH)
TB4CP0L (01CCH)
TB0CP0H (018DH)
TB1CP0H (019DH)
TB2CP0H (01ADH)
TB3CP0H (01BDH)
TB4CP0H (01CDH)
TB0CP1L (018EH)
TB1CP1L (019EH)
TB2CP1L (01AEH)
TB3CP1L (01BEH)
TB4CP1L (01CEH)
TB0CP1H (018FH)
TB1CP1H (019FH)
TB2CP1H (01AFH)
TB3CP1H (01BFH)
TB4CP1H (01CFH)
External clock/capture
trigger input pins
External
pins
Timer flip-flop output
pins
SFR
(address)
Timer registers
Capture registers
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TAzOUT
(From TMRA)
TBnIN0
TBnIN1
External INT input
INTx
INTy
Prescaler clock:
ǾT0
ǾT1
2
ǾT4
Count clock
Timer
TMRB0
TMRB1
TMRB2
TMRB3
TMRB4
Page 122
TBnRUN
<TBnRDE>
n
0
1
2
3
4
INTx
INT5
INT7
INT1
INT3
INT9
INTy
INT6
INT8
INT2
INT4
INT10
Internal data bus
Internal data bus
16-bit
timer register
TBnRG1H/L
16-bit
comparator
(CPn1)
TBnRUN<TBnRUN>
TBnMOD<TBnCLE>
16-bit up-counter
(UCn)
Match
detection
Register buffer P
16-bit
timer register
TBnRG0H/L
16-bit
comparator
(CPn0)
TBnMOD
<TBnCLK1:0>
Selector
TBnMOD
<TBnCP0I>
ǾT1
ǾT4
ǾT16
TBnMOD
<TBnCPM1:0>
Capture register 1
TBnCP1H/L
Capture register 0
TBnCP0H/L
Run/
clear TBnRUN
<TBnPRUN>
ǾT16
8 16 32
Capture, external
INT input control
4
Internal data bus
Internal data bus
Match detection
Timer flip-flop
control
INT output
INTTBn0 INTTBn1
TBnOUT1
TBnFF1
Overflow
interrupt
INTTBOFn
Timer flip-flop
output
TBnOUT0
TBnFF0
Timer flip-flop
TMP91FW60
7.1 Block Diagrams
TAzOUT
TA1OUT
TA1OUT
TA1OUT
TA3OUT
TA5OUT
Figure 7-1 Block Diagrams of TMRB0 to TMRB4
2007-10-15
TMP91FW60
7.2 Operation of Each Block
7.2.1
Prescaler
The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0) is divided clock
(divided by 4) from selected clock by the register SYSCR0<PRCK1> of clock gear.
This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting starts when <TB0PRUN> is
set to 1; the prescaler is cleared to 0 and stops operation when <TB0PRUN> is cleared to 0. Table 7-2 show
prescaler output clock resolution.
Table 7-2
@fc = 20 MHz, fs = 32.768 kHz
Prescaler Output Clock Resolution
System Clock
SelectionSYSC1<
SYSCK>
1 (fs)
Clock Gear Value
Prescaler Output Clock Resolution
φT1
(1/2)
φT4
(1/8)
φT16
(1/32)
XXX
23/fs (244 μs)
25/fs (977 μs)
27/fs (3.9 ms)
000 (fc)
23/fc (0.4 μs)
25/fc (1.6 μs)
27/fc(6.4 μs)
24/fc (0.8 μs)
26/fc (3.2 μs)
28/fc (12.8 μs)
25/fc (1.6 μs)
27/fc (6.4 μs)
29/fc (25.6 μs)
011 (fc/8)
26/fc (3.2 μs)
28/fc (12.8 μs)
210/fc (51.2 μs)
100 (fc/16)
27/fc (6.4 μs)
29/fc (25.6 μs)
211/fc (102.4 μs)
27/fc (6.4 μs)
29/fc (25.6 μs)
211/fc (102.4 μs)
SYSCR1<GEAR2:0>
001 (fc/2)
010 (fc/4)
0 (fc)
Prescaler Clock
Selection
XXX
<PRCK1>
0 (1/1)
fFPH
1 (1/16)
fc/16 clock
Note: xxx: Don’t care
7.2.2
Up counter (UC0)
UC0 is a 16-bit binary counter which counts up according to input from the clock specified by
TB0MOD<TB0CLK1:0> register.
As the input clock, one of the prescaler internal clocks φT1, φT4 and φT16 or an external clock from TB0IN0
pin can be selected. Counting or stopping and clearing of the counter is controlled by timer operation control
register TB0RUN<TB0RUN>.
When clearing is enabled, the up counter UC0 will be cleared to 0 each time its value matches the value in
the timer register TB0RG1H/L. If clearing is disabled, the counter operates as a free-running counter. Clearing
can be enabled or disabled by using TB0MOD<TB0CLE>.
A timer overflow interrupt (INTTBOF0) is generated when UC0 overflow occurs.
7.2.3
Timer registers (TB0RG0H/L, TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the up counter UC0 matches
the value set in this timer register, the comparator match detect signal will go active.
Setting data for both upper and lower timer registers is needed. For example, using 2-byte data transfer
instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order. (The compare circuit will not operate if only the lower 8 bits are written. Be sure to write to both timer registers (16 bits)
from the lower 8 bits followed by the upper 8 bits.)
The TB0RG0H/L timer register has a double-buffer structure, which is paired with register buffer 0. The
value set in TB0RUN<TB0RDE> determines whether the double-buffer structure is enabled or disabled: it is
disabled when <TB0RDE> = "0", and enabled when <TB0RDE> = "1".
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TMP91FW60
When the double buffer is enabled, data is transferred from the register buffer 0 to the timer register when the
values in the up counter (UC0) and the timer register TB0RG1H/L match.
The double buffer circuit incorporates two flags to indicate whether or not data is written to the lower 8 bits
and the upper 8 bits of the register buffer, respectively. Only when both flags are set can data be transferred
from the register buffer to the timer register by a match between the up-counter UC0 and the timer register
TB0RG1. This data transfer is performed so long as 16-bit data is written in the register buffer regardless of the
register buffer to the timer register unexpectedly as explained below.
For example, let us assume that an interrupt occurs when only the lower 8 bits (L1) of the register buffer data
(H1L1) have been written and the interrupt routine includes writes to all 16 bits in the register buffer and a
transfer of the data to the timer register. In this case, if the higher 8 bits (H1) are written after the interrupt routine is completed, only the flag for the higher 8 bits will be set, the flag for the lower 8 bits having been cleared
in the interrupt routine. Therefore, even if a match occurs between UC0 and TB0RG1, no data transfer will be
performed.
Then, in an attempt to set the next set of data (H2L2) in the register buffer, when the lower 8 bits (L2) are
written, this will cause the flag for the lower 8 bits to be set as well as the flag for the higher 8 bits which has
been set by writing the previous data (H1). If a match between UC0 and TB0RG1 occurs before the higher 8
bits (H2) are written, this will cause unexpected data (H1L2) to be sent to the timer register instead of the
intended data (H2L2).
To avoid such transfer timing problems due to interrupts, the DI instruction (disable interrupts) and the EI
(enable interrupts) can be executed before and after setting data in the register buffer, respectively.
After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to be used after a reset, data
should be written to it beforehand.
On a reset <TB0RDE> is initialized to "0", disabling the double buffer. To use the double buffer, write data
to the timer register, set <TB0RDE> to "1", then write data to the register buffer 10 as shown below.
TB0RG0H/L and the register buffer 0 both have the same memory addresses (0188H and 0189H) allocated
to them. If <TB0RDE> = "0", the value is written to both the timer register and the register buffer 0. If
<TB0RDE> = "1", the value is written to the register buffer 0 only.
The addresses of the timer registers are as follows:
TMRB0
TB0RG0H/L
Upper 8 bits
000189H
TMRB1
TMRB4
Lower 8 bits
000198H
Upper 8 bits
00019BH
Lower 8 bits
00019AH
Upper 8 bits
0001ABH
Lower 8 bits
0001AAH
TB3RG1H/L
Lower 8 bits
0001B8H
TB4RG0H/L
Upper 8 bits
0001C9H
Lower 8 bits
00018AH
TB2RG1H/L
Lower 8 bits
0001A8H
TB3RG0H/L
Upper 8 bits
0001B9H
Upper 8 bits
00018BH
TB1RG1H/L
TB2RG0H/L
Upper 8 bits
0001A9H
TMRB3
Lower 8 bits
000188H
TB1RG0H/L
Upper 8 bits
000199H
TMRB2
TB0RG1H/L
Upper 8 bits
0001BBH
Lower 8 bits
0001BAH
TB4RG1H/L
Lower 8 bits
0001C8H
Upper 8 bits
0001CBH
Lower 8 bits
0001CAH
Note:The timer registers are write-only registers and thus cannot be read.
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TMP91FW60
7.2.4
Capture registers (TB0CP0H/L, TB0CP1H/L)
These 16-bit registers are used to latch the values in the up counter (UC0).
Data in the capture registers should be read all 16 bits. For example, using a 2-byte data load instruction or
two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte.
(during capture is read, capture operation is prohibited. In that case, the lower 8 bits should be read first, followed by the 8 bits.)
The addresses of the capture registers are as follows;
TMRB0
TMRB1
TMRB2
TMRB3
TMRB4
TB0CP0H/L
TB0CP1H/L
Upper 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
00018DH
00018CH
00018FH
00018EH
TB1CP0H/L
TB1CP1H/L
Upper 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
00019DH
00019CH
00019FH
00019EH
TB2CP0H/L
TB2CP1H/L
Upper 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
0001ADH
0001ACH
0001AFH
0001AEH
TB3CP0H/L
TB3CP1H/L
Upper 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
0001BDH
0001BCH
0001BFH
0001BEH
TB4CP0H/L
TB4CP1H/L
Upper 8 bits
Lower 8 bits
Upper 8 bits
Lower 8 bits
0001CDH
0001CCH
0001CFH
0001CEH
Note:The capture registers are read-only registers and thus cannot be written to.
7.2.5
Capture Input Control and External Interrupt Control
This circuit controls the timing to latch the value of up-counter UC0 into TB0CP0H/L and TB0CP1H/L, and
generates external interrupt.The latch timing of capture register and selection of edge for external interrupt is
controlled by TB0MOD<TB0CPM1:0>.
The value in the up-counter (UC0) can be loaded into a capture register by software. Whenever 0 is written
to TB0MOD<TB0CP0I>, the current value in the up counter (UC0) is loaded into capture register TB0CP0H/
L. It is necessary to keep the prescaler in RUN mode (e.g., TB0RUN<TB0PRUN> must be held at a value of
1).
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TMP91FW60
7.2.6
Comparators (CP00, CP01)
CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC0 with the value set in
TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator
generates an interrupt (INTTB00 or INTTB01 respectively).
7.2.7
Timer flip-flops (TB0FF0, TB0FF1)
These flip-flops are inverted by the match detect signals from the comparators and the latch signals to the
capture registers. Inversion can be enabled and disabled for each element using TB0FFCR<TB0C0T1,
TB0E1T1, TB0E0T1>.
After a reset the value of TB0FF0 is undefined. If "00" is written to TB0FFCR <TB0FF0C1:0> or
<TB0FF1C1:0>, TB0FF0 will be inverted. If "01" is written to the capture registers, the value of TB0FF0 will
be set to "1". If "10" is written to the capture registers, the value of TB0FF0 will be set to "0".
Note:If an inversion by the match-detect signal and a setting change via the TB0FFCR register occurs simultaneously, the resultant operation varies depending on the situation, as shown below.
• If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the flip-flop will be
inverted only once.
• If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur simultaneously,
the flip-flop will be set to 1.
• If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur simultaneously, the flip-flop will be cleared to 0.
If an inversion by match-detect signal and inversion disable setting occur simultaneously, two case (it is inverted and it
is not inverted) are occurred. Therefore, if changing inversion control (inversion enable/disable), stop timer operation
beforehand.
The values of TB0FF0 and TB0FF1 can be output via the timer output pins TB0OUT0 (which is shared with
P82 and TB0OUT1 (which is shared with P83). Timer output should be specified using the port P function register.
Page 126
2007-10-15
TMP91FW60
7.3 SFR
TMRB Run Register
7
TB0RUN
(0180H)
2
1
0
–
–
–
I2TB0
TB0PRUN
–
TB0RUN
R/W
R/W
–
–
R/W
R/W
–
R/W
After reset
0
0
0
–
0
Double
Buffer
0: Disable
1: Enable
0
Always write
0.
IDLE2
0: Stop
1: Operate
Not in use
TMRB0
prescaler
TB1RDE
–
–
–
I2TB1
TB1PRUN
Read/Write
R/W
R/W
–
–
R/W
After reset
0
0
0
Double
Buffer
0: Disable
1: Enable
Always write
0.
IDLE2
0: Stop
1: Operate
Not in use
UC0
0: Stop and Clear
1: Run (count up)
Bit symbol
–
TB1RUN
R/W
–
R/W
0
–
0
TMRB1
prescaler
UC1
0: Stop and Clear
1: Run (count up)
Bit symbol
TB2RDE
–
–
–
I2TB2
TB2PRUN
–
TB2RUN
Read/Write
R/W
R/W
–
–
R/W
R/W
–
R/W
After reset
0
0
0
–
0
Double
Buffer
0: Disable
1: Enable
0
Always write
0.
IDLE2
0: Stop
1: Operate
Not in use
TMRB2
prescaler
TB3RDE
–
–
–
I2TB3
TB3PRUN
Read/Write
R/W
R/W
–
–
R/W
After reset
0
0
0
Double
Buffer
0: Disable
1: Enable
Always write
0.
IDLE2
0: Stop
1: Operate
Not in use
UC2
0: Stop and Clear
1: Run (count up)
Bit symbol
Function
TB4RUN
(01C0H)
3
TB0RDE
Function
TB3RUN
(01B0H)
4
Read/Write
Function
TB2RUN
(01A0H)
5
Bit symbol
Function
TB1RUN
(0190H)
6
–
TB3RUN
R/W
–
R/W
0
–
0
TMRB3
prescaler
UC3
0: Stop and Clear
1: Run (count up)
Bit symbol
TB4RDE
–
–
–
I2TB4
TB4PRUN
–
TB4RUN
Read/Write
R/W
R/W
–
–
R/W
R/W
–
R/W
After reset
0
0
0
–
0
Function
Double
Buffer
0: Disable
1: Enable
Always write
0.
0
Not in use
IDLE2
0: Stop
1: Operate
TMRB4
prescaler
UC4
0: Stop and Clear
1: Run (count up)
Operation
I2TB0, I2TB1, I2TB2, I2TB3, I2TB4: Operation of IDLE2 mode
0
Stop and Clear
TB0PRUN, TB1PRUN, TB2PRUN, TB3PRUN, TB4PRUN: Operation of prescaler
1
Count
TB0RUN, TB1RUN, TB2RUN, TB3RUN, TB4RUN: Operation of TMRB
Note: Bits 1, 4 and 5 of TB0RUN/TB1RUN/TB2RUN/TB3RUN/TB4RUN are "1" when read.
Page 127
2007-10-15
TMP91FW60
TMRB Mode Register (Read-modify-write instructions are prohibited.) (1/2)
7
Bit symbol
TB0MOD
(0182H)
TB0CT1
Read/Write
After reset
6
5
4
3
2
1
0
TB0ET1
TB0CP0I
TB0CPM1
TB0CPM0
TB0CLE
TB0CLK1
TB0CLK0
0
0
R/W
0
W*
0
TB0FF1 inversion trigger
0: Trigger disable
1: Trigger enable
Function
Invert when
UC0 is
loaded into
TB0CP1H/L
Bit symbol
TB1MOD
(0192H)
TB1CT1
Read/Write
After reset
Invert when
UC0
matches
with
TB0RG1H/L
TB1ET1
R/W
0
Invert when
UC1 is
loaded into
TB1CP1H/L
Bit symbol
TB2MOD
(01A2H)
After reset
Invert when
UC1
matches
with
TB1RG1H/L
TB2CT1
Read/Write
TB2ET1
R/W
0
Invert when
UC2 is
loaded into
TB2CP1H/L
Bit symbol
0
TB3MOD
(01B2H)
Read/Write
After reset
Invert when
UC2
matches
with
TB2RG1H/L
TB3CT1
TB3ET1
R/W
0
Invert when
UC3 is
loaded into
TB3CP1H/L
1: Undefined
0
Capture timing
00: Disable
INT5 occurs at rising edge
01: TB0IN0↑ TB0IN1↑
INT5 occurs at rising edge
10: TB0IN0↑ TB0IN0↓
INT5 occurs at falling edge
11: TA1OUT↑ TA1OUT↓
Invert when
UC3
matches
with
TB3RG1H/L
0
Up counter
control
0: Clear
disable
1: Clear
enable
TMRB0 input clock select
00: TB0IN0 pin input
01: φT1
10: φT4
11: φT16
INT5 occurs at rising edge
TB1CP0I
TB1CPM1
TB1CPM0
0
0
Software
capture
control
0: Software
capture
1: Undefined
TB1CLE
TB1CLK1
TB1CLK0
0
0
R/W
1
Capture timing
00: Disable
INT7 occurs at rising edge
01: TB1IN0↑ TB1IN1↑
INT7 occurs at rising edge
10: TB1IN0↑ TB1IN0↓
INT7 occurs at falling edge
11: TA1OUT↑ TA1OUT↓
0
Up counter
control
0: Clear
disable
1: Clear
enable
TMRB1 input clock select
00: TB1IN0 pin input
01: φT1
10: φT4
11: φT16
INT7 occurs at rising edge
TB2CP0I
TB2CPM1
TB2CPM0
1
Software
capture
control
0: Software
capture
1: Undefined
TB2CLE
TB2CLK1
TB2CLK0
0
0
R/W
0
0
Capture timing
00: Disable
INT1 occurs at rising edge
01: TB2IN0↑ TB2IN1↑
INT1 occurs at rising edge
10: TB2IN0↑ TB2IN0↓
INT1 occurs at falling edge
11: TA1OUT↑ TA1OUT↓
0
Up counter
control
0: Clear
disable
1: Clear
enable
TMRB2 input clock select
00: TB2IN0 pin input
01: φT1
10: φT4
11: φT16
INT1 occurs at rising edge
TB3CP0I
TB3CPM1
TB3CPM0
0
0
W*
0
TB3FF1 inversion trigger
0: Trigger disable
1: Trigger enable
Function
Software
capture
control
0: Software
capture
0
W*
TB2FF1 inversion trigger
0: Trigger disable
1: Trigger enable
Function
1
W*
0
TB1FF1 inversion trigger
0: Trigger disable
1: Trigger enable
Function
R/W
1: Undefined
TB3CLK1
TB3CLK0
0
0
R/W
1
Software
capture
control
0: Software
capture
TB3CLE
Capture timing
00: Disable
INT3 occurs at rising edge
01: TB3IN0↑ TB3IN1↑
INT3 occurs at rising edge
10: TB3IN0↑ TB3IN0↓
INT3 occurs at falling edge
11: TA3OUT↑ TA3OUT↓
0
Up counter
control
0: Clear
disable
1: Clear
enable
TMRB3 input clock select
00: TB3IN0 pin input
01: φT1
10: φT4
11: φT16
INT3 occurs at rising edge
Page 128
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TMP91FW60
TMRB Mode Register (Read-modify-write instructions are prohibited.) (2/2)
7
Bit symbol
TB4MOD
(01C2H)
TB4CT1
Read/Write
After reset
6
5
4
3
2
1
0
TB4ET1
TB4CP0I
TB4CPM1
TB4CPM0
TB4CLE
TB4CLK1
TB4CLK0
0
0
R/W
0
W*
0
TB4FF1 inversion trigger
0: Trigger disable
1: Trigger enable
Function
Invert when
UC4 is
loaded into
TB4CP1H/L
Invert when
UC4
matches
with
TB4RG1H/L
R/W
1
Software
capture
control
0: Software
capture
1: Undefined
0
0
Capture timing
00: Disable
INT9 occurs at rising edge
01: TB4IN0↑ TB4IN1↑
INT9 occurs at rising edge
10: TB4IN0↑ TB4IN0↓
INT9 occurs at falling edge
11: TA5OUT↑ TA5OUT↓
0
Up counter
control
0: Clear
disable
1: Clear
enable
TMRB4 input clock select
00: TB4IN0 pin input
01: φT1
10: φT4
11: φT16
INT9 occurs at rising edge
TMRB source clock
00
External input clock (TBnIN0 pin input)
01
φT1
<TBnCLK1:0>
10
φT4
11
φT16
0
Disable to clear up counter
1
Clear by match with TBnRG1H/L
00
Disable capture
01
Capture to TBnCP0H/L at rising edge of TBnIN0
Capture to TBnCP1H/L at rising edge of TBnIN1
10
Capture to TBnCP0H/L at rising edge of TBnIN0
Capture to TBnCP1H/L at falling edge of TBnIN0
INT generate at falling edge of TBnIN0
11
Capture to TBnCP0H/L at rising edge of TAzOUT
Capture to TBnCP1H/L at falling edge of TAzOUT
INT generate at rising edge of TBnIN0
0
Capture value of up counter to TBnCP0H/L.
1
Undefined (Note 3)
Up counter clear control (UCn)
<TBnCLE>
Capture/Interrupt timing
Capture control
<TB0CPM1:0>
INT5 control
INT generate at rising edge of TBnIN0
Software capture
<TBnCP0I>
Note 1: n=0,1,2,3,4
Note 2: z=1,3,5
Note 3: As described above, whenever 0 is written to TBnMOD<TBnCP0I>, the current value in the up counter is loaded into capture register TBnCP0H/L. However, note that the current value in the up counter is also loaded into capture register
TBnCP0H/L when 1 is written to TBnMOD<TBnCP0I> while this bit is holding 0.
Page 129
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TMP91FW60
TMRB Flip-Flop Control Register (Read-modify-write instructions are prohibited.) (1/2)
7
Bit symbol
TB0FFCR
(0183H)
TB0FF1C1
Read/Write
After reset
Function
6
5
4
TB0FF1C0
TB0C1T1
TB0C0T1
W*
1
Bit symbol
1
TB1FF1C1
After reset
Function
TB1FF1C0
Bit symbol
1
TB2FF1C1
After reset
Function
TB2FF1C0
Bit symbol
1
TB3FF1C1
After reset
Function
0
0
Invert when
UC0 is
loaded into
TB0CP0H/L.
Invert when
UC0
matches
TB0RG1H/L.
Invert when
UC0
matches
TB0RG0H/L.
TB1C1T1
TB1C0T1
TB1E1T1
TB1E0T1
0
0
1
1
TB0FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
TB1FF0C1
0
0
Invert when
UC1 is
loaded into
TB1CP0H/L.
Invert when
UC1
matches
TB1RG1H/L.
Invert when
UC1
matches
TB1RG0H/L.
TB2C1T1
TB2C0T1
TB2E1T1
TB2E0T1
0
TB3FF1C0
1
1
TB1FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
TB2FF0C1
0
0
Invert when
UC2 is
loaded into
TB2CP1H/L.
Invert when
UC2 is
loaded into
TB2CP0H/L.
Invert when
UC2
matches
TB2RG1H/L.
Invert when
UC2
matches
TB2RG0H/L.
TB3C1T1
TB3C0T1
TB3E1T1
TB3E0T1
TB3FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
0
0
1
Invert when
UC3 is
loaded into
TB3CP0H/L.
Page 130
1
TB2FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
TB3FF0C1
TB3FF0C0
W*
0
0
TB3FF0 inversion trigger
0: Disable
1: Enable
Invert when
UC3 is
loaded into
TB3CP1H/L.
TB2FF0C0
W*
R/W
1
TB1FF0C0
W*
Invert when
UC1 is
loaded into
TB1CP1H/L.
0
TB0FF0C0
W*
Invert when
UC0 is
loaded into
TB0CP1H/L.
W*
1
TB0FF0C1
TB2FF0 inversion trigger
0: Disable
1: Enable
TB2FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Read/Write
TB0E0T1
R/W
Note: Always read as 11.
TB3FFCR
(01B3H)
0
W*
1
TB0E1T1
TB1FF0 inversion trigger
0: Disable
1: Enable
TB1FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Read/Write
0
R/W
Note: Always read as 11.
TB2FFCR
(01A3H)
0
W*
1
1
TB0FF0 inversion trigger
0: Disable
1: Enable
TB0FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Read/Write
2
R/W
Note: Always read as 11.
TB1FFCR
(0193H)
3
Invert when
UC3
matches
TB3RG1H/L.
Invert when
UC3
matches
TB3RG0H/L.
1
1
TB3FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
2007-10-15
TMP91FW60
TMRB Flip-Flop Control Register (Read-modify-write instructions are prohibited.) (2/2)
7
Bit symbol
TB4FFCR
(01C3H)
TB4FF1C1
Read/Write
After reset
Function
6
5
4
TB4FF1C0
TB4C1T1
TB4C0T1
W*
1
3
2
1
TB4E1T1
TB4E0T1
TB4FF0C1
R/W
1
TB4FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
0
0
Invert when
UC4 is
loaded into
TB4CP0H/L.
TB4FF0C0
W*
0
0
TB4FF0 inversion trigger
0: Disable
1: Enable
Invert when
UC4 is
loaded into
TB4CP1H/L.
0
Invert when
UC4
matches
TB4RG1H/L.
Invert when
UC4
matches
TB4RG0H/L.
1
1
TB4FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
<TBnFF0C1:0>Timer flip-flop (TBnFF0) control
00
Invert TBnFF0.
01
Set TBnFF0 to 1.
10
Clear TBnFF0 to 0.
11
Don’t care
<TBnFF0C1:0>
<TBnE0T1> TBnFF0 inversion when UCn matches TBnRG0H/L
0
Disable trigger (disable inversion).
1
Enable trigger (enable inversion).
<TBnE0T1>
<TBnE1T1> TBnFF0 inversion when UCn matches TBnRG1H/L
0
Disable trigger (disable inversion).
1
Enable trigger (enable inversion).
<TBnE1T1>
<TBnC0T1> TBnFF0 inversion when UCn is loaded into TBnCP0H/L
0
Disable trigger (disable inversion).
1
Enable trigger (enable inversion).
<TBnC0T1>
<TBnC1T1> TBnFF0 inversion when UCn is loaded into TBnCP1H/L
0
Disable trigger (disable inversion).
1
Enable trigger (enable inversion).
<TBnC1T1>
<TBnFF1C1:0>Timer flip-flop (TBnFF1) control
00
Invert TBnFF1.
01
Set TBnFF1 to 1.
10
Clear TBnFF1 to 0.
11
Don’t care
<TBnFF1C1:0>
Note: n=0,1,2,3,4
Page 131
2007-10-15
TMP91FW60
7.4 Operation in Each Mode
7.4.1
16-Bit Interval Timer Mode
Generating interrupts at fixed intervals
In this example the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the
timer register TB0RG1H/L.
7
6
5
4
3
2
1
0
TB0RUN
←
0
0
X
X
–
0
X
0
Stop TMRB0.
INTETB0
←
X
1
0
0
X
0
0
0
Enable INTTB01 and set it to interrupt level 4. Disable INTTB00.
TB0FFCR
←
1
1
0
0
0
0
1
1
Disable trigger.
TB0MOD
←
0
0
1
0
0
1
*
*
Select internal clock for input and disable the capture function.
(**=01, 10, 11)
TB0RG1
←
*
*
*
*
*
*
*
*
*
TB0RUN
←
0
0
X
X
–
1
X
1
*
*
*
*
*
*
*
Set interval time (16 bits).
Start TMRB0.
Note:X: Don't care, –: No change
7.4.2
16-Bit Event Counter Mode
If the external clock (TB0IN0 pin input) is selected as the input clock in 16-bit timer mode, the timer can be
used as an event counter. The up-counter counts up on the rising edge of TB0IN0 input. To read the value of
the counter, first perform software capture once, then read the captured value.
6
5
4
3
2
1
0
TB0RUN
←
0
0
X
X
–
0
X
0
Stop TMRB0.
P8CR
←
–
–
–
–
–
–
–
0
Set port to input mode.
P8FC
←
–
–
–
–
–
–
–
1
Set port to input mode.
INTETB0
←
X
1
0
0
X
0
0
0
Enable INTTB01 and set interrupt level 4. Disable INTTB00.
TB0FFCR
←
1
1
0
0
0
0
1
1
Disable trigger.
TB0MOD
←
0
0
1
0
0
1
0
0
Select TB0IN0 as the input clock.
TB0RG1
←
*
*
*
*
*
*
*
*
Set the number of counts (16 bits).
*
*
*
*
*
*
*
*
TB0RUN
←
0
0
X
X
–
1
X
1
Start TMRB0.
Note 1: X: Don't care, –: No change
Note 2: When the timer is used as an event counter, set the prescaler to run mode (TB0RUN<TB0PRUN> = 1).
Page 132
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TMP91FW60
7.4.3
16-Bit Programmable Pulse Generation (PPG) Output Mode
Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either activeLow or active-High.
In PPG mode a match between the value of the up-counter UC0 and either timer register TB0RG0 or
TB0RG1 inverts the output value for timer flip-flop TB0FF0. The TB0FF0 output value is output on
TB0OUT0. In this mode the following conditions must be satisfied.
(value set in TB0RG0) < (value set in TB0RG1)
Match with TB0RG0
(INTTB00 interrupt)
Match with TB0RG1
(INTTB01 interrupt)
TB0OUT0 pin
Figure 7-2
Programmable Pulse Generation (PPG) Output Waveforms
When the TB0RG0 double buffer is enabled in this mode, the value of register buffer 0 will be shifted into
TB0RG0 when the up-counter value matches TB0RG1. This feature facilitates the handling of low-duty
waves.
Match with TB0RG0
Up-counter = Q1
Up-counter = Q2
Match with TB0RG1
Shift into TB0RG1
TB0RG0
(value to be compared)
Register buffer
Q1
Q2
Q2
Q3
Write to TB0RG0
Figure 7-3 Operation of Register Buffer
Note:The values that can be set in TBxRGx range from 0001h to 0000h (equivalent to 10000h). If the maximum
value 0000h is set, the match-detect signal goes active when the up-counter overflows.
Page 133
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TMP91FW60
The following block diagram illustrates this mode.
TB0OUT0 (PPGQWVRWV)
TB0RUN<TB0RUN>
Selector
TB0IN0
ǾT1
ǾT4
ǾT16
16-bit
up counter
(UC0)
F/F
(TB0FF0)
Clear
Match
16DKVEQORCTCVQT
Selector
16DKVEQORCTCVQT
TB0RG0H/L
TB0RG0-WR
4GIKUVGTDWHHGT0
TB0RG1H/L
TB0RUN<TB0RDE>
Internal data bus
Figure 7-4
Block Diagram of 16-Bit PPG Mode
The following example shows how to set 16-bit PPG output mode:
7
6
5
4
3
2
1
0
TB0RUN
←
0
0
X
X
–
0
X
0
Disable the TB0RGH/L double buffer and stop TMRB0.
TB0RG0
←
*
*
*
*
*
*
*
*
Set the duty ratio.
*
*
*
*
*
*
*
*
(16 bits)
*
*
*
*
*
*
*
*
Set the frequency.
*
*
*
*
*
*
*
*
(16 bits)
TB0RG1
←
TB0RUN
←
1
0
X
X
–
0
X
0
Enable the TB0RG0H/L double buffer.
(The duty and frequency are changed on an INTTB01 interrupt.)
TB0FFCR
←
1
1
0
0
1
1
1
0
Set the mode to invert TB0FF0 at the match with TB0RG0H/L,
TB0RG1H/L. Clear TB0FF0 to “0”.
TB0MOD
←
0
0
1
0
0
1
*
*
(**=01, 10, 11)
P8CR
←
–
–
–
–
–
1
–
–
P8FC
←
–
–
–
–
–
1
–
–
TB0RUN
←
1
0
X
X
–
1
X
1
Select prescaler output as input clock and disable the capture function.
Set P82 to function as TB0OUT0.
Start TMRB0.
Note:X: Don’t care, –: No change
Page 134
2007-10-15
TMP91FW60
7.4.4
Capture function examples
Used capture function, they can be applicable in many ways, for example:
1. One-shot pulse output from external trigger pulse
2. Frequency measurement
3. Pulse width measurement
4. Time difference measurement
7.4.4.1
One-shot pulse output from external trigger pulse
Set the up counter UC0 in free-running mode with the internal input clock, input the external trigger
pulse from TB0IN0 pin, and load the value of up-counter into capture register TB0CP0H/L at the rise
edge of the TB0IN0 pin.
When the interrupt INT5 is generated at the rise edge of TB0IN0 input, set the TB0CP0H/L value (c)
plus a delay time (d) to TB0RG0H/L (= c + d), and set the above set value (c + d) plus a one-shot width (p)
to TB0RG1H/L (= c + d + p). And, set “11” to timer flip-flop control register TB0FFCR<TB0E1T1,
TB0E0T1>. Set to trigger enable for be inverted timer flip-flop TB0FF0 by UC0 matching with
TB0RG0H/L and with TB0RG1H/L. When interrupt INTTB01 occurs, this inversion will be disabled
after one-shot pulse is output.
The (c), (d) and (p) correspond to c, d and p Figure 7-5.
Set the counter in free-running mode.
Count clock
(Prescaler output clock)
c+d
c
TB0IN0 pin input
(External trigger pulse)
c+d+p
Load to capture register 0 (TB0CP0H/L)
INT5 occurred
Match with TB0RG0H/L
INTTB01
occurred
Inversion
enable
Match with TB0RG1H/L
Inversion enable
Timer output pin
TB0OUT0
Disables inversion caused by
loading into TB0CP1H/L.
Delay time
Pulse width
d
p
Figure 7-5 One-shot Pulse Output (with delay)
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TMP91FW60
Example: To output a 2-ms one-shot pulse with a 3-ms delay to the external trigger pulse to the TB0IN0
pin.
* Clock state
TB0MOD
←
X
X
1
0
1
0
0
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock:
fFPH
1
Set free running. Count with φT1. Load the up counter value into
TB0CP0H/L at the rising edge of TB0IN0 pin input.
TB0FFCR
←
X
X
0
0
0
0
1
0
Clear TB0FF0 to 0. Disable inversion of TB0FF0.
P8CR
←
–
–
–
–
–
1
–
–
P8FC
←
–
–
–
–
–
1
–
–
Set P82 to function as the TB0OUT0 pin.
Set P80 to TB0IN0 input mode.
INTE56
←
X
–
–
–
X
1
0
0
Enable INT5.
INTETB0
←
X
0
0
0
X
0
0
0
Disable INTTB00 and INTTB01.
TB0RUN
←
–
0
X
X
–
1
X
1
Start TMRB0.
TB0RG0
←
TB0CP0 + 3 ms/φT1
TB0RG1
←
TB0RG0 + 2 ms/φT1
TB0FFCR
←
X
X
–
–
1
1
–
–
Enable TB0FF0 inversion when the up counter value match with
TB0RG0H/L or TB0RG1H/L.
INTETB0
←
X
1
0
0
X
–
–
–
Enable INTTB01.
TB0FFCR
←
X
X
–
–
0
0
–
–
Disable inversion of TB0FF0 when the up counter value match with
value of TB0RG0H/L or TB0RG1H/L.
INTETB0
←
X
0
0
0
X
–
–
–
Disable INTTB01.
Note: X: Don't care, –: No change
When delay time is unnecessary, invert timer flip-flop TB0FF0 when up-counter value is loaded into
capture register (TB0CP0H/L), and set the TB0CP0H/L value (c) plus the one-shot pulse width (p) to
TB0RG1H/L when the interrupt INT5 occurs. The TB0FF0 inversion should be enable when the up
counter (UC10) value matches TB0RG1H/L, and disabled when generating the interrupt INTTB01.
Count clock
(Prescaler output clock)
c+p
c
TB0IN0 pin input
(External trigger pulse)
Load into capture register 0 (TB0CP0H/L).
INT5 occurred.
Match with TB0RG1H/L
INTTB01
occurred.
Load the up counter value in
capture register 1 (TB0CP1
Inversion enable
Timer output
TB0OUT0
Pulse width
Enables inversion caused by loading
into TB0CP0H/L.
Figure 7-6
p
Disable inversion caused by loading
into TB0CP1H/L.
One-shot Pulse Output (without delay)
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7.4.4.2
Frequency measurement
The frequency of the external clock can be measured in this mode. The clock is input through the
TB0IN0 pin, and its frequency is measured by the 8-bit timers TMRA01 and the 16-bit timer/event
counter (TMRB0). (TMRA01 is used to setting of measurement time by inversion TA1FF.)
The TB0IN0 pin input should be for the input clock of TMRB0. Set to TB0MOD <TB0CPM1:0> =
“11”. The value of the up counter (UC10) is loaded into the capture register TB0CP0H/L at the rise edge
of the timer flip-flop TA1FF of 8-bit timers (TMRA01), and into TB0CP1H/L at its fall edge.
The frequency is calculated by difference between the loaded values in TB0CP0H/L and TB0CP1H/L
when the interrupt (INTTA0 or INTTA1) is generates by either 8-bit timer.
Count clock
(TB0IN0 pin input)
C1
C2
TA1FF
Load to TB0CP0H/L
Load to TB0CP1H/L
C1
C1
C2
C2
INTTA0/INTTA1
Figure 7-7 Frequency Measurement
For example, if the value for the level 1 width of TA1FF of the 8-bit timer is set to 0.5 s and the difference between the values in TB0CP0H/L and TB0CP1H/L is 100, the frequency is 100 ÷ 0.5 s = 200 Hz.
Note: The frequency in this example is calculated with 50 duty.
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7.4.4.3
Pulse width measurement
This mode allows to measure the high-level width of an external pulse. While keeping the 16-bit timer/
event counter counting (Free running) with the internal clock input, external pulse is input through the
TB0IN0 pin. Then the capture function is used to load the UC0 values into TB0CP0H/L and TB0CP1H/L
at the rising edge and falling edge of the external trigger pulse respectively. The interrupt INT5 occurs at
the falling edge of TB0IN0.
The pulse width is obtained from the difference between the values of TB0CP0H/L and TB0CP1H/L
and the internal clock cycle.
For example, if the internal clock is 0.8 μs and the difference between TB0CP0H/L and TB0CP1H/L is
100, the pulse width will be 100 × 0.8 μs = 80 μs.
Additionally, the pulse width which is over the UC0 maximum count time specified by the clock source,
can be measured by changing software.
Count clock
(Prescaler output clock)
C1
C2
TB0IN0 pin input
(External pulse)
Load to TB0CP0H/L
C1
C1
Load to TB0CP1H/L
C2
C2
INT5
Figure 7-8 Pulse Width Measurement
Note: Only in this pulse width measuring mode (TB0MOD<TB0CPM1:0> = 10), external interrupt INT5 occurs
at the falling edge of TB0IN0 pin input. In other modes, it occurs at the rising edge.
The width of low-level can be measured from the difference between the first C2 and the second C1 at
the second INT5 interrupt.
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7.4.4.4
Time Difference Measurement
This mode is used to measure the difference in time between the rising edges of external pulses input
through TB0IN0 and TB0IN1.
Keep the 16-bit timer/event counter (TMRB0) counting (Free running) with the internal clock, and load
the UC0 value into TB0CP0H/L at the rising edge of the input pulse to TB0IN0. Then the interrupt INT5
is generated.
Similarly, the UC0 value is loaded into TB0CP1H/L at the rising edge of the input pulse to TB0IN1,
generating the interrupt INT6.
The time difference between these pulses can be obtained by multiplying the value subtracted
TB0CP0H/L from TB0CP1H/L and the internal clock cycle together at which loading the up counter
value into TB0CP0H/L and TB0CP1H/L has been done.
Count clock
(Prescaler output clock)
C1
C2
TB0IN0 pin input
TB0IN1 pin input
Load to TB0CP0H/L
Load to TB0CP1H/L
INT5
INT6
Time difference
Figure 7-9 Time Difference Measurement
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TMP91FW60
8. Serial Channels (SIO)
TMP91FW60 includes 3 serial I/O channels. For both channels either UART mode (Asynchronous transmission)
or I/O interface mode (Synchronous transmission) can be selected.
1. I/O interface mode
• Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending
I/O.
2. UART mode
• Mode 1: 7-bit data
• Mode 1: 8-bit data
• Mode 1: 9-bit data
In mode 1 and mode 2, a parity bit can be added. Mode 3 has a wakeup function for the master controller to start
slave controllers via a serial link (A multi-controller system).
Figure 8-2 are block diagrams for each channel.
SIO is compounded mainly prescaler, serial clock generation circuit, receiving buffer and control circuit, transmission buffer and control circuit.
Both channels operate in the same function except for the following points; hence only the operation of channel 0
is explained below.
Table 8-1 Differences in Serial Channel Specifications
Pin name
SIO0
SIO1
SIO2
TXD0 (P90)
RXD0 (P91)
CTS0/SCLK0 (P92)
TXD1 (P93)
RXD1 (P94)
CTS1/SCLK1 (P95)
TXD2 (P41)
RXD2 (P42)
CTS2/SCLK2 (P43)
Mode 0 (I/O interface mode
٨
Bit 0
1
2
3
4
5
6
7
Transfer direction
Mode 1 (7-bit UART mode)
٨
No parity
Start
Bit 0
1
2
3
4
5
6
Stop
Parity
Start
Bit 0
1
2
3
4
5
6
Parity Stop
Mode 2 (8-bit UART mode)
٨
No parity
Start
Bit 0
1
2
3
4
5
6
7
Stop
Parity
Start
Bit 0
1
2
3
4
5
6
7
Parity Stop
Mode 3 (9-bit UART mode
٨
Wakeup function
Start
Bit 0
1
2
3
4
5
6
7
8
Stop
Start
Bit 0
1
2
3
4
5
6
7
Bit 8
Stop
When bit8 = 1, address (Select code) is denoted.
When bit8 = 0, data is denoted.
Figure 8-1 Data Formats
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8.1 Block Diagrams
Prescaler
4 8 16 32 64
2
ǾT0
ǾT2
ǾT8
0QVGP
5+15+15+1
ǾT32
Serial clock generation circuit
BRnCR
<BRnCK1:0>
TA0TRG
(from TMRA0)
BRnCR
<BRnADDE>
SCnMOD0
<SC1:0>
UART
mode
Selector
Selector
BRnADD
<BRnK3:0>
Prescaler
ǾT0
ǾT2
ǾT8
ǾT32
Selector
BRnCR
<BRnS3:0>
SIOCLK
SCnMOD0
<SM1:0>
Baud date generator
Selector
fSYS
¸2
SCLKn
I/O
interface mode
SC0CR
<IOC>
I/O interface mode
INT request
INTRXn
SCLKn
INTTXn
Receive counter
(UART only ¸16)
SCnMOD0
<WU>
Serial channel
interrupt
control
TXDCLK
RXDCLK
SCnMOD0
<RXE>
Transmission
Receive control
RB8
SCnMOD0
<CTSE>
Parity control
Receive buffer 2 (SCnBUF)
Error flag
CTSn
control
SCnCR
<PE> <EVEN>
Receive buffer 1 (Shift register)
RXDn
Transmission
counter
(UART only ¸16)
TB8
Transmission buffer (SCnBUF)
TXDn
SCnCR
<OERR><PERR><FERR>
Internal data bus
Figure 8-2 Block Diagram of the Serial Channel 0/1/2
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8.2 Operation of Each Circuit
8.2.1
Prescaler
A 6-bit prescaler generates an operation clock for SIO0. The prescaler is acteve only when a baud rate generator is specified as a serial transfer clock. As an input clock of the prescaler, be sure to set SYSCR0<PRCK1>
to “0” and then specify fFPH. This clock is used for φT0 with being divided by 4.
Table 8-2 shows prescaler clock resolution into the baud rate generator.
Table 8-2
Prescaler Clock Resolution to Baud Rate Generator
Select System Clock
<SYSCK>
Gear Value
<GEAR2:0>
1 (fs)
Select Prescaler Clock
<PRCK1>
φT0
φT2
φT8
φT32
XXX
22/fs
24/fs
26/fs
28/fs
000 (fc)
22/fc
24/fc
26/fc
28/fc
23/fc
25/fc
27/fc
29/fc
24/fc
26/fc
28/fc
210/fc
011 (fc/8)
25/fc
27/fc
29/fc
211/fc
100 (fc/16)
26/fc
28/fc
210/fc
212/fc
001 (fc/2)
0 (fc)
Prescaler Output Clock Resolution
010 (fc/4)
0 (1/1)
fFPH
The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, and φT32 among the prescaler outputs.
8.2.2
Baud rate generator
The baud rate generator is a circuit which generates transmission and receiving clocks which determine the
transmission rate of the serial channels.
The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which
is shared by the timers. One of these input clocks is selected using the BR0CR<BR0CK1:0> field in the baud
rate generator control register.
The baud rate generator includes a frequency divider, which divides the frequency by 1, N + (16 – K)/16 or
16 values, determining the transmission rate. The transmission rate is determined by the settings of
BR0CR<BR0ADDE><BR0S3:0> and BR0ADD<BR0K3:0>.
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8.2.2.1
In UART mode
(1)
When BR0CR<BR0ADDE> = 0
The settings BR0ADD<BR0K3:0> are ignored. The baud rate generator divides the selected
prescaler clock by N, which is set in BR0CK<BR0S3:0>. (N = 1, 2, 3 ... 16)
(2)
When BR0CR<BR0ADDE> = 1
The N + (16 – K)/16 division function is enabled. The baud rate generator divides the selected
prescaler clock by N + (16 – K)/16 using the value of N set in BR0CR<BR0S3:0> (N = 2, 3 ... 15)
and the value of K set in BR0ADD<BR0K3:0> (K = 1, 2, 3 ... 15)
Note: If N = 1 and N = 16, the N + (16 – K)/16 division function is disabled. Set BR0CR<BR0ADDE> to
“0”.
8.2.2.2
In I/O interface mode
The N + (16 – K)/16 division function is not available in I/O interface mode. Set BR0CR<BR0ADDE>
to “0” before dividing by N.
The method for calculating the transmission rate when the baud rate generator is used is explained
below.
(1)
In UART mode
Input clock of baud rate generator
Baud rate = ---------------------------------------------------------------------------------------------------- ÷ 16
Frequency divider for baud rate generator
(2)
In I/O interface mode
Input clock of baud rate generator
Baud rate = ---------------------------------------------------------------------------------------------------- ÷ 2
Frequency divider for baud rate generator
8.2.2.3
Integer divider (N divider)
For example, when the source clock frequency (fc) =19.6608 MHz, the input clock frequency = φT2 (fc/
16), the frequency divider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0ADDE> = 0, the baud rate in
UART mode is as follows:
*Clock state
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock:
fFPH
fc ⁄ 16
Baudrate = -------------- ÷ 16
8
= 19.6608 × 106 ÷ 16 ÷ 8 ÷ 16 = 9600 (bps)
Note: The + (16 - K)/16 division function is disabled and setting BR0ADD<BR0K3:0> is invalid.
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8.2.2.4
N + (16 - K)/16 divider (UART mode only)
Accordingly, when the source clock frequency (fc) = 15.9744 MHz, the input clock frequency = φT2,
the frequency divider N (BR0CR<BR0S3:0>) = 6, K (BR0ADD<BR0K3:0>) = 8, and
BR0CR<BR0ADDE> = 1, the baud rate in UART mode is as follows:
*Clock state
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock:
fFPH
⎛
⎞
fc/16
Baudrate= ⎜ ----------------------------- ÷ 16⎟
⎜
⎟
( 16 – 8 )
⎝ 6 + ------------------⎠
16
6
8
= 15.9744 × 10 ÷ 16 ÷ ⎛ 6 + ------⎞ ÷ 16 = 9600(bps)
⎝
16⎠
Table 8-3 show examples of UART mode transfer rates.
Additionally, the external clock input is available in the serial clock.
The method for calculating the baud rate is explained below:
• In UART mode
Baud rate = External clock input frequency ÷ 16
It is necessary to satisfy (External clock input cycle) ≥ 4/fSYS
• In I/O interface mode
Baud rate = External clock input frequency
It is necessary to satisfy (External clock input cycle) ≥ 16/fSYS
Table 8-3 UART Baud Rate Selection
(When baud rate generator is used and BR0CR<BR0ADDE>=0, SYSCR0<PRCK>=0)
Input Clock
fc [MHz]
Frequency Divider N
Unit (kbps)
φT0
(fc/4)
φT2
(fc/16)
φT8
(fc/64)
φT32
(fc/256)
7.3728
1
115.200
28.800
7.200
1.800
↑
3
38.400
9.600
2.400
0.600
↑
6
19.200
4.800
1.200
0.300
↑
A
11.520
2.880
0.720
0.180
↑
C
9.600
2.400
0.600
0.150
↑
F
7.680
1.920
0.480
0.120
9.8304
1
153.600
38.400
9.600
2.400
↑
2
76.800
19.200
4.800
1.200
↑
4
38.400
9.600
2.400
0.600
↑
5
30.720
7.680
1.920
0.480
↑
8
19.200
4.800
1.200
0.300
↑
10
9.600
2.400
0.600
0.150
Note: Transmission rates in I/O interface mode are eight times faster than the values given above.
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Timer out clock (TA0TRG) can be used for source clock of UART mode only.
Calculation method the frequency of TA0TRG
Frequency of TA0TRG = Baud rate × 16
Note: In case of I/O interface mode, prohibit to use TA0TRG for source clock.
8.2.3
Serial clock generation circuit
This circuit generates the basic clock for transmission and receiving data.
8.2.3.1
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC> = “0”, the basic clock is generated by dividing the
output of the baud rate generator by 2, as described previously.
In SCLK input mode with the setting SC0CR<IOC> = “1”, the rising edge or falling edge will be
detected according to the setting of the SC0CR<SCLKS> register to generate the basic clock.
8.2.3.2
In UART mode
The SC0MOD0<SC1:0> setting determines whether the baud rate generator clock, the internal system
clock fSYS, the match detect signal from timer TMRA0 or the external clock (SCLK0) is used to generate
the basic clock SIOCLK.
8.2.4
Receiving counter
The receiving counter is a 4-bit binary counter used in UART mode which counts up the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each data bit is sampled three times – on the
7th, 8th and 9th clock cycles.
The value of the data bit is determined from these three samples using the majority rule.
For example, if the data bit is sampled respectively as “1”, “0” and “1” on 7th, 8th and 9th clock cycles, the
received data bit is taken to be “1”. A data bit sampled as “0”, “0” and “1” is taken to be “0”.
8.2.5
Receiving control
8.2.5.1
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC> = “0”, the RXD0 signal is sampled on the rising
or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR<SCLKS>
setting.
In SCLK input mode with the setting SC0CR<IOC> = “1”, the RXD0 signal is sampled on the rising or
falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting.
8.2.5.2
In UART mode
The receiving control block has a circuit which detects a start bit using the majority rule. Received bits
are sampled three times; when two or more out of three samples are “0”, the bit is recognized as the start
bit and the receiving operation commences.
The values of the data bits that are received are also determined using the majority rule.
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8.2.6
Receiving buffers
To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure.
Received data is stored one bit at a time in receiving buffer 1 (which is a shift register).
When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transmitted to receiving
buffer 2 (SC0BUF); this causes an INTRX0 interrupt to be generated. The CPU only reads receiving buffer 2
(SC0BUF). Even before the CPU reads receiving buffer 2 (SC0BUF), the received data can be stored in receiving buffer 1. However, unless receiving buffer 2 (SC0BUF) is read before all bits of the next data are received
by receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of receiving buffer 1 will
be lost, although the contents of receiving buffer 2 and SC0CR<RB8> will be preserved.
SC0CR<RB8> is used to store either the parity bit – added in 8-bit UART mode – or the most significant bit
(MSB) – in 9-bit UART mode.
In 9-bit UART mode the wakeup function for the slave controller is enabled by setting SC0MOD0<WU> to
“1”; in this mode INTRX0 interrupts occur only when the value of SC0CR<RB8> is “1”.
Note 1: The double buffer structure does not support SC0CR<RV08>.
Note 2: If the CPU reads receive buffer 2 while data is being transferred from receive buffer 1 to receive buffer 2,
the data may not be read properly. To avoid this situation, a read of receive buffer 2 should be triggered by
a receive interrupt.
8.2.7
Transmission counter
The transmission counter is a 4-bit binary counter which is used in UART mode and which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is generated every 16 SIOCLK clock pulses.
SIOCLK
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
TXDCLK
Figure 8-3 Generation of the Transmission Clock
8.2.8
Transmission controller
8.2.8.1
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC> = “0”, the data in the transmission buffer is output
one bit at a time to the TXD0 pin on the rising or falling edge of the shift clock which is output on the
SCLK0 pin, according to the SC0CR<SCLKS> setting.
In SCLK input mode with the setting SC0CR<IOC> = “1”, the data in the transmission buffer is output
one bit at a time on the TXD0 pin on the rising or falling edge of the SCLK0 input, according to the
SC0CR<SCLKS> setting.
8.2.8.2
In UART mode
When transmission data sent from the CPU is written to the transmission buffer, transmission starts on
the rising edge of the next TXDCLK.
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8.2.8.3
Handshake function
Use of CTS0 pin allows data can be sent in units of one frame; thus, overrun errors can be avoided. The
handshake function is enabled or disabled by the SC0MOD0<CTSE> setting.
When the CTS0 pin goes high on completion of the current data send, data transmission is halted until
the CTS0 pin goes low again. However, the INTTX0 interrupt is generated, it requests the next data send
to the CPU. The next data is written in the transmission buffer and data transmission is halted.
Though there is no RTS pin, a handshake function can be easily configured by setting any port assigned
to be the RTS function. The RTS should be output “high” to request send data halt after data receive is
completed by software in the RXD interrupt routine.
6/2(9
6/2(9
RXD
TXD
RTS (Any port)
CTS0
Sender
Receiver
Figure 8-4 Handshake Function
Timing to write to
the transmission buffer
Transmission is
suspended during
this period
b
CTS0
a
13 14 15 16 1
2
3
13 14 15 16 1
2
3
SIOCLK
TXDCLK
Start bit
TXD
Bit 0
Note 1: If the CTS0 signal goes high during transmission, no more data will be sent after completion of the current transmission.
Note 2: Transmission starts on the first falling edge of the TXDCLK clock after the CTS0 signal has fallen.
Figure 8-5 CTS0 (Clear to send) Timing
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8.2.9
Transmission buffer
The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU from the
least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty
and generates an INTTX0 interrupt.
8.2.10 Parity control circuit
When SC0CR<PE> in the serial channel control register is set to “1”, it is possible to transmit and receive
data with parity. However, parity can be added only in 7-bit UART mode or 8-bit UART mode. The
SC0CR<EVEN> field in the serial channel control register allows either even or odd parity to be selected.
In the case of transmission, parity is automatically generated when data is written to the transmission buffer
SC0BUF. The data is transmitted after the parity bit has been stored in SC0BUF<TB7> in 7-bit UART mode or
in SC0MOD0<TB8> in 8-bit UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission data is written to the transmission buffer.
In the case of receiving, data is shifted into receiving buffer 1, and the parity is added after the data has been
transmitted to receiving buffer 2 (SC0BUF), and then compared with SC0BUF<RB7> in 7-bit UART mode or
with SC0CR<RB8> in 8-bit UART mode. If they are not equal, a parity error is generated and the
SC0CR<PERR> flag is set.
8.2.11 Error flags
Three error flags are provided to increase the reliability of data reception.
8.2.11.1 Overrun error <OERR>
If all the bits of the next data item have been received in receiving buffer 1 while valid data still remains
stored in receiving buffer 2 (SC0BUF), an overrun error is generated.
The below is a recommended flow when the overrun error is generated.
(INTRX interrupt routine)
1. Read receiving buffer
2. Read error flag
3. if <OERR> = 1
then
a. Set to disable receiving (Write “0” to SC0MOD0<RXE>)
b. Wait to terminate current frame
c. Read receiving buffer
d. Read error flag
e. Set to enable receiving (Write “1” to SC0MOD0<RXE>)
f. Request to transmit again
4. Other
Note: Overrun errors are generated only with regard to receive buffer 2 (SC0BUF). Thus, if SC0CR<RB8> is
not read, no overrun error will occur.
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TMP91FW60
8.2.11.2 Parity error <PERR>
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity
bit received via the RXD pin. If they are not equal, a parity error is generated.
Note: The parity error flag is cleared every time it is read. However, if a parity error is detected twice in succession and the parity error flag is read between the two parity errors, it may seem as if the flag had not
been cleared. To avoid this situation, a read of the parity error flag should be triggered by a receive
interrupt.
8.2.11.3 Framing error <FERR>
The stop bit for the received data is sampled three times around the center. If the majority of the samples
are “0”, a framing error is generated.
8.2.12 Timing generation
8.2.12.1 In UART mode
Table 8-4 Receiving
Mode
9 Bits
8 Bits + Parity
8 Bits, 7 Bits + Parity, 7 Bits
Interrupt timing
Center of last bit
(Bit8)
Center of last bit
(Parity bit)
Center of stop bit
Framing error timing
Center of stop bit
Center of stop bit
Center of stop bit
Center of last bit
(Parity bit)
Center of stop bit
Center of last bit
(Parity bit)
Center of stop bit
Parity error timing
–
Center of last bit
(Bit8)
Overrun error timing
Note 1: In 9 Bits and 8 Bits + Parity mode, interrupts coincide with the ninth bit pulse. Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error.
Note 2: The higher the transfer rate, the later than the middle receive interrupts and errors occur.
Table 8-5
Transmitting
Mode
Interrupt timing
9 Bits
8 Bits + Parity
8 Bits, 7 Bits + Parity, 7 Bits
Just before stop bit is transmitted
Just before stop bit is
transmitted
Just before stop bit is transmitted
8.2.12.2 I/O interface
Immediately after the last bit.
(See Figure 8-8)
Transmission
interrupt
timing
SCLK output mode
Receiving
interrupt
timing
SCLK output mode
Timing used to transmit received data to receive buffer 2 (SC0BUF)
(e.g., immediately after last SCLK). (See Figure 8-10)
SCLK input mode
Timing used to transmit received data to receive buffer 2 (SC0BUF)
(e.g., immediately after last SCLK). (See Figure 8-11)
SCLK input mode
Immediately after rise of last SCLK signal rising mode, or immediately
after fall in falling mode. (See Figure 8-9)
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TMP91FW60
8.3 SFR
Serial Control Register (Read-modify-write instructions are prohibited.)
SC0CR
(0201H)
7
6
Bit symbol
RB8
EVEN
Read/Write
R
After reset
Undefined
Function
Received
data bit8
4
PE
OERR
R/W
0
Parity addition
0: Disable
1: Enable
Parity
0: Odd
1: Even
3
2
1
PERR
FERR
SCLKS
R (Cleared to "0" when read)
0
SC1CR
(0209H)
SC2CR
(0211H)
5
0
0
Overrun
error flag
0: Undetect
error
1: Detect
error
Parity error
flag
0: Undetect
error
1: Detect
error
0
IOC
R/W
0
Framing
error flag
0: Undetect
error
1: Detect
error
0
0
Edge selection for
SCLK pin (I/
O mode)
0: SCLK↑
1: SCLK↓
I/O interface
input clock
selection
0: Baud rate
generator
1: SCLK
pin input
Note1: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.
Note2: A baud rate generator SCnCR<IOC> = "0" is unavailable as an input clock for an I/O interface if a prescaler clock
is set to fc/16 whenSYSCR0<PRCK1> is "1".
Note3: n =0, 1, 2.
Serial Mode Control Register 0
Bit symbol
SC0MOD0
(0202H)
6
5
4
3
2
1
0
CTSE
RXE
WU
SM1
SM0
SC1
SC0
0
0
0
0
0
0
0
0
Read/Write
After reset
SC1MOD0
(020AH)
SC2MOD0
(0212H)
7
TB8
Function
R/W
Transmission data
bit8
Handshake
function
0: Disable
1: Enable
Receive
function
0: Disable
1: Enable
Wakeup
function
0: Disable
1: Enable
Serial transmission mode
00: I/O interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial transmission clock
(UART)
00: Timer TA0TRG
01: Baud rate generator
10: Internal clock fSYS
11: External clock
(SCLK input)
Note1: SCLKpin and CTS pin
SCLK pin
CTS pin
SIO0
SCLK0
CTS0
SIO1
SCLK1
CTS1
SIO2
SCLK2
CTS2
Note2: A baud rate generator SCnMOD0<SC1:0> = "01" is unavailable as a serial transfer clock if a prescaler clock
is set to fc/16 whenSYSCR0<PRCK1> is "1".
Note3: n =0, 1, 2.
Serial Mode Control Register 1
SC0MOD1
(0205H)
7
6
5
4
3
2
1
0
Bit symbol
I2S0
FDPX0
–
–
–
–
–
–
Read/Write
R/W
R/W
–
–
–
–
–
–
After reset
0
0
–
–
–
–
–
–
Bit symbol
I2S1
FDPX1
–
–
–
–
–
–
Read/Write
R/W
R/W
–
–
–
–
–
–
SC1MOD1
(020DH)
After reset
0
0
–
–
–
–
–
–
Bit symbol
I2S2
FDPX2
–
–
–
–
–
–
SC2MOD1
(0215H)
Read/Write
R/W
R/W
–
–
–
–
–
–
After reset
0
0
–
–
–
–
–
–
IDLE2
0: Stop
1: Run
Duplex
0: Half
1: Full
Function
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TMP91FW60
Baud Rate Generator Control
Bit symbol
BR0CR
(0203H)
BR1CR
(020BH)
BR2CR
(0213H)
BR2ADD
(0214H)
5
4
–
BR0ADDE
BR0CK1
BR0CK0
3
2
1
0
BR0S3
BR0S2
BR0S1
BR0S0
R/W
After reset
0
0
0
0
0
0
0
0
Bit symbol
–
BR1ADDE
BR1CK1
BR1CK0
BR1S3
BR1S2
BR1S1
BR1S0
After reset
0
0
0
0
0
0
0
0
Bit symbol
–
BR2ADDE
BR2CK1
BR2CK0
BR2S3
BR2S2
BR2S1
BR2S0
0
0
0
0
Read/Write
R/W
Read/Write
Function
BR1ADD
(020CH)
6
Read/Write
R/W
After reset
BR0ADD
(0204H)
7
0
0
+ (16 - K)/16
division
0: Disable
1: Enable
Always write
“0”.
0
0
Input clock selection for
baud rate generator
00: φT0
01: φT2
10: φT8
11: φT32
Setting of the divided frequency “N”
7
6
5
4
3
2
1
0
Bit symbol
–
–
–
–
BR0K3
BR0K2
BR0K1
BR0K0
Read/Write
–
–
–
–
After reset
–
–
–
–
0
0
0
0
BR1K3
BR1K2
BR1K1
BR1K0
Bit symbol
–
–
–
–
Read/Write
–
–
–
–
R/W
R/W
After reset
–
–
–
–
0
0
0
0
Bit symbol
–
–
–
–
BR2K3
BR2K2
BR2K1
BR2K0
Read/Write
–
–
–
–
After reset
–
–
–
–
0
0
0
0
R/W
Sets frequency divisor “K”
(Divided by N + (16 - K)/16)
Function
Baud rate generator frequency divisor setting
BRnCR<BRnADDE> = 1
BRnCR
<BRnS3:0>
BRnADD
0010(N=2)
0000(N=16)
or
0001(N=1)
to
1111(N=15)
Disable
Disable
Disable
Divided by
N + (16 - K)/
16
<BRnK3:0>
0000
0001 (K = 1)
to
1111 (K = 15)
BRnCR<BRnADDE> = 0
0001(N=1)UART only
to
1111(N=15)
0000(N=16)
Divided by N
Note: Availability of +(16 - K)/16 division function
UART mode
I/O mode
2 to 15
O
x
1, 16
x
x
N
The baud rate generator can be set “1” in UART mode and disable + (16 K)/16 division function. Don’t use in I/O interface mode.
Note: Set BR1CR<BR1ADDE> to 1 after setting K (K = 1 to 15) to BR1ADD<BR1K3:0> when N+ (16 - K)/16
division function is used.
Note: n = 0,1,2
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TMP91FW60
Serial Transmission/receiving Buffer Registers (Read-modify-write instructions are prohibited.)
SC0BUF
(0200H)
SC1BUF
(0208H)
SC2BUF
(0210H)
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
(Transmission)
(Receiving)
8.4 Operation in Each Mode
8.4.1
Mode 0 (I/O interface mode)
This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data
from an external shift register.
This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to
input external synchronous clock SCLK.
Output extension
6/2(9
TXD
Input extension
Shift register
SI
SCLK
SCK
Port
RCK
6/2(9
A
B
C
D
E
F
G
H
RXD
SCLK
Port
Shift register
QH
CLOCK
S/L
A
B
C
D
E
F
G
H
TC74HC165 or equivalent
TC74HC595 or equivalent
Figure 8-6 SCLK Output Mode Connection Example
Output extension
6/2(9
TXD
Input extension
Shift register
SI
SCLK
SCK
Port
RCK
6/2(9
A
B
C
D
E
F
G
H
RXD
SCLK
Port
Shift register
QH
CLOCK
S/L
A
B
C
D
E
F
G
H
TC74HC165 or equivalent
TC74HC595 or equivalent
External clock
External clock
Figure 8-7 SCLK Input Mode Connection Example
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TMP91FW60
8.4.1.1
Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins
respectively each time the CPU writes the data to the transmission buffer. When all data is output,
INTES0<ITX0C> will be set to generate the INTTX0 interrupt.
Timing to write
transmission data
SCLK0 output
(<SCLKS> = 0: Rising edge mode)
(Internal clock
timing)
SCLK0 output
(<SCLKS> = 1: Falling edge mode)
Bit 0
TXD0
Bit 1
Bit 6
Bit 7
ITX0C
(INTTX0 interrupt request)
Figure 8-8 Transmitting Operation in I/O Interface Mode (SCLK output mode)
In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0 input becomes active after
the data has been written to the transmission buffer by the CPU.
When all data is output, INTES0<ITX0C> will be set to generate INTTX0 interrupt.
SCLK0 input
(<SCLKS> = 0: Rising edge mode)
SCLK0 input
(<SCLKS> = 1: Falling edge mode)
TXD0
Bit 0
Bit 1
Bit 5
Bit 6
Bit 7
ITX0C (INTTX0
interrupt request)
Figure 8-9 Transmitting Operation in I/O Interface Mode (SCLK input mode)
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8.4.1.2
Receiving
In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to
receiving buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading the
received data. When 8-bit data are received, the data will be transmitted to receiving buffer 2 (SC0BUF
according to the timing shown below) and INTES0<IRX0C> will be set to generate INTRX0 interrupt.
The outputting for the first SCLK0 starts by setting SC0MOD0<RXE> to “1”.
IRX0C
(INTRX0 interrupt request)
SCLK0 output
(<SCLKS> = 0: Rising edge mode)
SCLK0 output
(<SCLKS> = 1: Falling edge mode)
RXD0
Bit 0
Bit 1
Bit 6
Bit 7
Figure 8-10 Receiving Operation in I/O Interface Mode (SCLK output mode)
In SCLK input mode, the data is shifted to receiving buffer 1 when the SCLK input becomes active after
the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit data is
received, the data will be shifted to receiving buffer 2 (SC0BUF according to the timing shown below)
and INTES0<IRX0C> will be set again to be generate INTRX0 interrupt.
SCLK0 input
(<SCLKS> = 0: Rising edge mode)
SCLK0 input
(<SCLKS> = 1: Falling edge mode)
Bit 0
RXD1
Bit 1
Bit 5
Bit 6
Bit 7
IRX0C
(INTRX0 interrupt request)
Figure 8-11 Receiving Operation in I/O Interface Mode (SCLK input mode)
Note: The system must be put in the receive enable state (SC0MOD0<RXE> = 1) before data can be
received.
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8.4.1.3
Transmission and receiving (Full duplex mode)
When the full duplex mode is used, set the level of receive interrupt to “0” and set enable the interrupt
level (1 to 6) to the transmission interrupt. In the transmission interrupt program, the receiving operation
should be done like the above example before setting the next transmission data.
Example: Channel 0, SCLK output
Baud rate = 9600 bps
fc = 14.7456 MHz
*Clock state
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock:
fFPH
port setting
7
6
5
4
3
2
1
0
INTES0
X
0
0
1
0
0
0
0
Set the INTTX0 level to 1. Set the INTRX0 level to 0.
SC0MOD0
–
–
–
–
0
0
–
–
Select I/O interface mode.
SC0MOD1
–
1
X
X
X
X
X
X
Select full duplex mode.
SC0CR
–
–
–
–
–
–
0
0
SCLK0 output mode, transmit on falling edge mode,
receive on rising edge mode.
BR0CR
0
0
1
1
0
0
1
1
Baud rate = 9600 bps
SC0MOD0
–
–
1
–
–
–
–
–
Enable receiving
SC0BUF
*
*
*
*
*
*
*
*
Set the transmit data and start.
7
6
5
4
3
2
1
0
*
*
*
*
*
*
*
*
Acc SC0BUF
SC0BUF
Read the receiving buffer.
Set the next transmission data.
Note: X: Don't care, –: No change, *: Data
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8.4.2
Mode 1 (7-bit UART mode)
7-bit UART mode is selected by setting serial channel mode register SC0MOD0<SM1:0> to “01”.
In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial
channel control register SC0CR<PE> bit; whether even parity or odd parity will be used is determined by the
SC0CR<EVEN> setting when SC0CR<PE> is set to “1” (Enabled).
Example: When transmission data of the following format, the control registers should be set as described
below. This explanation applies to channel 0.
Start
Bit 0
1
2
3
4
5
6
Even
parity
Stop
Transmission direction (Transmission rate: 2400 bps at fc = 12.288 MHz)
Figure 8-12 7-bit UART mode
*Clock state
7
6
5
4
3
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock:
System clock
2
1
0
SC0MOD0
←
–
–
–
–
0
1
0
1
Select 7-bit UART mode.
SC0CR
←
–
1
1
–
–
–
–
–
Add even parity.
BR0CR
←
0
0
1
0
0
1
0
1
Set the transmission rate to 2400 bps.
INTES0
←
X
1
0
0
–
–
–
–
Enable the INTTX0 interrupt and set it to interrupt level 4.
SC0BUF
←
*
*
*
*
*
*
*
*
Set data for transmission.
Note:X: Don't care, –: No change, *: Data
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8.4.3
Mode 2 (8-bit UART mode)
8-bit UART mode is selected by setting SC0MOD0<SM1:0> to “10”. In this mode, a parity bit can be added
(Use of a parity bit is enabled or disabled by the setting of SC0CR<PE>); whether even parity or odd parity
will be used is determined by the SC0CR<EVEN> setting when SC0CR<PE> is set to “1” (Enabled).
Example: When receiving data of the following format, the control registers should be set as described
below.
Start
Bit 0
1
2
3
4
5
6
7
Odd
parity
Stop
Transmission direction (Transmission rate: 9600 bps at fc = 12.288 MHz)
Figure 8-13 8-bit UART mode
*Clock state
7
6
5
4
3
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock:
System clock
2
1
0
SC0MOD0
←
–
–
1
–
1
0
0
1
Enable receiving in 8-bit UART mode.
SC0CR
←
–
0
1
–
–
–
–
–
Add odd parity.
BR0CR
←
0
0
0
1
0
1
0
1
Set the transmission rate to 9600 bps.
INTES0
←
–
–
–
–
X
1
0
0
Enable the INTTX0 interrupt and set it to interrupt level 4.
Note:X: Don't care, –: No change
Acc ← SC0CR AND 00011100
if Acc ≠ 0 then ERROR
Acc ← SC0BUF
Check for errors.
Read the received data.
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8.4.4
Mode 3 (9-bit UART mode)
9-bit UART mode is selected by setting SC0MOD0<SM1:0> to “11”. In this mode parity bit cannot be
added.
In the case of transmission, the MSB (9th bit) is written to SC0MOD0<TB8>. In the case of receiving, it is
stored in SC0CR<RB8>. When the buffer is written and read, the MSB is read or written first, before the rest of
the SC0BUF data.
8.4.4.1
Wakeup function
In 9-bit UART mode, the wakeup function for slave controllers is enabled by setting SC0MOD0<WU>
to “1”. The interrupt INTRX0 occurs only when <RB8> = “1”.
TXD
RXD
/CUVGT
TXD
RXD
TXD
5NCXG
RXD
5NCXG
TXD
RXD
5NCXG
Note: The TXD pin of each slave controller must be in open-drain output mode.
Figure 8-14 Serial Link Using Wakeup Function
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8.4.4.2
Protocol
1. Select 9-bit UART mode on the master and slave controllers.
2. Set the SC0MOD0<WU> bit on each slave controller to “1” to enable data receiving.
3. The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The MSB (Bit8) <TB8> is set to “1”.
Start
Bit 0
1
2
3
4
5
6
7
Select code of slave controller
8
Stop
"1"
4. Each slave controller receives the above frame. Each controller checks the above select code
against its own select code. The controller whose code matches clears its WU bit to “0”.
5. The master controller transmits data to the specified slave controller whose SC0MOD0<WU>
bit is cleared to “0”. The MSB (Bit8) <TB8> is cleared to “0”.
Start
Bit 0
1
2
3
4
5
6
7
Bit 8
Stop
"0"
&CVC
6. The other slave controllers (whose <WU> bits remain at “1”) ignore the received data because
their MSBs (Bit8 or <RB8>) are set to “0”, disabling INTRX0 interrupts.
The slave controller (WU bit = “0”) can transmit data to the master controller, and it is possible
to indicate the end of data receiving to the master controller by this transmission.
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8.4.4.3
Example
To link two slave controllers serially with the master controller using the internal clock fSYS as the
transfer clock.
TXD
RXD
TXD
/CUVGT
RXD
TXD
RXD
5NCXG
5NCXG
5GNGEVEQFG
00000001
5GNGEVEQFG
00001010
Main settings (except port setting)
Register
INTES0
MSB
←
LSB
7
6
5
4
3
2
1
0
X
1
0
0
X
1
0
1
Enable the INTTX0 interrupt and set it to interrupt level 4.
Enable the INTRX0 interrupt and set it to interrupt level 5.
SC0MOD0
←
1
0
1
0
1
1
1
0
Set fSYS as the transmission clock for 9-bit UART mode.
SC0BUF
←
0
0
0
0
0
0
0
1
Set the select code for slave controller 1.
INTTX0 interrupt
Register
MSB
LSB
7
6
5
4
3
2
1
0
SC0MOD0
←
0
–
–
–
–
–
–
–
Set TB8 to “0”.
SC0BUF
←
*
*
*
*
*
*
*
*
Set data for transmission.
Main settings (except port setting)
Register
MSB
LSB
7
6
5
4
3
2
1
0
INTES0
←
X
1
0
1
X
1
1
0
SC0MOD0
←
0
0
1
1
1
1
1
0
7
6
5
4
3
2
1
0
–
0
–
–
–
–
Enable INTRX0 and INTTX0.
Set <WU> to “1” in 9-bit UART transmission mode using fSYS as the
transmission clock.
INTRX0 interrupt
Register
MSB
LSB
Acc ← SC0BUF, if Acc = select code
then SC0MOD0
←
–
–
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Clear <WU> to “0”.
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TMP91FW60
9. Serial Bus Interface (SBI)
The TMP91FW60 has a 2-channel serial bus interface which an I2C bus mode. This circuit supports only I2C bus
mode (Multi master).
The serial bus interface is connected to an external device through SDA0,SCL0,SDA1 and SCL1 in the I2C bus
mode.
9.1 Configuration
INTSBI interrupt request
SCL
+PRWV
output
control
HU[U
Noise
canceller
Divider
I2C bus
clock sysn.
Control
SBInCR2/
SBInSR
SBIn control register 2/
SBIn status register
SDAn
Transfer
control
circuit
5JKHV
TGIKUVGT
I2C bus
FCVC
EQPVTQN
I2CnAR
SBInDBR
SBInCR1
I2C bus/
address register
SBIn data/
buffer register
SBIn control
register 1
SCLn
0QKUG
ECPEGNNGT
SBInBR
SDA
0QVGP
SBIn baud rate
registers
Figure 9-1 Serial Bus Interface (SBI)
9.2 Serial Bus Interface (SBI) Control
The following registers are used to control the serial bus interface and monitor the operation status.
• Serial bus interface control register 0 (SBI0CR0, SBI1CR0)
• Serial bus interface control register 1 (SBI0CR1, SBI1CR1)
• Serial bus interface control register 2 (SBI0CR2, SBI1CR2)
• Serial bus interface data buffer register (SBI0DBR, SBI1DBR)
• I2C bus address register (I2C0AR, I2C1AR)
• Serial bus interface status register (SBI0SR, SBI1SR)
• IDLE2 control register (SBI0BR, SBI1BR)
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9.3 Operation in I2C Bus Mode
Both channels operate in the same function except for the following points; hence only the operation of channel 0
is explained below.
9.3.1
The Data Formats in the I2C Bus Mode
The data formats in the I2C bus mode is shown below.
(a) Addressing format
8 bits
1
RA
S Slave address / C
WK
1 to 8 bits
1
1 to 8 bits
Data
A
C
K
Data
1
1
A
CP
K
1 or more
(b) Addressing format (with restart)
8 bits
1
RA
S Slave address / C
WK
1
1 to 8 bits
Data
1
8 bits
1
A
RA
C S Slave address / C
K
WK
1 or more
1
1 to 8 bits
Data
1
A
CP
K
1 or more
(c) Free data format (Data transferred from master device to slave device)
S
8 bits
1
1 to 8 bits
1
1 to 8 bits
Data
A
C
K
Data
A
C
K
Data
1
S
R/W
ACK
P
1
A
CP
K
1 or more
: Start condition
: Direction bit
: Acknowledge bit
: Stop condition
Figure 9-2 Data Format in the I2C Bus Mode
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9.3.2
I2C Bus Mode Control Register
The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I2C bus mode.
Serial Bus Interface Control Register 0 (Read-modify-write instructions are prohibited.)
SBI0CR0
(0247H)
SBI1CR0
(024FH)
7
6
5
4
3
2
1
0
Bit symbol
SBI0EN
–
–
–
–
–
–
–
Read/Write
R/W
After reset
0
0
0
0
0
0
0
0
Bit symbol
SBI1EN
–
–
–
–
–
–
–
Read/Write
R/W
0
0
0
After reset
Function
R
R
0
0
0
0
SBI
operation
0: disable
1: enable
0
Always read "0".
Note <SBIEN>: When using SBI, <SBIEN> should be set "1" (SBI operation enable) before setting each register of SBI module.
Serial Bus Interface Control Register 1 (Read-modify-write instructions are prohibited.)
7
Bit symbol
SBI0CR1
(0240H)
BC2
Bit symbol
4
BC0
W
0
0
BC2
BC0
W
0
0
–
R/W
–
0
–
ACK
–
R/W
–
0
–
0
Acknowledge mode
specification
Number of transferred bits
(Note 1)
Function
3
ACK
0
BC1
Read/Write
After reset
5
BC1
Read/Write
After reset
SBI1CR1
(0248H)
6
2
SCK2
1
0
SCK1
SCK0/
SWRMON
W
0
SCK2
R/W
0
0/1
SCK1
SCK0/
SWRMON
W
0
R/W
0
0/1
Internal serial clock selection and software
reset monitor
(Note 2)
Internal serial clock selection <SCK2:0> at write
000
n=4
– (Note3)
001
n=5
73.53 kHz
010
n=6
50.00 kHz
011
n=7
30.49 kHz
100
n=8
17.12 kHz
101
n=9
9.12 kHz
110
n = 10
4.72 kHz
111
(Reserved)
SCK2:0
System clock: fc
Clock gear: fc/1
fc =20 MHz (Internal SCL output)
fscl = (fSYS/2) / (2n+36) [Hz]
(Reserved)
Software reset state monitor <SWRMON> at read
0
During software reset
1
Initial data
SWRMON
Acknowledge mode specification
0
Not generate clock pulse for acknowledge signal
1
Generate clock pulse for acknowledge signal
ACK
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Number of bits transferred
<ACK> = 0
<BC2:0>
BC2:0
Number of
clock pulses
000
<ACK> = 1
Bits
Number of
clock pulses
Bits
8
8
9
8
001
1
1
2
1
010
2
2
3
2
011
3
3
4
3
100
4
4
5
4
101
5
5
6
5
110
6
6
7
6
111
7
7
8
7
Note 1: For the frequency of the SCL line clock, see 9.3.3.3 “Serial clock”.
Note 2: Initial data of SCK0 is “0”,SWRMON is “1”.
Note 3: This I2C bus circuit dose not support high-speed mode, it supports standard mode only. The fscl speed can be selected
over 100 kbps by fc and <SCK2:0>, however it’s irregular operation.
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Serial Bus Interface Control Register 2 (Read-modify-write instructions are prohibited.)
Bit symbol
SBI0CR2
(0243H)
SBI1CR2
(024BH)
7
6
MST
TRX
Read/Write
5
4
3
BB
PIN
SBIM1
W
2
1
0
SBIM0
SWRST1
W
SWRST0
W
After reset
0
0
0
1
0
0
0
0
Bit symbol
MST
TRX
BB
PIN
SBIM1
SBIM0
SWRST1
SWRST0
0
0
0
1
0
0
0
Read/Write
After reset
Function
W
Master/slave
selection
Transmitter/
receiver
selection
W
Start/stop
condition
generation
Cancel
INTSBI
interrupt
request
W
Serial bus interface operation mode selection
0
Software reset generate
Software reset generate
SWRST1:0
10
↓
01
Write “10” and “01”, then an internal reset signal is generated
Serial bus interface operating mode selection (Note 2)
00
Port mode (Serial bus interface output disabled)
01
(Reserved)
10
I2C bus mode
11
(Reserved)
SBIM1:0
INTSBI interrupt request
0
–
1
Cancel interrupt request
PIN
Start/stop condition generation
0
Generates the stop condition
1
Generates the start condition
BB
Transmitter/receiver selection
0
Receiver
1
Transmitter
0
Slave
1
Master
TRX
Master/slave selection
MST
Note 1: Reading this register functions as SBI0SR/SBI1SR register.
Note 2: Switch to port mode after confirming that the bus is free.
Switch a mode between I2C bus mode and clocked-synchronous 8-bit SIO mode after confirming that input signals via
port are high level.
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Serial Bus Interface Status Register (Read-modify-write instructions are prohibited.)
Bit symbol
SBI0SR
(0243H)
SBI1SR
(024BH)
7
6
5
4
MST
TRX
BB
PIN
Read/Write
3
2
1
0
AL
AAS
AD0
LRB
R
After reset
0
0
0
1
0
0
0
0
Bit symbol
MST
TRX
BB
PIN
AL
AAS
AD0
LRB
0
0
0
1
0
0
0
0
Arbitration
lost detection
monitor
Slave
address
match detection monitor
GENERAL
CALL detection monitor
Last
received bit
monitor
Read/Write
After reset
Function
R
Master/slave
status monitor
Transmitter/
receiver status monitor
I2C bus status monitor
INTSBI
interrupt
request
monitor
Last received bit monitor
0
Last received bit was 0
1
Last received bit was 1
LRB
GENERAL CALL detection monitor
0
Undetected
1
GENERAL CALL detected
AD0
Slave address match detection monitor
0
Undetected
1
Slave address match or GENERAL CALL detected
AAS
Arbitration lost detection monitor
0
–
1
Arbitration lost detected
AL
INTSBI interrupt request monitor
0
Interrupt requested
1
Interrupt canceled
PIN
I2C bus status monitor
0
Free
1
Busy
BB
Transmitter/receiver status monitor
0
Receiver
1
Transmitter
TRX
Master/slave status monitor
0
Slave
1
Master
MST
Note 1: Writing in this register functions as SBI0CR2/SBI1CR2.
Note 2: The initial data SBI0SR/SBI1SR<PIN> is "1" if SBI operation is enable (SBI0CR0<SBI0EN>/SBI1CR0<SBI1EN> "1"). If
SBI operation is disable (SBI0CR0<SBI0EN>/SBI1CR0<SBI1EN> "0"), the initial data of SBI0SR/SBI1SR<PIN> is "0".
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IDLE2 Control Register (Read-modify-write instructions are prohibited.)
SBI0BR
(0244H)
SBI1BR
(024CH)
7
6
Bit symbol
–
I2SBI0
–
–
–
–
–
–
Read/Write
W
R/W
–
–
–
–
–
R/W
After reset
0
0
–
–
–
–
–
0
Bit symbol
–
I2SBI1
–
–
–
–
–
–
Read/Write
W
R/W
–
–
–
–
–
R/W
After reset
0
0
–
–
–
–
–
0
Always write
“0”
Operation in
IDLE2 mode
0: Stop
1: Operate
Function
5
4
3
2
1
0
Always write
“0”
Serial Bus Interface Data Buffer Register (Read-modify-write instructions are prohibited.)
Bit symbol
SBI0DBR
(0241H)
7
6
5
DB7
DB6
DB5
Read/Write
4
3
2
1
0
DB4
DB3
DB2
DB1
DB0
DB2
DB1
DB0
R (Received)/W (Transfer)
After reset
Bit symbol
SBI1DBR
(0249H)
Undefined
DB7
DB6
DB5
DB4
DB3
Read/Write
R (Received)/W (Transfer)
After reset
Undefined
Note 1: When writing transmitted data, start from the MSB (bit7).Receiving data is placed from LSB (bit0).
Note 2: SBI0DBR can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is prohibitted.
I2C Bus Address Register (Read-modify-write instructions are prohibited.)
7
6
5
4
3
2
1
0
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ALS
After reset
0
0
0
0
0
0
0
0
Bit symbol
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ALS
0
0
0
Bit symbol
I2C0AR
(0242H)
I2C1AR
(024AH)
Read/Write
W
Read/Write
After reset
W
0
Function
0
0
0
Slave address selection for when device is operating as slave device
0
Address
recognition
mode specification
Address recognition mode specification
0
Slave address recognition
1
Non slave address recognition
ALS
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9.3.3
Control in I2C Bus Mode
9.3.3.1
Acknowledge mode specification
Set the SBI0CR1<ACK> to “1” for operation in the acknowledge mode. The TMP91FW60 generates an
additional clock pulse for an acknowledge signal when operating in master mode. In the transmitter mode
during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the
receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the low in order to generate the acknowledge signal.
Clear the <ACK> to “0” for operation in the non-acknowledge mode, the TMP91FW60 does not generate a clock pulse for the acknowledge signal when operating in the master mode.
9.3.3.2
Number of transfer bits
The SBI0CR1<BC2:0> is used to select a number of bits for next transmitting and receiving data.
Since the <BC2:0> is cleared to “000” as a start condition, a slave address and direction bit transmission
are always executed in 8 bits. Other than these, the <BC2:0> retains a specified value.
9.3.3.3
Serial clock
(1)
Clock source
The SBI0CR1<SCK2:0> is used to select a maximum transfer frequency outputted on the SCL pin
in master mode. Set the baud rates, which have been calculated according to the formula below, to
meet the specifications of the I2C bus, such as the smallest pulse width of tLOW.
tHIGH
tLOW
1/fscl
Figure 9-3 Clock Source
SBI0CR1<SCK2:0>
n
000
001
010
011
100
101
110
4
5
6
7
8
9
10
tLOW = (2n − 1+29)/fSBI
tHIGH = (2n − 1+7)/fSBI
fscl = 1/(tLOW + tHIGH) = fSBI/(2n + 36)
Note: fSBI shows fSYS/2
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(2)
Clock synchronization
In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line
to low level, in the first place, invalidate a clock pulse of another master device which generates a
high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation
and implement the following procedure.
The TMP91FW60 has a clock synchronization function for normal data transfer even when more
than one master exists on the bus.
The example explains the clock synchronization procedures when two masters simultaneously
exist on a bus.
Wait counting high-level
width of a clock pulse
Start counting high-level width of a clock pulse
Internal SCL output
(Master A)
Internal SCL output
(Master B)
Reset a counter of
high-level width of a
clock pulse
SCL pin
a
b
c
Figure 9-4 Clock Synchronization
As master A pulls down the internal SCL output to the low level at point “a”, the SCL line of the
bus becomes the low level. After detecting this situation, master B resets a counter of high-level
width of an own clock pulse and sets the internal SCL output to the low level.
Master A finishes counting low-level width of an own clock pulse at point “b” and sets the internal
SCL output to the high level. Since master B holds the SCL line of the bus at the low level, master A
waits for counting high-level width of an own clock pulse. After master B finishes counting lowlevel width of an own clock pulse at point “c” and master A detects the SCL line of the bus at the
high level, and starts counting high level of an own clock pulse. The clock pulse on the bus is determined by the master device with the shortest high-level width and the master device with the longest
low-level width from among those master devices connected to the bus.
9.3.3.4
Slave address and address recognition mode specification
When the TMP91FW60 is used as a slave device, set the slave address <SA6:0> and <ALS> to the
I2C0AR. Clear the <ALS> to “0” for the address recognition mode.
9.3.3.5
Master/slave selection
Set the SBI0CR2<MST> to “1” for operating the TMP91FW60 as a master device. Clear the
SBI0CR2<MST> to “0” for operation as a slave device. The <MST> is cleared to “0” by the hardware
after a stop condition on the bus is detected or arbitration is lost.
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9.3.3.6
Transmitter/receiver selection
Set the SBI0CR2<TRX> to “1” for operating the TMP91FW60 as a transmitter. Clear the <TRX> to
“0” for operation as a receiver.
When data with an addressing format is transferred in slave mode, when a slave address with the same
value that an I2C0AR or a GENERAL CALL is received (All 8-bit data are “0” after a start condition), the
<TRX> is set to “1” by the hardware if the direction bit (R/W) sent from the master device is “1”, and
<TRX> is cleared to “0” by the hardware if direction bit is “0”.
In the master mode, after an acknowledge signal is returned from the slave device, the <TRX> is
cleared to “0” by the hardware if a transmitted direction bit is “1”, and <TRX> is set to “1” by the hardware if direction is “0”. When an acknowledge signal is not returned, the current condition is maintained.
The <TRX> is cleared to “0” by the hardware after a stop condition on the I2C bus is detected or arbitration is lost.
9.3.3.7
Start/stop condition generation
When the SBI0SR<BB> is “0”, slave address and direction bit which are set to SBI0DBR are output on
a bus after generating a start condition by writing “1” to the SBI0CR2<MST, TRX, BB, PIN>. It is necessary to set transmitted data to the data buffer register (SBI0DBR) and set “1” to <ACK> beforehand.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
A6
A5
A4
A3
A2
A1
A0
R/W
Slave address and the direction bit
Start condition
9
Acknowledge signal
Figure 9-5 Start Condition Generation and Slave Address Generation
When the <BB> is “1”, a sequence of generating a stop condition is started on the bus by writing “1” to
the <MST, TRX, PIN>, and “0” to the <BB>. Do not modify the contents of <MST, TRX, BB, PIN> until
a stop condition is generated on the bus.
SCL pin
SDA pin
Stop condition
Figure 9-6 Stop Condition Generation
The state of the bus can be ascertained by reading the contents of SBI0SR<BB>. SBI0SR<BB> will be
set to “1” if a start condition has been detected on the bus, and will be cleared to “0” if a stop condition has
been detected.
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9.3.3.8
Interrupt service requests and interrupt cancellation
When a serial bus interface interrupt request (INTSBI) occurs, the SBI0CR2<PIN> is cleared to “0”.
During the time that the SBI0CR2<PIN> is “0”, the SCL line is pulled down to the low level.
The <PIN> is cleared to “0” when an 1 word of data is transmitted or received. Either writing/reading
data to/from SBI0DBR sets the <PIN> to “1”.
The time from the <PIN> being set to “1” until the SCL line is released takes tLOW.
In the address recognition mode (<ALS> = “0”), <PIN> is cleared to “0” when the received slave
address is the same as the value set at the I2C0AR or when a GENERAL CALL is received (All 8-bit data
are “0” after a start condition). Although SBI0CR2<PIN> can be set to “1” by the program, the <PIN> is
not cleared to “0” when it is written “0”.
9.3.3.9
Serial bus interface operation mode selection
SBI0CR2<SBIM1:0> is used to specify the serial bus interface operation mode.
Set SBI0CR2<SBIM1:0> to “10” when the device is to be used in I2C bus mode after confirming pin
condition of serial bus interface to “H”.
Switch to port mode after confirming a bus is free.
9.3.3.10 Arbitration lost detection monitor
Since more than one master device can exist simultaneously on the bus in I2C bus mode, a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data.
Data on the SDA line is used for I2C bus arbitration.
The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on the bus. Master A and master B output the same data until point “a”. After master A outputs
“L” and master B, “H”, the SDA line of the bus is wired-AND and the SDA line is pulled down to the low
level by master A. When the SCL line of the bus is pulled up at point b, the slave device reads the data on
the SDA line, that is, data in master A. A data transmitted from master B becomes invalid. The state in
master B is called “ARBITRATION LOST”. Master B device which loses arbitration releases the internal
SDA output in order not to affect data transmitted from other masters with arbitration. When more than
one master sends the same data at the first word, arbitration occurs continuously after the second word.
SCL pin
Internal SDA output
(Master A)
Internal SDA output
(Master B)
Internal SDA output becomes 1 after arbitration
has been lost.
SDA pin
a
b
Figure 9-7 Arbitration Lost
The TMP91FW60 compares the levels on the bus’s SDA line with those of the internal SDA output on
the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBI0SR<AL> is set to
“1”.
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When SBI0SR<AL> is set to “1”, SBI0SR<MST, TRX> are cleared to “00” and the mode is switched
to slave receiver mode. Thus, clock output is stopped in data transfer after setting <AL> = “1”.
SBI0SR<AL> is cleared to “0” when data is written to or read from SBI0DBR or when data is written to
SBI0CR2.
Internal
SCL output
1
2
3
D7A D6A
D5A
4
5
6
7
8
9
1
2
3
4
Master A
Internal
SDA output
D4A D3A D2A D1A D0A
D7A' D6A' D5A' D4A'
Stop the clock pulse
Internal
SCL output
1
2
3
4
Master B
Internal
SDA output
D7B D6B
Keep internal SDA output to high level as losing arbitration
<AL>
<MST>
<TRX>
Accessed to
SBI0DBR or SBI0CR2
Figure 9-8 Example of when TMP91FW60 is a Master Device B (D7A = D7B, D6A = D6B)
9.3.3.11 Slave address match detection monitor
SBI0SR<AAS> is set to “1” in slave mode, in address recognition mode (e.g., when I2C0AR<ALS> =
“0”), when a GENERAL CALL is received, or when a slave address matches the value set in I2C0AR.
When I2C0AR<ALS> = “1”, SBI0SR<AAS> is set to “1” after the first word of data has been received.
SBI0SR<AAS> is cleared to “0” when data is written to or read from the data buffer register SBI0DBR.
9.3.3.12 GENERAL CALL detection monitor
SBI0SR<AD0> is set to “1” in slave mode, when a GENERAL CALL is received (All 8-bit received
data is “0” after a start condition). SBI0SR<AD0> is cleared to “0” when a start condition or stop condition is detected on the bus.
9.3.3.13 Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is set to the SBI0SR<LRB>. In the
acknowledge mode, immediately after an INTSBI interrupt request is generated, an acknowledge signal is
read by reading the contents of the SBI0SR<LRB>.
9.3.3.14 Software reset function
The software reset function is used to initialize the SBI circuit, when SBI is locked by external noises,
etc.
An internal reset signal pulse can be generated by setting SBI0CR2<SWRST1:0> to “10” and “01”.
This initializes the SBI circuit internally. All control registers and status registers are initialized as well.
SBI0CR1<SWRMON> is automatically set to “1” after the SBI circuit has been initialized.
Note: If the software reset is executed, operation selection is reset, and its mode is set to port mode from I2C
mode.
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9.3.3.15 Serial bus interface data buffer register (SBI0DBR)
The received data can be read and transferred data can be written by reading or writing the SBI0DBR.
In the master mode, after the start condition is generated the slave address and the direction bit are set in
this register.
9.3.3.16 I2CBUS address register (I2C0AR)
I2C0AR<SA6:0> is used to set the slave address when the TMP91FW60 functions as a slave device.
The slave address output from the master device is recognized by setting the I2C0AR<ALS> to “0”.
The data format is the addressing format. When the slave address is not recognized at the <ALS> = “1”,
the data format is the free data format.
9.3.3.17 Setting register for IDLE2 mode operation (SBI0BR0)
SBI0BR0<I2SBI0> is the register setting operation/stop during IDLE2 mode. Therefore, setting
<I2SBI0> is necessary before the HALT instruction is executed.
9.3.4
Data Transfer in I2C Bus Mode
9.3.4.1
Device initialization
Set the SBI0CR1<ACK, SCK2:0>, clear bits 2 to 0 and 4 in the SBI0CR1 to “0”.
Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing format) to the I2C0AR.
For specifying the default setting to a slave receiver mode, clear “0” to the SBI0CR2<MST, TRX, BB>,
set “1” to the <PIN>, “10” to the <SBIM1:0>, and write “0” to bit 1, 0.
7
6
5
4
3
2
1
0
SBI0CR1
←
X
X
X
0
X
0
0
0
Set acknowledge and SCL clock.
I2C0AR
←
X
X
X
X
X
X
X
0
Set slave address and address recognition mode.
SBI0CR2
←
0
0
0
1
1
0
0
0
Set to slave receiver mode.
Note: X: Don’t care
Page 173
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TMP91FW60
9.3.4.2
Start condition and slave address generation
(1)
Master mode
In the master mode, the start condition and the slave address are generated as follows.
Check a bus free status (when <BB> = “0”).
Set the SBI0CR1<ACK> to “1” (Acknowledge mode) and specify a slave address and a direction
bit to be transmitted to the SBI0DBR.
When SBI0CR2<BB> = “0”, the start condition are generated by writing “1” to SBI0CR2<MST,
TRX, BB, PIN>. Subsequently to the start condition, nine clocks are output from the SCL pin. While
eight clocks are output, the slave address and the direction bit which are set to the SBI0DBR. At the
9th clock, the SDA line is released and the acknowledge signal is received from the slave device.
An INTSBI0 interrupt request occurs at the falling edge of the 9th clock. The <PIN> is cleared to
“0”. In the master mode, the SCL pin is pulled down to the low level while <PIN> is “0”. When an
interrupt request occurs, the <TRX> is changed according to the direction bit only when an acknowledge signal is returned from the slave device.
Setting in main routine
7
6
5
Reg
←
SBI0SR
Reg
←
Reg. 0X20
4
3
2
1
0
≠0x00
if Reg
Wait until bus is free.
Then
SBI0CR1
←
X
X
X
1
X
0
0
0
Set to acknowledgement mode.
SBI0DBR
←
X
X
X
X
X
X
X
X
Set slave address and direction bit.
SBI0CR2
←
1
1
1
1
1
0
0
0
Generate start condition.
In INTSBI0 interrupt routine
INTCLR <-- 0x30
; Clear the interrupt request
Process
End of interrupt
(2)
Slave mode
In the slave mode, the start condition and the slave address are received.
After the start condition is received from the master device, while eight clocks are output from the
SCL pin, the slave address and the direction bit which are output from the master device are received.
When a GENERAL CALL or the same address as the slave address set in I2C0AR is received, the
SDA line is pulled down to the low level at the 9th clock, and the acknowledge signal is output.
An INTSBI0 interrupt request occurs on the falling edge of the 9th clock. The <PIN> is cleared to
“0”. In slave mode the SCL line is pulled down to the low level while the <PIN> = “0”.
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TMP91FW60
SCL pin
1
2
3
4
5
6
7
8
9
SDA pin
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
Slave address + Direction bit
Start condition
Acknowledge
signal from a slave
device
<PIN>
INTSBI
interrupt request
Output of master
Output of slave
Figure 9-9 Start Condition Generation and Slave Address Transfer
9.3.4.3
1-word data transfer
Check the <MST> by the INTSBI0 interrupt process after the 1-word data transfer is completed, and
determine whether the mode is a master or slave.
(1)
If <MST> = “1” (Master mode)
Check the <TRX> and determine whether the mode is a transmitter or receiver.
(a) When the <TRX> = “1” (Transmitter mode)
Check the <LRB>. When <LRB> is “1”, a receiver does not request data. Implement the process to generate a stop condition (Refer to below) and terminate data transfer.
When the <LRB> is “0”, the receiver requests new data. When the next transmitted data is 8
bits, write the transmitted data to SBI0DBR. When the next transmitted data is other than 8
bits, set the <BC2:0> <ACK> and write the transmitted data to SBI0DBR. After written the
data, <PIN> becomes “1”, a serial clock pulse is generated for transferring a new 1 word of
data from the SCL pin, and then the 1-word data is transmitted. After the data is transmitted, an
INTSBI interrupt request occurs. The <PIN> becomes “0” and the SCL line is pulled down to
the low level. If the data to be transferred is more than one word in length, repeat the procedure
from the <LRB> checking above.
if MST = 0
Then shift to the process when slave mode
if TRX = 0
Then shift to the process when receiver mode.
if LRB = 0
Then shift to the process that generates stop condition.
7
6
5
4
3
2
1
0
SBI0CR1
←
0
0
0
1
X
X
X
X
Set the bit number of transmit and ACK.
SBI0DBR
←
X
X
X
X
X
X
X
X
Write the transmit data.
End of interrupt
Note: X: Don’t care
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TMP91FW60
SCL pin
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Write to SBI0DBR
SDA pin
Acknowledge signal
from a receiver
<PIN>
INTSBI interrupt request
Output from master
Output from slave
Figure 9-10 Example in which <BC2:0> = “000” and <ACK> = “1” in Transmitter Mode
(b) When the <TRX> is “0” (Receiver mode)
When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and read the
received data from SBI0DBR to release the SCL line (Data which is read immediately after a
slave address is sent is undefined). After the data is read, <PIN> becomes “1”. Serial clock
pulse for transferring new 1 word of data is defined SCL and outputs “L” level from SDA pin
with acknowledge timing.
An INTSBI0 interrupt request then occurs and the <PIN> becomes “0”, then the
TMP91FW60 pulls down the SCL pin to the low level. The TMP91FW60 outputs a clock pulse
for 1 word of data transfer and the acknowledge signal each time that received data is read from
the SBI0DBR.
Read SBI0DBR
SCL pin
1
2
3
4
5
6
7
8
9
SDA pin
D7
D6
D5
D4
D3
D2
D1
D0
ACK
ᰴߩD7
Acknowledge
signal to a
<PIN>
INTSBI interrupt request
Output from master
Output from slave
Figure 9-11 Example of when <BC2:0> = “000”, <ACK> = “1” in Receiver Mode
In order to terminate the transmission of data to a transmitter, clear <ACK> to “0” before
reading data which is 1 word before the last data to be received. The last data word does not
generate a clock pulse as the acknowledge signal. After the data has been transmitted and an
interrupt request has been generated, set <BC2:0> to “001” and read the data. The
TMP91FW60 generates a clock pulse for an 1-bit data transfer. Since the master device is a
receiver, the SDA line on the bus remains high. The transmitter interprets the high signal as an
ACK signal. The receiver indicates to the transmitter that data transfer is complete.
After the one data bit has been received and an interrupt request been generated, the
TMP91FW60 generates a stop condition and terminates data transfer.
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TMP91FW60
SCL pin
9
SDA pin
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
1
Acknowledge sig
sent to a transmit
<PIN>
INTSBI interrupt request
"0" ψ <ACK>
Read SBI0DBR
"001" ψ <BC2:0>
Read SBI0DBR
Output of master
Output of slave
Figure 9-12 Termination of Data Transfer in Master Receiver Mode
Example: In case receive data N times
INTSBI0 interrupt (After transmitting data)
SBI0CR1
Reg.
←
←
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
SBI0DBR
Set the bit number of receive data and ACK.
Load the dummy data.
End of interrupt
INTSBI0 interrupt (Receive data of 1st to (N 2) th)
7
←
Reg.
6
5
4
3
2
1
0
SBI0DBR
Load the data of 1st to (N 2)th.
End of interrupt
INTSBI0 interrupt ((N 1) th Receive data)
SBI0CR1
Reg.
←
←
7
6
5
4
3
2
1
0
X
X
X
0
0
X
X
X
SBI0DBR
Not generate acknowledge signal
Load the data of (N 1)th
End of interrupt
INTSBI0 interrupt (Nth Receive data)
SBI0CR1
Reg.
←
←
7
6
5
4
3
2
1
0
0
0
1
0
0
X
X
X
SBI0DBR
Generate the clock for 1bit transmit
Receive the data of Nth.
End of interrupt
INTSBI0 interrupt (After receiving data)
The process of generating stop condition
Finish the transmit of data
End of interrupt
Note: X: Don’t care
(2)
If <MST> = 0 (Slave mode)
In the slave mode the TMP91FW60 operates either in normal slave mode or in slave mode after
losing arbitration.
In the slave mode, an INTSBI0 interrupt request occurs when the TMP91FW60 receives a slave
address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and
data transfer is complete, or after matching received address. In the master mode, the TMP91FW60
operates in a slave mode if it detects losing arbitration. An INTSBI0 interrupt request occurs when a
word data transfer terminates after losing arbitration. When an INTSBI0 interrupt request occurs the
<PIN> is cleared to “0” and the SCL pin is pulled down to the low level. Either reading/writing from/
to the SBI0DBR or setting the <PIN> to “1” will release the SCL pin after taking tLOW time.
Check the SBI0SR<AL>, <TRX>, <AAS>, and <AD0> and implements processes according to
conditions listed in the next table.
Page 177
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TMP91FW60
Example: In case matching slave address in slave receive mode, direction bit is "1".
INTSBI0 interrupt
if TRX = 0
Then shift to other process
if AL = 1
Then shift to other process
if AAS = 0
Then shift to other process
7
6
5
4
3
2
1
0
SBI0CR1
←
X
X
X
1
X
X
X
X
Set the bit number of transmit.
SBI0DBR
←
X
X
X
X
X
X
X
X
Set the data of transmit.
Note: X: Don’t care
Table 9-1
<TRX>
Operation in the Slave Mode
<AL>
1
<AAS>
1
1
<AD0>
Conditions
0
The TMP91FW60 loses arbitration when
transmitting a slave address and
receives a slave address for which the
value of the direction bit sent from
another master is “1”.
0
1
In slave receiver mode, the TMP91FW60
receives a slave address for which the
value of the direction bit sent from the
master is “1”.
0
0
In slave transmitter mode, a single word
of data is transmitted.
1/0
The TMP91FW60 loses arbitration when
transmitting a slave address and
receives a slave address or GENERAL
CALL for which the value of the direction
bit sent from another master is “0”.
0
The TMP91FW60 loses arbitration when
transmitting a slave address or data and
terminates word data transfer.
1
1/0
In slave receiver mode, the TMP91FW60
receives a slave address or GENERAL
CALL for which the value of the direction
bit sent from the master is “0”.
0
1/0
In slave receiver mode, the TMP91FW60
terminates receiving word data.
0
1
1
0
0
0
Page 178
Process
Set the number of bits a word in <BC2:0>
and write the transmitted data to
SBI0DBR.
Check the <LRB> setting. If <LRB> is set
to “1”, set <PIN> to “1” since the receiver
win no request the data which follows.
Then, clear <TRX> to “0” to release the
bus. If <LRB> is cleared to “0”, set
<BC2:0> to the number of bits in a word
and write the transmitted data to
SBI0DBR since the receiver requests
next data.
Read the SBI0DBR for setting the <PIN>
to “1” (Reading dummy data) or set the
<PIN> to “1”.
Set <BC2:0> to the number of bits in a
word and read the received data from
SBI0DBR.
2007-10-15
TMP91FW60
9.3.4.4
Stop condition generation
When SBI0SR<BB> = “1”, the sequence for generating a stop condition is started by writing “1” to
SBI0CR2<MST, TRX, PIN> and “0” to SBI0CR2<BB>. Do not modify the contents of SBI0CR2<MST,
TRX, PIN, BB> until a stop condition has been generated on the bus. When the bus’s SCL line has been
pulled low by another device, the TMP91FW60 generates a stop condition when the other device has
released the SCL line and SDA pin rising.
SBI0CR2
←
7
6
5
4
3
2
1
0
1
1
0
1
1
0
0
0
Generate stop condition.
1 ψ <MST>
"1" ψ <TRX>
"0" ψ <BB>
"1" ψ <PIN>
Stop condition
Internal SCL
SDA pin
<PIN>
<BB> (Read)
Figure 9-13 Stop Condition Generation (Single master)
"1" ψ <MST>
"1" ψ <TRX>
"0" ψ <BB>
"1" ψ <PIN>
Internal SCL
SCL pin
Stop condition
The case of pulled
low by another device
SDA pin
<PIN>
<BB> (Read)
Figure 9-14 Condition Generation (Multi master)
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TMP91FW60
9.3.4.5
Restart
Restart is used during data transfer between a master device and a slave to change the data transfer
direction.
The following description explains how to restart when the TMP91FW60 is in Master mode.
Clear SBI0CR2<MST, TRX, BB> to “0” and set SBI0CR2<PIN> to “1” to release the bus. The SDA
line remains High and the SCL pin is released. Since a stop condition has not been generated on the bus,
other devices assume the bus to be in busy state.
And confirm SCL pin, that SCL pin is released and become bus-free state by SBI0SR<BB> = “0” or
signal level “1” of SCL pin by sensing its port (change to input mode). Check the <LRB> until it becomes
“1” to check that the SCL line on a bus is not pulled down to the low level by other devices. After confirming that the bus remains in a free state, generate a start condition using the procedure described in
9.3.4.2.
In order to satisfy the setup time requirements when restarting, take at least 4.7 μs of waiting time by
software from the time of restarting to confirm that the bus is free until the time to generate the start condition.
SBI0CR2
←
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
if SBI0SR<BB> ≠ 0
Release the bus
Check if SCL pin is released.
Then
if SBI0SR<LRB> ≠ 1
Check if SCL pin of other device is "L" level.
Then
4.7us Wait
SBI0CR1
SBI0DBR
SBI0CR2
←
←
←
0
0
0
1
0
X
X
X
Set acknowledgement mode.
X
X
X
X
X
X
X
X
Set the slave address and direction bit.
1
1
1
1
1
0
0
0
Generate start condition.
Note: X: Don’t care
"1"→<MST>
"1"→<TRX>
"1"→<BB>
"1"→<PIN>
"0"→<MST>
"0"→<TRX>
"0"→<BB>
"1"→<PIN>
4.7μs (Min)
Start condition
SCL pin
Internal SCL
9
SDA pin
<LRB>
<BB>
<PIN>
Figure 9-15 Timing Diagram for TMP91FW60 Restart
Note: Don't write <MST> "0", when <MST> "0" condition. (Cannot be restarted)
Page 180
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TMP91FW60
10. 10-bit AD Converter (ADC)
The TMP91FW60 have a 10-bit successive approximation type AD converter.
10.1 Configuration
The circuit configuration of the 10-bit AD converter is shown in Figure 10-1.
It consists of control register ADCCR1 and ADCCR2, converted value register ADCDRH and ADCDRL, a DA
converter, a sample-hold circuit, a comparator, and a successive comparison circuit.
DA converter
84'(* #8%% #0
#0
#0
#0
4
Analog input
multiplexer
# ;
$
1
2
5 5#+0
'0 #+0'0
4
#855
4
Sample hold
circuit
Reference
voltage
Analog comparator Successive approximate
circuit
Shift clock
Control circuit
+06#& ' #
#& 4 5 # /& #%- 1 %
#&%%4 &
45'. $
( (
#&%%4
AD converter control register 1, 2
5GNGEVQT
#&%&4. #&%&4* AD conversion result register 1, 2
Note: Before using AD converter, set appropriate value to I/O port register combining a analog input port. For details, see the section on "I/O ports".
Figure 10-1 10-bit AD Converter
10.2 Register configuration
The AD converter consists of the following four registers:
1. AD converter control register 1 (ADCCR1)
This register selects the analog channels and operation mode (single or repeat) in which to perform AD
conversion and controls the AD converter as it starts operating.
2. AD converter control register 2 (ADCCR2)
This register selects the AD conversion time and controls the connection of the DA converter (Ladder
resistor network) and monitors the operating status of the AD converter.
3. AD converted value register (ADCDRH, ADCDRL)
This register used to store the digital value after being converted by the AD converter.
Page 181
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TMP91FW60
AD Converter Control Register 1
7
Bit symbol
ADCCR1
(02B0H)
6
ADRS
5
4
AMD
Function
2
AINEN
Read/Write
After reset
3
1
0
0
0
SAIN
R/W
0
0
AD conversion start
0: 1: AD conversion start
0
AD operating mode
00: AD operation disable
01: single mode
10: Reserved
11: Repeat mode
0
0
0
Analog input channel select
Analog input
control
0:disable
1:enable
0000: AN0
0001: AN1
0010: AN2
0011: AN3
0100: AN4
0101: AN5
0110: AN6
0111: AN7
1000: AN8
1001: AN9
1010: AN10
1011: AN11
1100: AN12
1101: AN13
1110: AN14
1111: AN15
Note 1: Select analog input channel during AD converter stops (ADCCR2<ADBF> = “0”).
Note 2: When the analog input channel is all use disabling, the ADCCR1<AINEN> should be set to “0”.
Note 3: During conversion, Do not perform port output instruction to maintain a precision for all of the pins because analog input
port use as general input port. And for port near to analog input, Do not input intense signaling of change.
Note 4: The ADCCR1<ADRS> is automatically cleared to “0” after starting conversion.
Note 5: Do not set ADCCR1<ADRS> newly again during AD conversion. Before setting ADCCR1<ADRS> newly again, check
ADCDR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g.,
interrupt handling routine).
Note 6: Starting of STOP mode, SLOW mode, and the IDLE1 mode initializes the AD control register 1 (ADCCR1) except for
SAIN. Moreover, in the case of the IDLE2 mode, it controls by the <I2AD> bit of ADCCR2. Therefore, to use AD converter
again, set the ADCCR1 newly after returning to NORMAL mode.
AD Converter Control Register 2 (Read-modify-write instructions are prohibited.)
Bit symbol
ADCCR2
(02B1H)
7
6
5
4
EOCF
ADBF
RSEL
I2AD
Read/Write
After reset
0
0:Before or
during conversion
1: Conversion completed
2
1
0
0
0
ACK
R
AD conversion end flag
Function
3
R/W
0
AD conversion BUSY
flag
0: During
stop of AD
conversion
0
0
1
1
AD conversion time select
Storing of an
AD conversion result
0: 10bit
mode
IDLE2 control
0:Stop
See" Table 10-1 ACK setting and Conversion time "
1:Operation
1: During AD
conversion
1: 8bit mode
Note 1: Starting of STOP mode, SLOW mode, and the IDLE1 mode initializes the AD control register 2 (ADCCR2) except for ACK
and I2AD. Moreover, in the case of the IDLE2 mode, it controls by the <I2AD> bit of ADCCR2. Therefore, to use AD converter again, set the ADCCR2 newly after returning to NORMAL mode. Therefore, the AD conversion result should be
read to ADCDRL more first than ADCDRH.
Note 2: The ADCCR2<EOCF> is cleared to “0” when reading the ADCDRH.
Note 3: The ADCCR2<ADBF> is set to “1” when AD conversion starts, and cleared to “0” when AD conversion finished.
Page 182
2007-10-15
TMP91FW60
Table 10-1 ACK setting and Conversion time
Condition
ACK
Conversion
time
20MHz
16MHz
10 MHz
0xxx
Reserved
1000
Reserved
1001
Reserved
8MHz
4 MHz
2 MHz
1010
78/fc
−
−
−
−
19.5 μs
39.0 μs
1011
156/fc
−
−
15.6 μs
19.5 μs
39.0 μs
78.0 μs
1100
312/fc
15.6 μs
19.5 μs
31.2 μs
39.0 μs
78.0 μs
156.0 μs
1101
624/fc
31.2 μs
39.0 μs
62.4 μs
78.0 μs
156.0 μs
−
1110
1248/fc
62.4 μs
78.0 μs
124.8 μs
156.0 μs
−
−
1111
Reserved
Note 1: Setting for “-” in the above table are inhibited.
fc: High Frequency oscillation clock [Hz]
Note 2: Set conversion time setting should be kept more than the following time by Analog reference voltage.
−
VREFH = 4.5 to 5.5 V
15.6 us and more
AD Converted value Register H (8-bit storing mode)
Bit symbol
ADCDRH
(02B3H)
7
6
5
4
3
2
1
0
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
0
0
0
0
0
Read/Write
After reset
R
0
0
0
AD Converted value Register H (10-bit storing mode)
Bit symbol
ADCDRH
(02B3H)
7
6
5
4
3
2
1
0
−
−
−
−
−
−
AD09
AD08
Read/Write
After reset
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
0
0
0
0
AD Converted value Register L
Bit symbol
ADCDRL
(02B2H)
Read/Write
After reset
R
0
0
0
0
Note: At the time of 10-bit storing mode, if the bit 7 to 2 of ADCDRH is read, “0” will be read.
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TMP91FW60
10.3 Function
10.3.1 Single mode
After setting ADCCR1<AMD> to “01” (single mode), set ADCCR1<ADRS> to “1”. AD conversion of the
voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started.
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDRH, ADCDRL) and at the same time ADCCR2<EOCF> is set to 1, the AD conversion finished interrupt (INTADC) is generated.
ADCCR1<ADRS> is automatically cleared after AD conversion has started. Do not set ADCCR1<ADRS>
newly again (Restart) during AD conversion. Before setting ADCCR1<ADRS> newly again, check
ADCCR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine).
AD conversion start
AD conversion start
#&%%4#&45
#&%%4#&$(
#&%&4ZUVCVWU
Indeterminate
1st conversion result
2nd conversion result
EOCF cleared by reading
conversion result
#&%%4'1%(
+06#&%KPVGTTWRVTGSWGUV
#&%&4*
#&%&4.
Conversion result
read
Conversion result
read
Conversion result
read
Conversion result
read
Figure 10-2 Single mode
Page 184
2007-10-15
TMP91FW60
10.3.2 Repeat Mode
AD conversion of the voltage at the analog input pin specified by ADCCR1<SAIN> is performed repeatedly. In this mode, AD conversion is started by setting ADCCR1<ADRS> to “1” after setting
ADCCR1<AMD> to “11” (Repeat mode).
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDRL, ADCDRH) and at the same time ADCCR2<EOCF> is set to 1, the AD conversion finished interrupt (INTADC) is generated.
In repeat mode, each time one AD conversion is completed, the next AD conversion is started. To stop AD
conversion, set ADCCR1<AMD> to “00” (Disable mode) by writing 0s. The AD convert operation is stopped
immediately. The converted value at this time is not stored in the AD converted value register.
#/& When not performing conversion result read-out,
EOCF is not cleared and a conversion result is
not stored.
#/& #&45 Conversion
operation
#&%&4Z
1st conversion
result
Indeterminate
AD convert operation suspended.
Conversion result is not stored.
3rd conversion result
2nd conversion result
3rd conversion result
1st conversionresult
'1%( +06#& Conversion
result read
AD conversion start
Figure 10-3 Repeat Mode
10.3.3
Register Setting
1. Set up the AD converter control register 1 (ADCCR1) as follows:
• Choose the channel to AD convert using AD input channel select (SAIN).
• Specify analog input enable for analog input control (AINDS).
• Specify AMD for the AD converter control operation mode (ssingle or repeat mode).
2. Set up the AD converter control register 2 (ADCCR2) as follows:
Set the AD conversion time using AD conversion time (ACK). For details on how to set the conversion time, refer to Table 10-1 and AD converter control register 2.
3. After setting up (1) and (2) above, set AD conversion start (ADRS) of AD converter control register 1
(ADCCR1) to “1”. If software start mode has been selected, AD conversion starts immediately.
4. After an elapse of the specified AD conversion time, the AD converted value is stored in AD converted value register (ADCDRH and ADCDRL) and the AD conversion finished flag (EOCF) of AD
converter control register 2 (ADCCR2) is set to “1”, upon which time AD conversion interrupt
INTADC is generated.
5. EOCF is cleared to “0” by a read of the conversion result. However, if reconverted before a register
read, although EOCF is cleared the previous conversion result is retained until the next conversion is
completed.
Page 185
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TMP91FW60
Example :After selecting the conversion time 19.5 μs at 16 MHz and the analog input channel AIN3 pin, perform AD conversion once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store
the upper 8 bits in address 0009FH in RAM. The operation mode is single mode.
SLOOP :
LD
(ADCCR1) , 00110011B
; Select AIN3
LD
(ADCCR2) , 00001100B
;Select conversion time(312/fc) and operation
mode
SET
(ADCCR1) . 7
; ADRS = 1(AD conversion start)
TEST
(ADCCR2) . 7
; EOCF= 1 ?
JRS
T, SLOOP
LD
A , (ADCDRL)
LD
(9EH) , A
LD
A , (ADCDRH)
LD
(9FH), A
; Read result data
; Read result data
10.4 IDLE1/STOP/SLOW Modes during AD Conversion
When standby mode (IDLE1,STOP or SLOW mode) is entered forcibly during AD conversion, the AD convert
operation is suspended and the AD converter is initialized (ADCCR1 and ADCCR2 are initialized to initial value).
Also, the conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure
to read the conversion results before entering standby mode (IDLE1,STOP or SLOW mode).) When restored from
standby mode (IDLE1,STOP or SLOW mode), AD conversion is not automatically restarted, so it is necessary to
restart AD conversion. Note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage.
Moreover, in the case of the IDLE2 mode, it controls by the <I2AD> bit of ADCCR2.
Page 186
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TMP91FW60
10.5 Analog Input Voltage and AD Conversion Result
The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 10-4.
3FFH
3FEH
3FDH
AD
conversion
result
03H
02H
01H
˜
0
1
2
3
1021 1022 1023 1024
Analog input voltage
84'(*㧙 #855
1024
Figure 10-4 Analog Input Voltage and AD Conversion Result (Typ.)
Page 187
2007-10-15
TMP91FW60
10.6 Precautions about AD Converter
10.6.1 Analog input pin voltage range
Make sure the analog input pins (AN0 to AN15) are used at voltages within VREFH to AVSS. If any voltage
outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain.
The other analog input pins also are affected by that.
10.6.2 Analog input shared pins
The analog input pins (AN0 to AN15) are shared with input/output ports. When using any of the analog
inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary
to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other
pins may also be affected by noise arising from input/output to and from adjacent pins.
10.6.3 Noise Countermeasure
The internal equivalent circuit of the analog input pins is shown in Figure 10-5. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output
impedance of the signal source in your design is 5kΩ or less. Toshiba also recommends attaching a capacitor
external to the chip.
ANi
Internal resistance
4Mǡ6[R
Analog comparator
Permissible signal
source impedance
Mǡ/CZ
Internal capacitance
%R(
6[R
DA converter
PQVGKVQ
Figure 10-5
Analog Input Equivalent Circuit and Example of Input Pin Processing
Page 188
2007-10-15
TMP91FW60
11. Program Patch Logic
The TMP91FW60 has a program patch logic, which enables the user to fix the program code in the on-chip ROM
without generating a new mask. Patch program must be read into on-chip RAM from external memory during the
startup routine.
Up to six two-byte sequences, or banks (Twelve bytes in total) can be replaced with patch code. More significant
code correction can be performed by replacing program code with single-byte instruction code which generates a
software interrupt (SWI) to make a branch to a specified location in the on-chip RAM area.
The program patch logic only compares addresses in the on-chip ROM area; it cannot fix the program code in the
on-chip peripheral, on-chip RAM and external ROM areas.
Each of six banks is independently programmable, and functionally equivalent. In the following sections, any references to bank0 also apply to other banks.
11.1 Block Diagram
%27
41/
41/4&
41/4&
#FFTGUUDWU
$CPM
#FFTGUUEQORCTGTGIKUVGTU
41/%/2VQ41/%/2
1WVRWV
GPCDNG
1WVRWVEQPVTQNDNQEM
$CPM
#FFTGUUEQORCTGTGIKUVGTU
41/%/2VQ41/%/2
/CVEJ
UKIPCN
#FFTGUUEQORCTGDNQEM
$CPM
#FFTGUUEQORCTGTGIKUVGTU
41/%/2VQ41/%/2
$CPM
#FFTGUUEQORCTGTGIKUVGTU
41/%/2VQ41/%/2
$CPM
#FFTGUUEQORCTGTGIKUVGTU
41/%/2VQ41/%/2
$CPM
#FFTGUUEQORCTGTGIKUVGTU
41/%/2VQ41/%/2
&CVCDWU
$CPM
#FFTGUUUWDUVKVWVKQP
TGIKUVGTU
41/57$.*
$CPM
#FFTGUUUWDUVKVWVKQP
TGIKUVGTU
41/57$.*
$CPM
#FFTGUUUWDUVKVWVKQP
TGIKUVGTU
41/57$.*
$CPM
#FFTGUUUWDUVKVWVKQP
TGIKUVGTU
41/57$.*
$CPM
#FFTGUUUWDUVKVWVKQP
TGIKUVGTU
41/57$.*
$CPM
#FFTGUUUWDUVKVWVKQP
TGIKUVGTU
41/57$.*
Figure 11-1 Program Patch Logic Diagram
Page 189
2007-10-15
TMP91FW60
11.2 SFR Descriptions
The program patch logic consists of six banks (0 to 5). Each bank is provided with three bytes of address compare
registers (ROMCMPx0 to ROMCMPx2) and two bytes of address substitution registers (ROMSUBxL and ROMSUBxH).
Bank0 Address Compare Register 0
ROMCMP00
(0400H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
−
Read/Write
After reset
−
W
0
0
Function
0
0
0
0
0
−
−
Target ROM address (Lower 7 bits)
Bank0 Address Compare Register 1
ROMCMP01
(0401H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Middle 8 bits)
Bank0 Address Compare Register 2
ROMCMP02
(0402H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Upper 8 bits)
Bank0 Data Substitution Register L
ROMSUB0L
(0404H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Patch code (Lower 8 bits)
Bank0 Data Substitution Register H
ROMSUB0H
(0405H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
Read/Write
After reset
Function
W
0
0
0
0
Patch code (Upper 8 bits)
Note 1: The ROMCMP00/01/02, and ROMSUB0L/0H registers do not support read-modify-write operation.
Note 2: Bit0 of the Address Compare Register 0 is read as undefined.
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TMP91FW60
Bank1 Address Compare Register 0
ROMCMP10
(0408H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
−
Read/Write
After reset
−
W
0
0
Function
0
0
0
0
0
−
−
Target ROM address (Lower 7 bits)
Bank1 Address Compare Register 1
ROMCMP11
(0409H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Middle 8 bits)
Bank1 Address Compare Register 2
ROMCMP12
(040AH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Upper 8 bits)
Bank1 Data Substitution Register L
ROMSUB1L
(040CH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Patch code (Lower 8 bits)
Bank1 Data Substitution Register H
ROMSUB1H
(040DH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
Read/Write
After reset
Function
W
0
0
0
0
Patch code (Upper 8 bits)
Note 1: The ROMCMP10/11/12, and ROMSUB1L/1H registers do not support read-modify-write operation.
Note 2: Bit0 of the Address Compare Register 0 is read as undefined.
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TMP91FW60
Bank2 Address Compare Register 0
ROMCMP20
(0410H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
−
Read/Write
After reset
−
W
0
0
Function
0
0
0
0
0
−
−
Target ROM address (Lower 7 bits)
Bank2 Address Compare Register 1
ROMCMP21
(0411H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Middle 8 bits)
Bank2 Address Compare Register 2
ROMCMP22
(0412H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Upper 8 bits)
Bank2 Data Substitution Register L
ROMSUB2L
(0414H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Patch code (Lower 8 bits)
Bank2 Data Substitution Register H
ROMSUB2H
(0415H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
Read/Write
After reset
Function
W
0
0
0
0
Patch code (Upper 8 bits)
Note 1: The ROMCMP20/21/22, and ROMSUB2L/2H registers do not support read-modify-write operation.
Note 2: Bit0 of the Address Compare Register 0 is read as undefined.
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TMP91FW60
Bank3 Address Compare Register 0
ROMCMP30
(0418H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
−
Read/Write
After reset
−
W
0
0
Function
0
0
0
0
0
−
−
Target ROM address (Lower 7 bits)
Bank3 Address Compare Register 1
ROMCMP31
(0419H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Middle 8 bits)
Bank3 Address Compare Register 2
ROMCMP32
(041AH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Upper 8 bits)
Bank3 Data Substitution Register L
ROMSUB3L
(041CH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Patch code (Lower 8 bits)
Bank3 Data Substitution Register H
ROMSUB3H
(041DH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
Read/Write
After reset
Function
W
0
0
0
0
Patch code (Upper 8 bits)
Note 1: The ROMCMP30/31/32, and ROMSUB3L/3H registers do not support read-modify-write operation.
Note 2: Bit0 of the Address Compare Register 0 is read as undefined.
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TMP91FW60
Bank4 Address Compare Register 0
ROMCMP40
(0420H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
−
Read/Write
After reset
−
W
0
0
Function
0
0
0
0
0
−
−
Target ROM address (Lower 7 bits)
Bank4 Address Compare Register 1
ROMCMP41
(0421H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Middle 8 bits)
Bank4 Address Compare Register 2
ROMCMP42
(0422H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Upper 8 bits)
Bank4 Data Substitution Register L
ROMSUB4L
(0424H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Patch code (Lower 8 bits)
Bank4 Data Substitution Register H
ROMSUB4H
(0425H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
Read/Write
After reset
Function
W
0
0
0
0
Patch code (Upper 8 bits)
Note 1: The ROMCMP40/41/42, and ROMSUB4L/4H registers do not support read-modify-write operation.
Note 2: Bit0 of the Address Compare Register 0 is read as undefined.
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TMP91FW60
Bank5 Address Compare Register 0
ROMCMP50
(0428H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
−
Read/Write
After reset
−
W
0
0
Function
0
0
0
0
0
−
−
Target ROM address (Lower 7 bits)
Bank5 Address Compare Register 1
ROMCMP51
(0429H)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC15
ROMC14
ROMC13
ROMC12
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Middle 8 bits)
Bank5 Address Compare Register 2
ROMCMP52
(042AH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMC23
ROMC22
ROMC21
ROMC20
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Target ROM address (Upper 8 bits)
Bank5 Data Substitution Register L
ROMSUB5L
(042CH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS07
ROMS06
ROMS05
ROMS04
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
Read/Write
After reset
W
0
0
0
Function
0
Patch code (Lower 8 bits)
Bank5 Data Substitution Register H
ROMSUB5H
(042DH)
RMW
instructions
are prohibited.
Bit symbol
7
6
5
4
3
2
1
0
ROMS15
ROMS14
ROMS13
ROMS12
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
Read/Write
After reset
Function
W
0
0
0
0
Patch code (Upper 8 bits)
Note 1: The ROMCMP50/51/52, and ROMSUB5L/5H registers do not support read-modify-write operation.
Note 2: Bit0 of the Address Compare Register 0 is read as undefined.
Page 195
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TMP91FW60
11.3 Operation
11.3.1 Replacing data
Two consecutive bytes of data can be replaced for each bank. A two-byte sequence to be replaced must start
at an even address. If only a single byte at an even or odd address need be replaced, set the current masked
ROM data in the other byte.
Correction procedure:
Load the address compare registers (ROMCMP00 to ROMCMP02) with the target address where ROM data
need be replaced. Store 2-byte patch code in the ROMSUB0L and ROMSUB0H registers.
When the CPU address matches the value stored in the ROMCMP00 to ROMCMP02 registers, the program
patch logic disables RD output to the masked ROM and drives out the code stored in the ROMSUB0L and
ROMSUB0H to the internal bus. The CPU thus fetches the patch code.
The following shows some examples:
a. Replacing 00H at address FF1230H with AAH
ROMCMP00
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
Stores 30 in address compare register 0 for bank0.
ROMCMP01
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank0.
ROMCMP02
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank0.
ROMSUB0L
1
0
1
0
1
0
1
0
Store AA in address substitution register low for bank0.
ROMSUB0H
0
0
0
1
0
0
0
1
Store 11 in address substitution register high for bank0.
000000H
001000H
1PEJKR
RGTKRJGTCN
1PEJKR4#/
'ZVGTPCNCTGC
FE0000H
1PEJKR41/
C
FF1230H
00H
Replace with AAH
FF1231H
11H
Replace with 11H
(Same as current
value).
8GEVQTVCDNG
FFFFFFH
Figure 11-2 Example Patch Code Implementation
Page 196
2007-10-15
TMP91FW60
b. Replacing 33H at address FF1233H with BBH
7
6
5
4
3
2
1
0
ROMCMP00
0
0
1
1
0
0
1
0
Stores 32 in address compare register 0 for bank0.
ROMCMP01
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank0.
ROMCMP02
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank0.
ROMSUB0L
0
0
1
0
0
0
1
0
Store 22 in address substitution register low for bank0.
ROMSUB0H
1
0
1
1
1
0
1
1
Store BB in address substitution register high for bank0.
000000H
1PEJKR
RGTKRJGTCN
001000H
1PEJKR4#/
'ZVGTPCNCTGC
FE0000H
1PEJKR41/
D
FF1232H
00H
FF1233H
11H
Replace with 22H
(Same as current
value).
Replace with BBH
8GEVQTVCDNG
FFFFFFH
Figure 11-3 Example Patch Code Implementation
c. Replacing 44H at address FF1234H with CCH and 55H at address FF1235H with DDH
ROMCMP00
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
0
Stores 34 in address compare register 0 for bank0.
ROMCMP01
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank0.
ROMCMP02
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank0.
ROMSUB0L
1
1
0
0
1
1
0
0
Store CC in address substitution register low for bank0.
ROMSUB0H
1
1
0
1
1
1
0
1
Store DD in address substitution register high for bank0.
000000H
001000H
1PEJKR
RGTKRJGTCN
1PEJKR4#/
'ZVGTPCNCTGC
FE0000H
1PEJKR41/
E
FF1234H
00H
Replace with CCH
FF1235H
11H
Replace with DDH
8GEVQTVCDNG
FFFFFFH
Figure 11-4 Example Patch Code Implementation
Page 197
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TMP91FW60
d. Replacing 77H at address FF1237H with EEH and 88H at address FF1238H with FFH (Requiring two banks)
7
6
5
4
3
2
1
0
ROMCMP00
0
0
1
1
0
1
1
0
Stores 36 in address compare register 0 for bank0.
ROMCMP01
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank0.
ROMCMP02
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank0.
ROMSUB0L
0
1
1
0
0
1
1
0
Store 66 in address substitution register low for bank0.
ROMSUB0H
1
1
1
0
1
1
1
0
Store EE in address substitution register high for bank0.
ROMCMP10
0
0
1
1
1
0
0
0
Stores 38 in address compare register 0 for bank1.
ROMCMP11
0
0
0
1
0
0
1
0
Stores 12 in address compare register 1 for bank1.
ROMCMP12
1
1
1
1
1
1
1
1
Stores FF in address compare register 2 for bank1.
ROMSUB1L
1
1
1
1
1
1
1
1
Store FF in address substitution register low for bank1.
ROMSUB1H
1
0
0
1
1
0
0
1
Store 99 in address substitution register high for bank1.
000000H
001000H
1PEJKR
RGTKRJGTCN
1PEJKR4#/
'ZVGTPCNCTGC
FE0000H
1PEJKR41/
F
FF1236H
66H
FF1237H
FF1238H
77H
FF1239H
88H
99H
Replace with 66H
(Same as current
value).
Replace with EEH
Replace with FFH
Replace with 99H
(Same as current
value).
8GEVQTVCDNG
FFFFFFH
Figure 11-5 Example Patch Code Implementation
Page 198
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TMP91FW60
11.3.2 Using an interrupt to cause a branch
A wider range of program code can also be fixed using a software interrupt (SWI). With a patch code loaded
into on-chip RAM, the program patch logic can be used to replace program code at a specified address with a
single-byte SWI instruction, which causes a branch to the patch program.
Note that this method can only be used if the original masked ROM has been developed with on-chip RAM
addresses specified as SWI vector addresses.
Correction procedure:
Load the address compare registers (ROMCMP00 to ROMCMP02) with the start address of the program
code that is to be fixed. If it is an even address, store an SWI instruction code (e.g., SWI:F9H) in the ROMSUBL. If the start address is an odd address, store an SWI instruction code in the ROMSUBH and the current
ROM data at the preceding even address in the ROMSUBL.
When the CPU address matches the value stored in the ROMCMP00 to ROMCMP02 registers, the program
patch logic disables RD output to the masked ROM and drives out the SWI instruction code to the internal bus.
Upon fetching the SWI code, the CPU makes a branch to the internal RAM area to execute the preloaded code.
At the end of the patch program executed from the internal RAM, the CPU directly rewrites the saved PC
value so that it points to the address following the patch code, and then executes a RETI.
The following shows an example:
Example: Fixing a program within the range from FF5000H to FF507FH
Before developing the original masked ROM, set the SWI1 vector reference address to 001500H (onchip RAM area).
Use the startup routine to load the patch code to on-chip RAM (001500H to 0015EFH). Store the start
address (FF5000H) of the ROM area to be fixed in the ROMCMP00 to ROMCMP02. Store the SWI1
instruction code (F9H) in the ROMSUB0L and the current data at FF5001H (AAH) in the ROMSUB0H.
When the CPU address matches the value stored in ROMCMP00 to ROMCMP02, the program patch
logic replaces the ROM-based code at FF5000H with F9H. The CPU then executes the SWI1 instruction,
which causes a branch to 001500H in the on-chip RAM area. After executing the patch program the CPU
finally rewrites the saved PC value to FF5080H and executes a RETI.
Page 199
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TMP91FW60
*
*
*
'(*
1PEJKR
RGTKRJGTCN
2TQITCODQF[
࡮
࡮
࡮
࡮
4GYTKVGUVCEM
RETI
1PEJKR4#/
2CVEJ
RTQITCO
*
'(*
*
1PEJKR41/
((*
55H
((*
AAH
࡮
࡮
࡮
࡮
&GHGEVKXG
CTGC
(((*
((*
((((*
((((*
㨪
((((*
4GVWTPHTQO+06
('*
$TCPEJECWUGFD[59
'ZVGTPCNCTGC
Replace the start address with F9H
(SWI1 instruction code).
Replace with AAH
(Same as current value).
8GEVQTVCDNG
001500H
SW1 XGEVQT
Figure 11-6 Example ROM Correction
Page 200
2007-10-15
TMP91FW60
12. Watchdog Timer (Runaway detection timer)
The TMP91FW60 features a watchdog timer for detecting runaway.
The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to
malfunction (Runaway) due to causes such as noise.
When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU.
Connecting the watchdog timer output to the reset pin internally forces a reset.(The level of external RESET pin is
not changed)
12.1 Configuration
Figure 12-1 is a block diagram of he watchdog timer (WDT).
WDMOD
<RESCR>
RESET
Reset
control
Internal reset
INTWD interrupt reguest
WDMOD
<WDTP1:0>
Selector
215 217 219 221
fSYS
(fFPH/2)
Q
Binary counter
(22 stages)
R
S
Reset
Internal reset
Write
4EH
Write
B1H
WDMOD<WDTE>
WDT control register WDCR
Internal data bus
Figure 12-1 Block Diagram of Watchdog Timer
Note: It needs to care designing the total machine set, because watchdog timer can’t operate completely by external
noise.
Page 201
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TMP91FW60
12.2 Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has
elapsed. The watchdog timer must be cleared “0” by software before an INTWD interrupt will be generated. If the
CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to
clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated. The CPU will
detect malfunction (Runaway) due to the INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti-malfunction program.
The watchdog timer works immediately after reset.
The watchdog timer does not operate in IDLE1 or STOP mode. When the device is in IDLE2 mode, the operation
of WDT depends on the WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
The watchdog timer consists of a 22-stage binary counter which uses the system clock (fSYS) as the input clock.
The binary counter can output fSYS/215, fSYS/217, fSYS/219 and fSYS/221.
WDT counter
n
Overflow
0
WDT interrupt
Write clear code
WDT clear
(Software)
Figure 12-2 Normal Mode
The runaway is detected when an overflow occurs, and the watchdog timer can reset this device. In this case, the
reset time will be between 22 and 29 states (51.2 μs at fOSCH = 20 MHz) as shown in Figure 12-3. After a reset, the
fSYS clock (1 cycle = 1 state) is fFPH/2, where fFPH is generated by dividing the high-speed oscillator clock (fOSCH)
by sixteen through the clock gear function.
Overflow
WDT counter
n
WDT interrupt
Internal reset
(26.1 to 34.4
22 to 29 states
s at fOSCH = 27 MHz, fFPH = 1.7 MHz)
Figure 12-3 Reset Mode
Page 202
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TMP91FW60
12.3 Control Registers
The watchdog timer WDT is controlled by two control registers WDMOD and WDCR.
12.3.1 Watchdog timer mode register (WDMOD)
a. Setting the detection time for the watchdog timer in <WDTP1:0>
This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. After reset, this register is initialized to WDMOD<WDTP1:0> = “00”(215/ fSYS [S]).
b. Watchdog timer enable/disable control register <WDTE>
After reset, WDMOD<WDTE> is initialized to “1”, enabling the watchdog timer.
To disable the watchdog timer, it is necessary to set this bit to “0” and to write the disable code
(B1H) to the watchdog timer control register WDCR. This makes it difficult for the watchdog timer
to be disabled by runaway.
However, it is possible to return the watchdog timer from the disabled state to the enabled state
merely by setting <WDTE> to “1”.
c. Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the watchdog timer with the internal RESET. Since
WDMOD<RESCR> is initialized to “0” on reset, a reset by the watchdog timer will not be performed.
12.3.2 Watchdog timer control register (WDCR)
This register is used to disable and clear the binary counter for the watchdog timer.
• Disable control
The watchdog timer can be disabled by clearing WDMOD<WDTE> to “0” and then writing the
disable code (B1H) to the WDCR register.
WDMOD
←
0
–
–
X
X
–
–
0
Clear WDMOD<WDTE> to “0”.
WDCR
←
1
0
1
1
0
0
0
1
Write the disable code (B1H).
• Enable control
Set WDMOD<WDTE> to “1”.
• Watchdog timer clear control
To clear the binary counter and cause counting to resume, write the clear code (4EH) to the WDCR
register.
WDCR
←
0
1
0
0
1
1
1
Page 203
0
Write the clear code (4EH).
2007-10-15
TMP91FW60
Watchdog Timer Mode Register
WDMOD
(0300H)
7
6
Bit symbol
WDTE
WDTP1
Read/Write
R/W
After reset
1
5
4
3
2
WDTP0
–
–
I2WDT
–
–
–
–
R/W
0
0
1
0
RESCR
–
R/W
R/W
0
0
IDLE2
control
Reset
control
0
Select detecting time
00: 215/fSYS
Function
WDT control
1: Enable
01: 217/fSYS
10:
219/fSYS
Always write
“0”.
11: 221/fSYS
Watchdog timer out control
0
–
1
Connect WDT out to a internal reset
RESCR
IDLE2 control
0
Stop
1
Operation
I2WDT
Watchdog timer detection time
@fc = 20 MHz, fs = 32.768 kHz
Watchdog Timer Detection Time
SYSCR1
System Clock
Selection <SYSCK>
SYSCR1
Gear Value
<GEAR2:0>
00
01
10
11
1(fs)
xxx
2.0 s
8.0 s
32.0 s
128.0 s
000 (fc)
3.28 ms
13.11 ms
52.43 ms
209.72 ms
001 (fc/2)
6.55 ms
26.21 ms
104.86 ms
419.43 ms
WDMOD<WDTP1:0>
010(fc/4)
13.11 ms
52.43 ms
209.72 ms
838.86 ms
011 (fc/8)
26.21 ms
104.86 ms
419.43 ms
1677.72 ms
100 (fc/16)
52.43 ms
209.72 ms
838.86 ms
3355.44 ms
3
2
1
0(fc)
Watchdog timer enable/disable control
0
Disabled
1
Enabled
WDTE
Watchdog Timer Control Register
7
WDCR
(0301H)
RMW
instructions
are prohibited.
6
5
4
Bit symbol
-
Read/Write
W
After reset
-
0
B1H: WDT disable code
4EH: WDT clear code
Function
Disable/clear WDT
B1H
Disable code
4EH
Clear code
Others
Don’t care
Page 204
2007-10-15
TMP91FW60
13. Special timer for CLOCK
The TMP91FW60 includes a timer that is used for a clock operation.
An interrupt (INTRTC) can be generated each 0.0625 [s] or 0.125 [s] or 0.25 [s] or 0.50 [s] by using a low frequency clock of 32.768 kHz. A clock function can be easily used.
In addition, INTRTC can return from each standby mode except STOP mode.
A special timer for CLOCK can operate in all modes in which a low-frequency oscillation is operated.
The special timer for CLOCK is controlled by the special timer for CLOCK control register (RTCCR) as shown in.
13.1 Configuration
RTCCR<RTCSEL1:0>
Interrupt request
INTRTC
Selector
RTCCR<RTCRUN>
Run/
Clear
fs
(32.768 kHz)
211 212 213 214
14-stage binary counter
Figure 13-1 Block Diagram for Special Timer for CLOCK
Special Timer for CLOCK Control Register
RTCCR
(0310H)
7
6
5
4
3
2
1
0
Bit symbol
−
−
−
−
−
RTCSEL1
RTCSEL0
RTCRUN
Read/Write
R/W
−
−
−
−
After reset
0
−
−
−
−
R/W
0
00:
Function
Always write
“0”.
−
−
−
−
R/W
0
0
214/fs
01: 213/fs
12
10: 2 /fs
0: Stop &
clear
1: Count
11: 211/fs
Counting operation
0
Stop & clear
1
Count
<RTCRUN>
Interrupt generation cycle (fs = 32.768 kHz)
00
0.50 s
11
0.25 s
<RTCSEL1:0>
10
0.125 s
11
0.0625 s
Page 205
2007-10-15
TMP91FW60
14. Flash Memory
The TMP91FW60 incorporates flash memory that can be electrically erased and programmed using a single 5V
power supply.
The flash memory is programmed and erased using JEDEC-standard commands. After a program or erase command is input, the corresponding operation is automatically performed internally. Erase operations can be performed
by the entire chip (chip erase) or on a sector basis (sector erase).
The configuration and operations of the flash memory are described below.
14.1 Features
Power supply voltage for program/erase operations
- Vcc = 4.75 to 5.25 V
(TOPR = -10 to 40 °C, fc = 4 to 20MHz)
Configuration
- 64K × 16 bits (128 k bytes)
Functions
- Single-word programming
- Chip erase
- Sector erase
- Data polling / Toggle bit
Sector size
- 8Kbytes × 16
Mode control
- JEDEC-standard commands
Programming method
- On-board programming
- Parallel programmer
Security
- Write protection
- Read protection
14.2 Block Diagram
+PVGTPCNCFFTGUUDWU
+PVGTPCNFCVCDWU +PVGTPCNEQPVTQNDWU
OQFG
UGVVKPIRKP
OQFG
EQPVTQN
41/
%QPVTQN
EQPVTQNNGT
#FFTGUU
&CVC
(NCUJOGOQT[
#FFTGUUNCVEJ 4QYFGEQFGT %QPVTQN
EKTEWKV KPENWFKPI
CWVQOCVKE
UGSWGPEG
EQPVTQN
EKTEWKV
%QOOCPF
TGIKUVGT
&CVCNCVEJ %QNWOPFGEQFGT5GPUGCOR
(NCUJOGOQT[EGNNU -$ 'TCUGUGEVQTFGEQFGT
Figure 14-1 Block Diagram of Flash Memory Unit
Page 206
2007-10-15
TMP91FW60
14.3 Operation Modes
14.3.1 Overview
The following three types of operation modes are available to control program/erase operations on the flash
memory.
Table 14-1 Description of Operation Modes
Operation Mode Name
Single Chip mode
Normal mode
User Boot mode
Description
After reset release, the device starts up from the internal flash memory.
Single Chip mode is further divided into two modes: “Normal mode” is a mode in which user
application programs are executed, and “User Boot mode” is used to program the flash memory
on-board.
The means of switching between these two modes can be set by the user as desired. For example, it can be set so that Port 00 = '1' selects Normal mode and Port 00 = '0' selects User Boot
mode. The user must include a routine to handle mode switching in a user application program.
In this mode, the device starts up from a user application program.
In this mode, the flash memory can be programmed by a user-specified method.
Single Boot mode
After reset release, the device starts up from the internal boot ROM (mask ROM). The boot
ROM includes an algorithm which allows a program for programming/erasing the flash memory
on-board via a serial port to be transferred to the device's internal RAM. The transferred program is then executed in the internal RAM so that the flash memory can be programmed/erased
by receiving data from an external host and issuing program/erase commands.
Programmer mode
This mode enables the internal flash memory to be programmed/erased using a general-purpose programmer. For programmers that can be used, please contact your local Toshiba sales
representative.
Of the modes listed in Table 14-1, the internal flash memory can be programmed in User Boot mode, Single
Boot mode and Programmer mode.
The mode in which the flash memory can be programmed/erased while mounted on the user board is defined
as the on-board programming mode. Of the modes listed above, Single Boot mode and User Boot mode are
classified as on-board programming modes. Single Boot mode supports Toshiba's proprietary programming/
erase method using serial I/O. User Boot mode (within Single Chip mode) allows the flash memory to be programmed/erased by a user-specified method.
Programmer mode is provided with a read protect function which prohibits reading of ROM data. By
enabling the read protect function upon completion of programming, the user can protect ROM data from
being read by third parties.
Page 207
2007-10-15
TMP91FW60
The operation mode Single Chip mode, Single Boot mode or Programmer mode is determined during reset
by externally setting the input levels on the AM0, AM1 and BOOT (EMU0) pins.
Except in Programmer mode which is entered with RESET held at “0”, the CPU will start operating in the
selected mode after the reset state is released. Once the operation mode has been set, make sure that the input
levels on the mode setting pins are not changed during operation.Table 14-2 shows how to set each operation
mode, and Figure 14-2 shows a mode transition diagram.
Table 14-2 Operation Mode Pin Settings
Input pins
Operation Mode
RESET
(1)
BOOT(EMU0)
AM1
AM0
open
1
1
0
1
1
-
1
0
Single Chip mode (Normal or User Boot mode)
rising edge
(2)
Single Boot mode
(3)
Programmer mode
0
Note:Although EMU0 is an output pin, it becomes an input pin with pull-up resistor only during a reset. After a reset,
EMU0 operates as follows depending on the operation mode.
>Single chip mode : Output pin with pull-up resistor
>Single boot mode : Pull-up (Input gate is invalid, and output gate is in high impedance.)
2TQITCOOGT
OQFG
4GUGVUVCVG
QT
㧗 4'5'6 4'5'6
4'5'6
5KPINGEJKROQFG 5KPING$QQV
OQFG
0QTOCNOQFG 7UGT$QQV
OQFG
1PDQCTFRTQITCOOKPI
OQFG
5YKVEJKPIOGVJQF
VQDGUGVD[WUGT
Note: Numbers in ( ) correspond to the operation mode pin settings shown in Table 14-2.
Figure 14-2 Mode Transition Diagram
14.3.2 Reset Operation
To reset the device, hold the RESET input at “0” for at least 10 system clocks while the power supply voltage
is within the rated operating voltage range and the internal high-frequency oscillator is oscillating stably.
For details, refer to “Reset of CPU”.
Page 208
2007-10-15
TMP91FW60
14.3.3 Memory Map for Each Operation Mode
In this product, the memory map varies with operation mode. The memory map and sector address ranges for
each operation mode are shown below.
5KPING%JKROQFG
* * +PVGTPCN+1
+PVGTPCN
4#/ -$
5KPING$QQVOQFG
* * *
* +PVGTPCN
+1
+PVGTPCN
4#/ -$
+PVGTPCN
(NCUJ41/
-$ 'ZVGTPCNOGOQT[
* 'ZVGTPCNOGOQT[
* 2TQITCOOKPIOQFG
* ੍⚂
+PVGTPCN
ౝ⬿
(NCUJ41/
-$ (NCUJ41/
4GUGTXGF * 'ZVGTPCNOGOQT[
('* +PVGTPCN
(NCUJ41/
-$ ((((* +PVGTTWRVXGEVQT$
((((((* (((* +PVGTPCN$QQV41/
-$ ((((* ((((((* +PVGTTWRVXGEVQT$
((((((* Figure 14-3 Memory Map for Each Operation Mode
Page 209
2007-10-15
TMP91FW60
Table 14-3 Sector Address Ranges for Each Operation Mode
Single Chip Mode
Single Boot Mode
Sector-0
FE0000H to FE1FFFH
10000H to 11FFFH
Sector-1
FE2000H to FE3FFFH
12000H to 13FFFH
Sector-2
FE4000H to FE5FFFH
14000H to 15FFFH
Sector-3
FE6000H to FE7FFFH
16000H to 17FFFH
Sector-4
FE8000H to FE9FFFH
18000H to 19FFFH
Sector-5
FEA000H to FEBFFFH
1A000H to 1BFFFH
Sector-6
FEC000H to FEDFFFH
1C000H to 1DFFFH
Sector-7
FEE000H to FEFFFFH
1E000H to 1FFFFH
Sector-8
FF0000H to FF1FFFH
20000H to 21FFFH
Sector-9
FF2000H to FF3FFFH
22000H to 23FFFH
Sector-10
FF4000H to FF5FFFH
24000H to 25FFFH
Sector-11
FF6000H to FF7FFFH
26000H to 27FFFH
Sector-12
FF8000H to FF9FFFH
28000H to 29FFFH
Sector-13
FFA000H to FFBFFFH
2A000H to 2BFFFH
Sector-14
FFC000H to FFDFFFH
2C000H to 2DFFFH
Sector-15
FFE000H to FFFFFFH
2E000H to 2FFFFH
Page 210
2007-10-15
TMP91FW60
14.4 Single Boot Mode
In Single Boot mode, the internal boot ROM (mask ROM) is activated to transfer a program/erase routine (usercreated boot program) from an external source into the internal RAM. This program/erase routine is then used to program/erase the flash memory. In this mode, the internal boot ROM is mapped into an area containing the interrupt
vector table, in which the boot ROM program is executed. The flash memory is mapped into an address space different from the one into which the boot ROM is mapped (See Figure 14-3).
The device's SIO (SIO1) and the controller are connected to transfer the program/erase routine from the controller
to the device's internal RAM. This program/erase routine is then executed to program/erase the flash memory. The
program/erase routine is executed by sending commands and write data from the controller. The communications
protocol between the device and the controller is described later in this manual. Before the program/erase routine can
be transferred to the RAM, user password verification is performed to ensure the security of user ROM data. If the
password is not verified correctly, the RAM transfer operation cannot be performed. In Single Boot mode, disable
interrupts and use the interrupt request flags to check for an interrupt request.
Note: Do not change to another operation mode in the program/erase routine.
Page 211
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TMP91FW60
14.4.1 Using the program/erase algorithm in the internal boot ROM
(Step-1)Environment setup
Since the program/erase routine and write data are transferred via SIO (SIO1), connect the device's SIO
(SIO1) and the controller on the board. The user must prepare the program/erase routine (a) on the controller.
0GYWUGT
CRRNKECVKQP RTQITCO +1
C2TQITCOGTCUGTQWVKPG
6/2(9
$QQV41/
%QPVTQNNGT 5+1 (NCUJOGOQT[
1NFWUGTCRRNKECVKQP
RTQITCO QTGTCUGFUVCVG 4#/ (Step-2) Starting up the internal boot ROM
Release the reset with the relevant input pins set for entering Single Boot mode. When the internal boot
ROM starts up, the program/erase routine (a) is transferred from the controller to the internal RAM via SIO
according to the communications procedure for Single Boot mode. Before this can be carried out, the password
entered by the user is verified against the password written in the user application program. (If the flash memory has been erased, 12 bytes of “0xFF” are used as the password.)
0GYWUGT
CRRNKECVKQP RTQITCO C2TQITCOGTCUGTQWVKPG
+1
6/2(9
ψ4'5'6 $QQV41/
(NCUJOGOQT[
%QPVTQNNGT 5+1 1NFWUGTCRRNKECVKQP
RTQITCO QTGTCUGFUVCVG
%QPFKVKQPHQT GPVGTKPI5KPING
$QQVOQFG
4#/ Page 212
2007-10-15
TMP91FW60
(Step-3) Copying the program/erase routine to the RAM
After password verification is completed, the boot ROM copies the program/erase routine (a) from the controller to the RAM using serial communications. The program/erase routine must be stored within the RAM
address range of 001000H to 002DFFH.
0GYWUGT
CRRNKECVKQP RTQITCO +1
C2TQITCOGTCUGTQWVKPG
6/2(9
%QPVTQNNGT $QQV41/ 5+1 (NCUJOGOQT[
1NFWUGTCRRNKECVKQP
RTQITCO
QTGTCUGFUVCVG
C2TQITCOGTCUGTQWVKPG
4#/ (Step-4) Executing the program/erase routine in the RAM
Control jumps to the program/erase routine (a) in the RAM. If necessary, the old user application program is
erased (sector erase or chip erase).
Note 1: The boot ROM is provided with an erase command, which enables the entire chip to be erased from the
controller without using the program/erase routine.
Note 2: If it is necessary to erase data on a sector basis, incorporate the necessary code in the program/erase routine.
0GYWUGT
CRRNKECVKQP RTQITCO +1
6/2(9 $QQV41/
(NCUJOGOQT[
C2TQITCOGTCUGTQWVKPG
5+1 %QPVTQNNGT C2TQITCOGTCUGTQWVKPG
'TCUGF
4#/ Page 213
2007-10-15
TMP91FW60
(Step-5) Copying the new user application program
The program/erase routine (a) loads the new user application program from the controller into the erased area
of the flash memory.
In the example below, the new user application program is transferred under the same communications conditions as those used for transferring the program/erase routine. However, after the program/erase routine has
been transferred, this routine can be used to change the transfer settings (data bus and transfer source). Configure the board hardware and program/erase routine as desired.
0GYWUGT
CRRNKECVKQP
RTQITCO
+1
C2TQITCOGTCUGTQWVKPG
6/2(9
$QQV41/ (NCUJOGOQT[
%QPVTQNNGT 5+1 0GYWUGTCRRNKECVKQP
RTQITCO
C2TQITCOGTCUGTQWVKPG
4#/ (Step-6) Executing the new user application program
After the programming operation has been completed, turn off the power to the board and remove the cable
connecting the device and the controller. Then, turn on the power again and start up the device in Single Chip
mode to execute the new user application program.
6/2(9 ψ4'5'6 $QQV41/ 5+1 %QPVTQNNGT (NCUJOGOQT[
0GYWUGTCRRNKECVKQP
RTQITCO
4#/ Page 214
%QPFKVKQPHQT GPVGTKPI5KPING
%JKROQFG
0QTOCNOQFG
2007-10-15
TMP91FW60
14.4.2 Connection Examples for Single Boot Mode
In Single Boot mode the flash memory is programmed by serial transfer. Therefore, on-board programming
is performed by connecting the device's SIO (SIO1) and the controller (programming tool) and sending commands from the controller to the device. Figure 14-4 shows an example of connection between the target board
and a programming controller. Figure 14-5 shows an example of connection between the target board and an
RS232C board.
1P$QCTF2TQITCOOKPI%QPVTQNNGT
2QYGT
UWRRN[
4GI
8%%
6CTIGV$QCTF
8%% 8%%
6/2(9
&8%%
#/
#/
/QFGEQPVTQN
/%7
2TQITCO
EQPVTQNNGT
/QFGEQPVTQN
6CTIGVDQCTF
QRGTCVKQP
4'5'6
$116
4'5'6
$QQV
OQFG
UYKVEJKPI
EKTEWKV
$116
'/7
4#/
41/
2
2
4:&
45%
6:&
2
2
4:&
2
6:&
2
855
&855
2%
Figure 14-4 Example of Connection with an External Controller in Single Boot Mode
Page 215
2007-10-15
TMP91FW60
45%
8%%
2QYGT
UWRRN[
$QCTF
6CTIGV$QCTF
8%% 8%%
6/2(9
&8%%
#/
#/
4'5'6
$116
4:&
45%
6:&
4'5'6
$QQV
OQFG
UYKVEJKPI
EKTEWKV
$116
'/7
4:&
2
6:&
2
855
855
&855
2%
Figure 14-5 Example of Connection with an RS232C Board in Single Boot Mode
Page 216
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TMP91FW60
14.4.3 Mode Setting
To perform on-board programming, the device must be started up in Single Boot mode by setting the input
pins as shown below.
AM0,AM1= 1
BOOT = 0
RESET= 0 → 1
Set the AM0, AM1, and BOOT pins as shown above with the RESET pin held at “0”. Then, setting the
RESET pin to “1” will start up the device in Single Boot mode.
14.4.4 Memory Maps
Figure 14-6 shows a comparison of the memory map for Normal mode (in Single Chip mode) and the memory map for Single Boot mode. In Single Boot mode, the flash memory is mapped to addresses 10000H to
2FFFFH (physical addresses) and the boot ROM (mask ROM) is mapped to addresses FFF000H to FFFFFFH.
5KPING%JKROQFG
000000H
001000H
5KPING$QQVOQFG
000000H
Internal I/O
001000H
Internal RAM
8KB
Internal I/O
Internal RAM
8KB
003000H
003000H
External
Memory
010000H
External
Memory
(੍⚂)
Internalౝ⬿
Flash ROM
128KB
Flash ROM
030000H
External
Memory
FE0000H
FFFF00H
FFFFFFH
Internal Flash ROM
128KB
FFF000H
(Interrupt vector 256B)
FFFF00H
FFFFFFH
Internal Boot ROM 4KB
(Interrupt vector 256B)
Figure 14-6 Comparison of Memory Maps
Page 217
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TMP91FW60
14.4.5 Interface Specifications
The SIO communications format in Single Boot mode is shown below. The device supports the UART (asynchronous communications) serial operation mode.
To perform on-board programming, the same communications format must also be set on the programming
controller's side.
UART (asynchronous) communications
- Communications channel
: SIO channel 1(For the pins be used, see Table 14-4)
- Serial transfer mode
: UART (asynchronous communications) mode
- Data length
: 8 bits
- Parity bit
: None
- STOP bit
: 1 bit
- Baud rate
: See Table 14-5, Table 14-6
Table 14-4 Pin Connections
Pins
UART
Power supply pins
DVCC
Ο
DVSS
Ο
Mode setting pins
AM1,AM0
BOOT
Ο
Reset pin
RESET
Ο
Communications pins
TXD1
Ο
RXD1
Ο
Note: Unused pins are in the initial state after reset release.
Table 14-5 Baud Rate Table
SIO
UART
Transfer Rate (bps)
115200
57600
Page 218
38400
19200
9600
2007-10-15
TMP91FW60
+1.73
39063
+1.73
19531
9766
19.37 to 20.05
20
+1.73
0
57600
0
19200
9600
18.16 to 18.80
18.4320
0
+0.16
19231
9615
15.74 to 16.29
16
+0.16
0
115200
0
57600
0
38400
0
19200
9600
14.53 to 15.04
14.7456
0
0
38400
0
19200
9600
12.11 to 12.53
12.288
0
0
19200
0
9600
10.90 to 11.28
11.0592
+1.73
39063
+1.73
19531
9766
9.69 to 10.02
10
+1.73
9615
7.87 to 8.14
8
+0.16
Baud Rate
(bps)
Baud Rate
(bps)
Baud Rate
(bps)
Baud Rate
(bps)
Baud Rate
(bps)
Supported
Range
(MHz)
Reference
Frequency
(MHz)
Reference Baud Rate (bps)
9600
Error
(%)
19200
Error
(%)
38400
Error
(%)
57600
Error
(%)
115200
Error
(%)
Table 14-6 Correspondence between Operating Frequency and Baud Rate in Single Boot
Mode
Reference frequency:
The frequency of the high-speed oscillation circuit that can be used in Single Boot mode.
To program the flash memory using Single Boot mode, one of the reference frequencies must be
selected as a high-speed clock.
Supported Range:
The range of clock frequencies that are detected as each reference frequency. It may not be possible to
perform Single Boot operations at clock frequencies outside of the supported range.
Note:To automatically detect the reference frequency (microcontroller clock frequency), the transfer baud rate error
of the flash memory programming controller and the oscillation frequency error must be within −1.5%, +2% in
total.
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14.4.6 Data Transfer Formats
Table 14-7 to Table 14-12 show the operation command data and the data transfer format for each operation
mode.
Table 14-7 Operation Command Data
Operation Command Data
Operation Mode
10H
RAM Transfer
20H
Flash Memory SUM
30H
Product Information Read
40H
Flash Memory Chip Erase
60H
Flash Memory Protect Set
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Table 14-8 Transfer Format of Single Boot Program [RAM Transfer]
Transfer Byte
Number
BOOT ROM
1st byte
2nd byte
3rd byte
4th byte
Transfer Data
from Controller to Device
Baud Rate
Desired
Baud rate setting
UART
86H
baud rate#1
Transfer Data
from Device to Controller
ACK response to baud rate setting
Normal (baud rate OK)
>UART
86H
(If the desired baud rate cannot be set,
operation is terminated.)
-
Operation command data
(10H)
ACK response to operation command#2
Normal
10H
Error
x1H
-
Protection applied#3
Communications error
5th byte
to
16th byte
PASSWORD data (12 bytes)
17th byte
CHECKSUM value for 5th to 16th bytes
x6H
x8H
(02FEF4H to 02FEFFH)
ACK response to CHECKSUM value#2
RAM
#1
#2
#3
#4
Normal
Error
Communications error
18th byte
-
19th byte
RAM storage start address 31 to 24 #4
-
20th byte
RAM storage start address 23 to 16#4
-
21th byte
RAM storage start address 15 to 8#4
-
22th byte
RAM storage start address 7 to 0#4
-
23th byte
RAM storage byte count 15 to 8#4
-
24th byte
RAM storage byte count 7 to 0#4
-
25th byte
CHECKSUM value for 19th to 24th bytes #4
-
10H
11H
18H
ACK response to CHECKSUM value#2
Normal
10H
Error
11H
Communications error
18H
26th byte
-
27th byte
to
(m)th byte
RAM storage data
-
(m+1)th byte
CHECKSUM value for 27th to m'th bytes
-
(m+2)th byte
-
ACK response to CHECKSUM value#2
Normal
10H
Error
11H
Communications error
18H
(m+3)th byte
-
JUMP to RAM storage start address
For the desired baud rate setting, see Table 14-6.
After sending an error response, the device waits for operation command data (3rd byte).
When read protection or write protection is applied, the device aborts the received operation command and waits for the next
operation command data (3rd byte).
The data to be transferred in the 19th to 25th bytes should be programmed within the RAM address range of 001000H to
002DFFH (7.5 Kbytes).
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Table 14-9 Transfer Format of Single Boot Program [Flash Memory SUM]
Transfer Byte
Number
BOOT ROM
1st byte
2nd byte
3rd byte
#1
#2
Transfer Data
from Controller to Device
Baud Rate
Desired
Baud rate setting
UART
86H
-
baud rate#1
ACK response to baud rate setting
Normal (baud rate OK)
>UART
86H
(If the desired baud rate cannot be set,
operation is terminated.)
-
Operation command data
Transfer Data
from Device to Controller
(20H)
-
4th byte
-
ACK response to CHECKSUM value#2
Normal
20H
Error
x1H
Communications error
x8H
5th byte
-
SUM (upper)
6th byte
-
SUM (lower)
7th byte
-
CHECKSUM value for 5th and 6th bytes
8th byte
(Wait for the next operation command data)
-
For the desired baud rate setting, see Table 14-6.
After sending an error response, the device waits for operation command data (3rd byte).
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TMP91FW60
Table 14-10 Transfer Format of Single Boot Program [Product Information Read](1/2)
Transfer Byte
Number
BOOT ROM
1st byte
2nd byte
3rd byte
Transfer Data
from Controller to Device
Baud Rate
Desired
Baud rate setting
UART
86H
ACK response to baud rate setting Normal
(baud rate OK)
>UART
86H
(If the desired baud rate cannot be set,
operation is terminated.)
-
Operation command data
baud rate#1
Transfer Data
from Device to Controller
(30H)
-
4th byte
-
ACK response to operation command#2
Normal
30H
Error
x1H
Communications
x8H
5th byte
-
Flash memory data (address 02FEF0H)
6th byte
-
Flash memory data (address 02FEF1H)
7th byte
-
Flash memory data (address 02FEF2H)
8th byte
-
Flash memory data (address 02FEF3H)
9th byte
to
20th byte
-
21th byte
to
24th byte
-
Password comparison start address
(4 bytes)
F4H, FEH, 02H, 00H (from 21st byte)
25th byte
to
28th byte
-
RAM start address (4 bytes)
00H, 10H, 00H, 00H (from 25th byte)
29th byte
to
32th byte
-
RAM (user area) end address (4 bytes)
FFH, 2DH, 00H, 00H (from 29th byte)
33th byte
to
36th byte
-
RAM end address (4 bytes)
FFH, 2FH, 00H, 00H (from 33rd byte)
37th byte
to
40th byte
-
Dummy data (4 bytes)
00H,00H,00H,00H (from 37th byte)
41th byte
to
44th byte
-
Dummy data (4 bytes)
00H, 00H, 00H, 00H (from 41st byte)
45th byte
to
46th byte
-
FUSE information (2 bytes from 45th byte)
Read protection/Write protection
1) Applied/Applied
: 00H, 00H
2) Not applied/Applied
: 01H, 00H
3) Applied/Not applied
: 02H, 00H
4) Not applied/Not applied : 03H, 00H
47th byte
to
50th byte
-
Flash memory start address (4 bytes)
00H, 00H, 01H, 00H (from 47th byte)
51th byte
to
54th byte
-
Flash memory end address (4 bytes)
FFH, FFH, 02H, 00H (from 51st byte)
55th byte
to
56th byte
-
Number of sectors in flash memory (2
bytes)
10H, 00H (from 55th byte)
57th byte
to
60th byte
-
Start address of flash memory sectors of the
same size (4 bytes)
00H, 00H, 01H, 00H (from 57th byte)
Part number (ASCII code, 12 bytes)
'TMP91FW60 _ _ _ ' (from 9th byte)
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TMP91FW60
Table 14-10 Transfer Format of Single Boot Program [Product Information Read](2/2)
Transfer Data
from Controller to Device
61th byte
to
64th byte
-
Size (in half words) of flash memory sectors
of the same size (4 bytes)
00H, 10H, 00H, 00H (from 61st byte)
65th byte
-
Number of flash memory sectors of the
same size (1 byte)
10H
66th byte
-
CHECKSUM value for 5th to 65th bytes
67th byte
#1
#2
Transfer Data
from Device to Controller
Transfer Byte
Number
Baud Rate
(Wait for the next operation command
data)
-
For the desired baud rate setting, see Table 14-6.
After sending an error response, the device waits for operation command data (3rd byte).
Table 14-11 Transfer Format of Single Boot Program [Flash Memory Chip Erase]
Transfer Byte
Number
BOOT ROM
1st byte
2nd byte
3rd byte
4th byte
5th byte
Transfer Data
from Device to Controller
Baud Rate
Desired
Baud rate setting
UART
86H
-
baud rate#1
ACK response to baud rate setting
Normal (baud rate OK)
>UART
86H
(If the desired baud rate cannot be set,
operation is terminated.)
-
Operation command data
(40H)
ACK response to operation command#2
Normal
40H
Error
x1H
Communications
x8H
-
Erase Enable command data
(54H)
-
6th byte
-
ACK response to operation command#2
Normal
54H
Error
x1H
Communications
x8H
7th byte
-
ACK response to Erase command
Normal
4FH
Error
4CH
8th byte
-
ACK response
Normal
Error
9th byte
#1
#2
Transfer Data
from Controller to Device
(Wait for the next operation command
data)
5DH
60H
-
For the desired baud rate setting, see Table 14-6.
After sending an error response, the device waits for operation command data (3rd byte).
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TMP91FW60
Table 14-12 Transfer Format of Single Boot Program [Flash Memory Protect Set]
Transfer Byte
Number
BOOT ROM
1st byte
2nd byte
3rd byte
Transfer Data
from Device to Controller
Baud Rate
Desired
Baud rate setting
UART
86H
-
baud rate#1
ACK response to baud rate setting
Normal (baud rate OK)
>UART
86H
(If the desired baud rate cannot be set,
operation is terminated.)
-
Operation command data
(60H)
ACK response to operation command#2
Normal
60H
Error
x1H
Communications
x8H
4th byte
-
5th byte
to
16th byte
Password data (12 bytes)
17th byte
CHECKSUM value for 5th to 16th bytes
(02FEF4H to 02FEFFH)
-
18th byte
-
ACK response to checksum value#2
Normal
60H
Error
61H
Communications
68H
19th byte
-
ACK response to Protect Set command
Normal
6FH
Error
6CH
20th byte
-
ACK response
Normal
Error
21th byte
#1
#2
Transfer Data
from Controller to Device
(Wait for the next operation command
data)
31H
34H
-
For the desired baud rate setting, see Table 14-6.
After sending an error response, the device waits for operation command data (3rd byte).
Page 225
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TMP91FW60
14.4.7 Boot Program
When the device starts up in Single Boot mode, the boot program is activated.
The following explains the commands that are used in the boot program to communicate with the controller
when the device starts up in Single Boot mode. Use this information for creating a controller for using Single
Boot mode or for building a user boot environment.
1. RAM Transfer command
In RAM transfer, data is transferred from the controller and stored in the device's internal RAM.
When the transfer completes normally, the boot program will start running the transferred user program. Up to 7.5 Kbytes of data can be transferred as a user program. (This limit is implemented in
the boot program to protect the stack pointer area.) The user program starts executing from the RAM
storage start address.
This RAM transfer function enables a user-created program/erase routine to be executed, allowing
the user to implement their own on-board programming method. To perform on-board programming
with a user program, the flash memory command sequences (see section 14.6) must be used. After
the RAM Transfer command has been completed, the entire internal RAM area can be used.
If read protection or write protection is applied on the device or a password error occurs, this command will not be executed.
2. Flash Memory SUM command
This command calculates the SUM of 128 Kbytes of data in the flash memory and returns the
result. There is no operation command available to the boot program for reading data from the entire
area of the flash memory. Instead, this Flash Memory SUM command can be used. Reading the SUM
value enables revision management of the application program.
3. Product Information Read command
This command returns the information about the device including its part number and memory
details stored in the flash memory at addresses 02FEF0H to 02FEF3H. This command can also be
used for revision management of the application program.
4. Flash Memory Chip Erase command
This command erases all the sectors in the flash memory. If read protection or write protection is
applied on the device, all the sectors in the flash memory are erased and the read protection or write
protection is cleared.
Since this command is also used to restore the operation of the boot program when the password is
forgotten, it does not include password verification.
5. Flash Memory Protect Set command
This command sets both read protection and write protection on the device. However, if a password error occurs, this command will not be executed.
When read protection is set, the flash memory cannot be read in Programmer mode. When write
protection is set, the flash memory cannot be written in Programmer mode.
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TMP91FW60
14.4.8 RAM Transfer Command
See Table 14-8.
1. From the controller to the device
The data in the 1st byte is used to determine the baud rate. The 1st byte is transferred with receive
operation disabled (SC1MOD0<RXE> = 0). (The baud rate is determined using an internal timer.)
To communicate in UART mode
Send the value 86H from the controller to the target board using UART settings at the desired
baud rate. If the serial operation mode is determined as UART, the device checks to see
whether or not the desired baud rate can be set. If the device determines that the desired baud
rate cannot be set, operation is terminated and no communications can be established.
2. From the device to the controller
The data in the 2nd byte is the ACK response returned by the device for the serial operation mode
setting data sent in the 1st byte. If the data in the 1st byte is found to signify UART and the desired
baud rate can be set, the device returns 86H.
Baud rate determination
The device determines whether or not the desired baud rate can be set. If it is found that the
baud rate can be set, the boot program rewrites the BR1CR and BR1ADD values and returns
86H. If it is found that the desired baud rate cannot be set, operation is terminated and no data
is returned. The controller sets a time-out time (5 seconds) after it has finished sending the
1st byte. If the controller does not receive the response (86H) normally within the time-out
time, it should be considered that the device is unable to communicate. Receive operation is
enabled (SC1MOD0<RXE> = 1) before 86H is written to the transmission buffer.
3. From the controller to the device
The data in the 3rd byte is operation command data. In this case, the RAM Transfer command data
(10H) is sent from the controller to the device.
4. From the device to the controller
The data in the 4th byte is the ACK response to the operation command data in the 3rd byte. First,
the device checks to see if the received data in the 3rd byte contains any error. If a receive error is
found, the device returns the ACK response data for communications error (bit 3) x8H and waits for
the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined (They are the upper four bits of the immediately preceding operation command data).
Next, if the data received in the 3rd byte corresponds to one of the operation commands given in
Table 14-7, the device echoes back the received data (ACK response for normal reception). In the
case of the RAM Transfer command, if read or write protection is not applied, 10H is echoed back
and then execution branches to the RAM transfer processing routine. If protection is applied, the
device returns the corresponding ACK response data (bit 2/1) x6H and waits for the next operation
command data (3rd byte). The upper four bits of the ACK response data are undefined. (They are the
upper four bits of the immediately preceding operation command data.)
After branching to the RAM transfer processing routine, the device checks the data in the password
area. For details, see " 14.4.15 Password ".
If the data in the 3rd byte does not correspond to any operation command, the device returns the
ACK response data for operation command error (bit0) x1H and waits for the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined. (They are the
upper four bits of the immediately preceding operation command data.)
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TMP91FW60
5. From the controller to the device
The 5th to 16th bytes contain password data (12 bytes). The data in the 5th to 16th bytes is verified
against the data at addresses 02FEF4H to 02FEFFH in the flash memory, respectively.
6. From the controller to the device
The 17th byte contains CHECKSUM data. The CHECKSUM data sent by the controller is the
two's complement of the lower 8-bit value obtained by summing the data in the 5th to 16th bytes by
unsigned 8-bit addition (ignoring any overflow). For details on CHECKSUM, see " 14.4.17 How to
Calculate CHECKSUM ".
7. From the device to the controller
The data in the 18th byte is the ACK response data to the 5th to 17th bytes (ACK response to the
CHECKSUM value). The device first checks to see whether the data received in the 5th to 17th bytes
contains any error. If a receive error is found, the device returns the ACK response data for communications error (bit 3) 18H and waits for the next operation command data (3rd byte). The upper four
bits of the ACK response data are the upper four bits of the immediately preceding operation command data, so the value of these bits is “1”.
Next, the device checks the CHECKSUM data in the 17th byte. This check is made to see if the
lower 8-bit value obtained by summing the data in the 5th to 17th bytes by unsigned 8-bit addition
(ignoring any overflow) is 00H. If the value is not 00H, the device returns the ACK response data for
CHECKSUM error (bit 0) 11H and waits for the next operation command data (3rd byte).
Finally, the device examines the result of password verification. If all the data in the 5th to 16th
bytes is not verified correctly, the device returns the ACK response data for password error (bit 0)
11H and waits for the next operation command data (3rd byte).
If no error is found in all the above checks, the device returns the ACK response data for normal
reception 10 H.
8. From the controller to the device
The data in the 19th to 22nd bytes indicates the RAM start address for storing block transfer data.
The 19th byte corresponds to address bits 31 to 24, the 20th byte to address bits 23 to 16, the 21st
byte to address bits 15 to 8, and the 22nd byte to address bits 7 to 0.
9. From the controller to the device
The data in the 23rd and 24th bytes indicates the number of bytes to be transferred. The 23rd byte
corresponds to bits 15 to 8 of the transfer byte count and the 24th byte corresponds to bits 7 to 0.
10. From the controller to the device
The data in the 25th byte is CHECKSUM data. The CHECKSUM data sent by the controller is the
two's complement of the lower 8-bit value obtained by summing the data in the 19th to 24th bytes by
unsigned 8-bit addition (ignoring any overflow). For details on CHECKSUM, see " 14.4.17 How to
Calculate CHECKSUM ".
Note: The data in the 19th to 25th bytes should be placed within addresses 001000H to 002DFFH (7.5Kbytes) in
the internal RAM.
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11. From the device to the controller
The data in the 26th byte is the ACK response data to the data in the 19th to 25th bytes (ACK
response to the CHECKSUM value).
The device first checks to see whether the data received in the 19th to 25th bytes contains any
error. If a receive error is found, the device returns the ACK response data for communications error
(bit 3) 18H and waits for the next operation command (3rd byte). The upper four bits of the ACK
response data are the upper four bits of the immediately preceding operation command data, so the
value of these bits is “1”.
Next, the device checks the CHECKSUM data in the 25th byte. This check is made to see if the
lower 8-bit value obtained by summing the data in the 19th to 25th bytes by unsigned 8-bit addition
(ignoring any overflow) is 00H. If the value is not 00H, the device returns the ACK response data for
CHECKSUM error (bit 0) 11H and waits for the next operation command data (3rd byte).
12. From the controller to the device
The data in the 27th to m'th bytes is the data to be stored in the RAM. This data is written to the
RAM starting at the address specified in the 19th to 22nd bytes. The number of bytes to be written is
specified in the 23rd and 24th bytes.
13. From the controller to the device
The data in the (m+1)th byte is CHECKSUM data. The CHECKSUM data sent by the controller is
the two's complement of the lower 8-bit value obtained by summing the data in the 27th to m'th bytes
by unsigned 8-bit addition (ignoring any overflow). For details on CHECKSUM, see " 14.4.17 How
to Calculate CHECKSUM ".
14. From the device to the controller
The data in the (m+2)th byte is the ACK response data to the 27th to (m+1)th bytes (ACK response
to the CHECKSUM value).
The device first checks to see whether the data in the 27th to (m+1)th byte contains any error. If a
receive error is found, the device returns the ACK response data for communications error (bit 3)
18H and waits for the next operation command (3rd byte). The upper four bits of the ACK response
are the upper four bits of the immediately preceding operation command data, so the value of these
bits is “1”.
Next, the device checks the CHECKSUM data in the (m+1)th byte. This check is made to see if the
lower 8-bit value obtained by summing the data in the 27th to (m+1)th bytes by unsigned 8-bit addition (ignoring any overflow) is 00H. If the value is not 00H, the device returns the ACK response
data for CHECKSUM error (bit 0) 11H and waits for the next operation command data (3rd byte).
If no error is found in all the above checks, the device returns the ACK response data for normal
reception 10H.
15. From the device to the controller
If the ACK response data in the (m+2)th byte is 10H (normal reception), the boot program then
jumps to the RAM start address specified in the 19th to 22nd bytes.
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14.4.9 Flash Memory SUM command
See Table 14-9.
1. The data in the 1st and 2nd bytes is the same as in the case of the RAM Transfer command.
2. From the controller to the device
The data in the 3rd byte is operation command data. The Flash Memory SUM command data
(20H) is sent here.
3. From the device to the controller
The data in the 4th byte is the ACK response data to the operation command data in the 3rd byte.
The device first checks to see if the data in the 3rd byte contains any error. If a receive error is
found, the device returns the ACK response data for communications error (bit 3) x8H and waits for
the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined. (They are the upper four bits of the immediately preceding operation command data.)
Then, if the data in the 3rd byte corresponds to one of the operation command values given in
Table 14-7, the device echoes back the received data (ACK response for normal reception). In this
case, 20H is echoed back and execution then branches to the flash memory SUM processing routine.
If the data in the 3rd byte does not correspond to any operation command, the device returns the
ACK response data for operation command error (bit 0) x1H and waits for the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined. (They are the
upper four bits of the immediately preceding operation command data.)
4. From the device to the controller
The data in the 5th and 6th bytes is the upper and lower data of the SUM value, respectively. For
details on SUM, see " 14.4.16 How to Calculate SUM ".
5. From the device to the controller
The data in the 7th byte is CHECKSUM data. This is the two's complement of the lower 8-bit
value obtained by summing the data in the 5th and 6th bytes by unsigned 8-bit addition (ignoring any
overflow).
6. From the controller to the device
The data in the 8th byte is the next operation command data.
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14.4.10Product Information Read command
See Table 14-10.
1. The data in the 1st and 2nd bytes is the same as in the case of the RAM Transfer command.
2. From the controller to the device
The data in the 3rd byte is operation command data. The Product Information Read command data
(30H) is sent here.
3. From the device to the controller
The data in the 4th byte is the ACK response data to the operation command data in the 3rd byte.
The device first checks to see if the data in the 3rd byte contains any error. If a receive error is
found, the device returns the ACK response data for communications error (bit 3) x8H and waits for
the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined. (They are the upper four bits of the immediately preceding operation command data.)
Then, if the data in the 3rd byte corresponds to one of the operation command values given in
Table 14-7, the device echoes back the received data (ACK response for normal reception). In this
case, 30H is returned and execution then branches to the product information read processing routine. If the data in the 3rd byte does not correspond to any operation command, the device returns the
ACK response data for operation command error (bit 0) x1H and waits for the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined. (They are the
upper four bits of the immediately preceding operation command data.)
4. From the device to the controller
The data in the 5th to 8th bytes is the data stored at addresses 02FEF0H to 02FEF3H in the flash
memory. By writing the ID information of software at these addresses, the version of the software
can be managed. (For example, 0002H can indicate that the software is now in version 2.)
5. From the device to the controller
The data in the 9th to 20th bytes denotes the part number of the device. 'TMP91FW60 _ _ _ ' is sent
in ASCII code starting from the 9th byte.
Note: An underscore ('_') indicates a space.
6. From the device to the controller
The data in the 21st to 24th bytes is the password comparison start address. F4H, FEH, 02H and
00H are sent starting from the 21st byte.
7. From the device to the controller
The data in the 25th to 28th bytes is the RAM start address. 00H, 10H, 00H and 00H are sent starting from the 25th byte.
8. From the device to the controller
The data in the 29th to 32nd bytes is the RAM (user area) end address. FFH, 2DH, 00H and 00H
are sent starting from the 29th byte.
9. From the device to the controller
The data in the 33rd to 36th bytes is the RAM end address. FFH, 2FH, 00H and 00H are sent starting from the 33rd byte.
10. From the device to the controller
The data in the 37th to 44th bytes is dummy data.
11. From the device to the controller
The data in the 45th and 46th bytes contains the protection status and sector division information
of the flash memory.
>Bit 0 indicates the read protection status.
0: Read protection is applied.
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1: Read protection is not applied.
>Bit 1 indicates the write protection status.
0: Write protection is applied.
1: Write protection is not applied.
>Bit 2 indicates whether or not the flash memory is divided into sectors.
0: The flash memory is divided into sectors.
1: The flash memory is not divided into sectors.
>Bits 3 to 15 are sent as “0”.
12. From the device to the controller
The data in the 47th to 50th bytes is the flash memory start address. 00H, 00H, 01H and 00H are
sent starting from the 47th byte.
13. From the device to the controller
The data in the 51st to 54th bytes is the flash memory end address. FFH, FFH, 02H and 00H are
sent starting from the 51st byte.
14. From the device to the controller
The data in the 55th and 56th bytes indicates the number of sectors in the flash memory. 10H and
00H are sent starting from the 55th byte.
15. From the device to the controller
The data in the 57th to 65th bytes contains sector information of the flash memory. Sector information is comprised of the start address (starting from the flash memory start address), sector size and
number of consecutive sectors of the same size. Note that the sector size is represented in word units.
The data in the 57th to 65th bytes indicates 8 Kbytes of sectors (sector 0 to sector 15).
For the data to be transferred, see Table 14-10.
16. From the device to the controller
The data in the 66th byte is CHECKSUM data. This is the two's complement of the lower 8-bit
value obtained by summing the data in the 5th to 65th bytes by unsigned 8-bit addition (ignoring any
overflow).
17. From the controller to the device
The data in the 67th byte is the next operation command data.
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14.4.11Flash Memory Chip Erase Command
See Table 14-11.
1. The data in the 1st and 2nd bytes is the same as in the case of the RAM Transfer command.
2. From the controller to the device
The data in the 3rd byte is operation command data. The Flash Memory Chip Erase command data
(40H) is sent here.
3. From the device to the controller
The data in the 4th byte is the ACK response data to the operation command data in the 3rd byte.
The device first checks to see if the data in the 3rd byte contains any error. If a receive error is
found, the device returns the ACK response data for communications error (bit 3) x8H and waits for
the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined. (They are the upper four bits of the immediately preceding operation command data.)
Then, if the data in the 3rd byte corresponds to one of the operation command values given in
Table 14-7, the device echoes back the received data (ACK response for normal reception). In this
case, 40H is echoed back. If the data in the 3rd byte does not correspond to any operation command,
the device returns the ACK response data for operation command error (bit 0) x1H and waits for the
next operation command data (3rd byte). The upper four bits of the ACK response data are undefined. (They are the upper four bits of the immediately preceding operation command data.)
4. From the controller to the device
The data in the 5th byte is Erase Enable command data (54H).
5. From the device to the controller
The data in the 6th byte is the ACK response data to the Erase Enable command data in the 5th
byte.
The device first checks to see if the data in the 5th byte contains any error. If a receive error is
found, the device returns the ACK response data for communications error (bit 3) x8H and waits for
the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined (They are the upper four bits of the immediately preceding operation command data.)
Then, if the data in the 5th byte corresponds to the Erase Enable command data, the device echoes
back the received data (ACK response for normal reception). In this case, 54H is echoed back and
execution jumps to the flash memory chip erase processing routine. If the data in the 5th byte does
not correspond to the Erase Enable command data, the device returns the ACK response data for
operation command error (bit 0) x1H and waits for the next operation command (3rd byte). The
upper four bits of the ACK response data are undefined. (They are the upper four bits of the immediately preceding operation command data.)
6. From the device to the controller
The data in the 7th byte indicates whether or not the erase operation has completed successfully. If
the erase operation has completed successfully, the device returns the end code (4FH). If an erase
error has occurred, the device returns the error code (4CH).
7. From the device to the controller
The data in the 8th byte is ACK response data. If the erase operation has completed successfully,
the device returns the ACK response for erase completion (5DH). If an erase error has occurred, the
device returns the ACK response for erase error (60H).
8. From the controller to the device
The data in the 9th byte is the next operation command data.
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14.4.12Flash Memory Protect Set command
See Table 14-12.
1. The data in the 1st and 2nd bytes is the same as in the case of the RAM Transfer command.
2. From the controller to the device
The data in the 3rd byte is operation command data. The Flash Memory Protect Set command data
(60H) is sent here.
3. From the device to the controller
The data in the 4th byte is the ACK response data to the operation command data in the 3rd byte.
The device first checks to see if the data in the 3rd byte contains any error. If a receive error is
found, the device returns the ACK response data for communications error (bit 3) x8H and waits for
the next operation command data. The upper four bits of the ACK response data are undefined.
(They are the upper four bits of the immediately preceding operation command data.)
Then, if the data in the 3rd byte corresponds to one of the operation command data values given in
Table 14-7, the device echoes back the received data (ACK response for normal reception). In this
case, 60H is echoed back and execution branches to the flash memory protect set processing routine.
After branching to this routine, the data in the password area is checked. For details, see " 14.4.15
Password ". If the data in the 3rd byte does not correspond to any operation command, the device
returns the ACK response data for operation command error (bit 0) x1H and waits for the next operation command data (3rd byte). The upper four bits of the ACK response data are undefined. (They
are the upper four bits of the immediately preceding operation command data.)
4. From the controller to the device
The data in the 5th to 16th bytes is password data (12 bytes). The data in the 5th byte is verified
against the data at address 02FEF4H in the flash memory and the data in the 6th byte against the data
at address 02FEF5H. In this manner, the received data is verified consecutively against the data at the
specified address in the flash memory. The data in the 16th byte is verified against the data at address
02FEFFH in the flash memory.
5. From the controller to the device
The data in the 17th byte is CHECKSUM data. The CHECKSUM data sent by the controller is the
two's complement of the lower 8-bit value obtained by summing the data in 5th to 16th bytes by
unsigned 8-bit addition (ignoring any overflow). For details on CHECKSUM, see " 14.4.17 How to
Calculate CHECKSUM ".
6. From the device to the controller
The data in the 18th byte is the ACK response data to the data in the 5th to 17th bytes (ACK
response to the CHECKSUM value).
The device first checks to see whether the data in the 5th to 17th bytes contains any error. If a
receive error is found, the device returns the ACK response data for communications error (bit 3)
68H and waits for the next operation command data (3rd byte). The upper four bits of the ACK
response data are the upper four bits of the immediately preceding operation command data, so the
value of these bits is “6”.
Then, the device checks the CHECKSUM data in the 17th byte. This check is made to see if the
lower 8 bits of the value obtained by summing the data in the 5th to 17th bytes by unsigned 8-bit
addition (ignoring any overflow) is 00H. If the value is not 00H, the device returns the ACK response
data for CHECKSUM error (bit 0) 61H and waits for the next operation command data (3rd byte).
Finally, the device examines the result of password verification. If all the data in the 5th to 16th
bytes is not verified correctly, the device returns the ACK response data for password error (bit 0)
61H and waits for the next operation command data (3rd byte).
If no error is found in the above checks, the device returns the ACK response data for normal
reception 60H.
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7. From the device to the controller
The data in the 19th byte indicates whether or not the protect set operation has completed successfully. If the operation has completed successfully, the device returns the end code (6FH). If an error
has occurred, the device returns the error code (6CH).
8. From the device to the controller
The data in the 20th byte is ACK response data. If the protect set operation has completed successfully, the device returns the ACK response data for normal completion (31H). If an error has
occurred, the device returns the ACK response data for error (34H).
9. From the device to the controller
The data in the 21st byte is the next operation command data.
14.4.13ACK Response Data
The boot program notifies the controller of its processing status by sending various response data. Table 1413 to Table 14-18 show the ACK response data returned for each type of received data. The upper four bits of
ACK response data are a direct reflection of the upper four bits of the immediately preceding operation command data. Bit 3 indicates a receive error and bit 0 indicates an operation command error, CHECKSUM error
or password error.
Table 14-13 ACK Response Data to Serial Operation Mode Setting Data
Transfer Data
86H
Meaning
The device can communicate in UART mode. (Note)
Note: If the desired baud rate cannot be set, the device returns no data and terminates operation.
Table 14-14 ACK Response Data to Operation Command Data
Transfer data
Meaning
x8H (Note)
A receive error occurred in the operation command data.
x6H (Note)
Terminated receive operation due to protection setting.
x1H (Note)
Undefined operation command data was received normally.
10H
Received the RAM Transfer command.
20H
Received the Flash Memory SUM command.
30H
Received the Product Information Read command.
40H
Received the Flash Memory Chip Erase command.
60H
Received the Flash Memory Protect Set command.
Note:The upper four bits are a direct reflection of the upper four bits of the immediately preceding operation command data.
Table 14-15 ACK Response data to CHECKSUM Data for RAM Transfer Command
Transfer data
Meaning
18H
A receive error occurred.
11H
A CHECKSUM error or password error occurred.
10H
Received the correct CHECKSUM value.
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Table 14-16 ACK Response Data to Flash Memory Chip Erase Operation
Transfer data
Meaning
54H
Received the Erase Enable command.
4FH
Completed erase operation.
4CH
An erase error occurred.
5DH (Note)
Reconfirmation of erase operation
60H (Note)
Reconfirmation of erase error
Note:These codes are returned for reconfirmation of communications.
Table 14-17 ACK Response Data to CHECKSUM Data for Flash Memory Protect Set Command
Transfer data
Meaning
68H
A receive error occurred.
61H
A CHECKSUM or password error occurred.
60H
Received the correct CHECKSUM value.
Table 14-18 ACK Response Data to Flash Memory Protect Set Operation
Transfer data
Meaning
6FH
Completed the protect (read/write) set operation.
6CH
A protect (read/write) set error occurred.
31H (Note)
Reconfirmation of protect (read/write) set operation
34H (Note)
Reconfirmation of protect (read/write) set error
Note:These codes are returned for reconfirmation of communications.
14.4.14Determining Serial Operation Mode
To communicate in UART mode, the controller should transmit the data value 86H as the first byte at the
desired baud rate. Figure 14-7 shows the waveform of this operation.
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The boot program receives the first byte (86H) after reset release not as serial communications data. Instead,
the boot program uses the first byte to determine the baud rate. The baud rate is determined by the output periods of tAB, tAC and tAD as shown in Figure 14-7 using the procedure shown in Figure 14-8.
The CPU monitors the level of the receive pin. Upon detecting a level change, the CPU captures the timer
value to determine the baud rate.
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Start
Initialize 16-bit timer B0
(φT1 = 8/fc, clear counter)
Start the prescaler
Point A
Receive pin changed from
High to Low?
YES
Start counting up of 16-bit timer B0
Point B
Receive pin changed
from Low to High?
YES
Capture timer value (tAB) by software
Point C
Receive pin changed
from High to Low?
YES
Capture timer value (tAC) by software
Point D
Receive pin changed
from Low to High?
YES
Capture timer value (tAD) by software
Stop 16-bit timer B0
YES
tAC ≥ tAD?
Back up tAD value
Stop operation
(Endless loop)
End
Figure 14-8 Flowchart for Serial Operation Mode Receive Operation
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14.4.15Password
When the RAM Transfer command (10H) or the Flash Memory Protect Set command (60H) is received as
operation command data, password verification is performed. First, the device echoes back the operation command data (10H to 60H) and checks the data (12 bytes) in the password area (addresses 02FEF4H to
02FEFFH).
Then, the device verifies the password data received in the 5th to 16th bytes against the data in the password
area as shown in Table 14-19.
Unless all the 12 bytes are verified correctly, a password error will occur.
A password error will also occur if all the 12 bytes of password data contain the same value. Only exception
is when all the 12 bytes are “FFH” and verified correctly and the reset vector area (addresses 02FF00H to
02FF02H) is all “FFH”. In this case, a blank device will be assumed and no password error will occur.
If a password error has occurred, the device returns the ACK response data for password error in the 18th
byte.
Table 14-19
Password Verification Table
Receive data
Data to be verified against
5th byte
Data at address 02FEF4H
6th byte
Data at address 02FEF5H
7th byte
Data at address 02FEF6H
8th byte
Data at address 02FEF7H
9th byte
Data at address 02FEF8H
10th byte
Data at address 02FEF9H
11th byte
Data at address 02FEFAH
12th byte
Data at address 02FEFBH
13th byte
Data at address 02FEFCH
14th byte
Data at address 02FEFDH
15th byte
Data at address 02FEFEH
16th byte
Data at address 02FEFFH
Example of data that cannot be specified as a password
For blank products (Note)
The password of a blank product must be all “FFH” (FFH, FFH, FFH, FFH, FFH, FFH, FFH,
FFH, FFH, FFH, FFH, FFH).
Note:A blank product is a product in which all the bytes in the password area (addresses 02FEF4H to
02FEFFH) and the reset vector area (addresses 02FF00H to 02FF02H) are “FFH”.
For programmed products
The same 12 consecutive bytes cannot be specified as a password.
The table below shows password error examples.
Programmed product
1
2
3
4
5
6
7
8
9
10
11
12
Note
Error example 1
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
ALL"FF"
Error example 2
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
ALL"00"
Error example 3
5AH
5AH
5AH
5AH
5AH
5AH
5AH
5AH
5AH
5AH
5AH
5AH
ALL"5A"
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14.4.16How to Calculate SUM
SUM is calculated by summing the values of all data read from the flash memory by unsigned 8-bit addition
and is returned as a word (16-bit) value. The resulting SUM value is sent to the controller in order of upper 8
bits and lower 8 bits. All the 128 Kbytes of data in the flash memory are included in the calculation of SUM.
When the Flash Memory SUM command is executed, SUM is calculated in this way.
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14.4.17How to Calculate CHECKSUM
CHECKSUM is calculated by taking the two's complement of the lower 8-bit value obtained by summing the
values of received data by unsigned 8-bit addition (ignoring any overflow). When the Flash Memory SUM
command or the Product Information Read command is executed, CHECKSUM is calculated in this way. The
controller should also use this CHECKSUM calculation method for sending CHECKSUM values.
Example: Calculating CHECKSUM for the Flash Memory SUM command
When the upper 8-bit data of SUM is E5H and the lower 8-bit data is F6H, CHECKSUM is calculated
as shown below.
First, the upper 8 bits and lower 8 bits of the SUM value are added by unsigned operation.
E5H+F6H = 1DBH
Then, the two's complement of the lower 8 bits of this result is obtained as shown below. The resulting
CHECKSUM value (25H) is sent to the controller.
0-DBH = 25H
14.5 User Boot Mode (in Single Chip Mode)
User Boot mode, which is a sub mode of Single Chip mode, enables a user-created flash memory program/erase
routine to be used. To do so, the operation mode of Single Chip mode must be changed from Normal mode for executing a user application program to User Boot mode for programming/erasing the flash memory.
For example, the reset processing routine of a user application program may include a routine for selecting Normal
mode or User Boot mode upon entering Single Chip mode. Any mode-selecting condition may be set using the
device's I/O to suit the user system.
To program/erase the flash memory in User Boot mode, a program/erase routine must be incorporated in the user
application program in advance. Since the processor cannot read data from the internal flash memory while it is
being programmed or erased, the program/erase routine must be executed from the outside of the flash memory.
While the flash memory is being programmed/erased in User Boot mode, interrupts must be disabled.
The pages that follow explain the procedure for programming the flash memory using two example cases. In one
case the program/erase routine is stored in the internal flash memory (1-A); in the other the program/erase routine is
transferred from an external source (1-B).
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14.5.1 (1-A) Program/Erase Procedure Example 1
When the program/erase routine is stored in the internal flash memory
(Step-1)Environment setup
First, the condition (e.g. pin status) for entering User Boot mode must be set and the I/O bus for transferring data must be determined. Then, the device's peripheral circuitry must be designed and a corresponding program must be written. Before mounting the device on the board, it is necessary to write the
following four routines into one of the sectors in the flash memory.
(a)Mode select routine:
Selects Normal mode or User Boot mode.
(b)Program/erase routine:
Loads program/erase data from an external source and programs/erases the flash memory.
(c)Copy routine 1:
Copies routines (a) to (d) into the internal RAM or external memory.
(d)Copy routine 2:
Copies routines (a) to (d) from the internal RAM or external memory into the flash memory.
Note:The above (d) is a routine for reconstructing the program/erase routine on the flash memory. If the entire flash
memory is always programmed and the program/erase routine is included in the new user application program, this copy routine is not needed.
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TMP91FW60
(Step-2) Entering User Boot mode (using the reset processing)
After reset release, the reset processing program determines whether or not the device should enter User
Boot mode. If the condition for entering User Boot mode is true, User Boot mode is entered to program/
erase the flash memory.
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(NCUJOGOQT[
0GYWUGT
CRRNKECVKQP RTQITCO ψ4'5'6 %QPVTQNNGT 1NFWUGTCRRNKECVKQP
RTQITCO =4GUGVRTQEGUUKPITQWVKPG ?
%QPFKVKQPHQT
GPVGTKPI7UGT $QQVOQFG
WUGTURGEKHKGF
C/QFGUGNGEVTQWVKPG
D2TQITCOGTCUGTQWVKPG
E%QR[TQWVKPG
F%QR[TQWVKPG
4#/ (Step-3) Copying the program/erase routine
After the device has entered User Boot mode, the copy routine 1 (c) copies the routines (a) to (d) into
the internal RAM or external memory (The routines are copied into the internal RAM here.)
+1
6/2(9
(NCUJOGOQT[
0GYWUGT CRRNKECVKQP
RTQITCO %QPVTQNNGT 1NFWUGTCRRNKECVKQP
RTQITCO C/QFGUGNGEVTQWVKPG
=4GUGVRTQEGUUKPITQWVKPG ?
C/QFGUGNGEVTQWVKPG
D2TQITCOGTCUGTQWVKPG
E%QR[TQWVKPG
F%QR[TQWVKPG
D2TQITCOGTCUGTQWVKPG
E%QR[TQWVKPG
F%QR[TQWVKPG
4#/ Page 241
2007-10-15
TMP91FW60
(Step-4) Erasing the flash memory by the program/erase routine
Control jumps to the program/erase routine in the RAM and the old user program area is erased (sector
erase or chip erase). (In this case, the flash memory erase command is issued from the RAM.)
Note: If data is erased on a sector basis and the routines (a) to (d) are left in the flash memory, only the program/
erase routine (b) need be copied into the RAM.
+1
6/2(9
(NCUJOGOQT[
0GYWUGT CRRNKECVKQP RTQITCO %QPVTQNNGT C/QFGUGNGEVTQWVKPG
D2TQITCOGTCUGTQWVKPG
'TCUGF
E%QR[TQWVKPG
F%QR[TQWVKPG
4#/ (Step-5) Restoring the user boot program in the flash memory
The copy routine 2 (d) in the RAM copies the routines (a) to (d) into the flash memory.
Note: If data is erased on a sector basis and the routines (a) to (d) are left in the flash memory, step 5 is not needed.
+1
6/2(9
(NCUJOGOQT[
0GYWUGT CRRNKECVKQP RTQITCO %QPVTQNNGT C/QFGUGNGEVTQWVKPG
=4GUGVRTQEGUUKPITQWVKPG ?
C/QFGUGNGEVTQWVKPG
D2TQITCOGTCUGTQWVKPG
E%QR[TQWVKPG
F%QR[TQWVKPG
D2TQITCOGTCUGTQWVKPG
E%QR[TQWVKPG
F%QR[TQWVKPG
4#/ Page 242
2007-10-15
TMP91FW60
(Step-6) Writing the new user application program to the flash memory
The program/erase routine in the RAM is executed to load the new user application program from the
controller into the erased area of the flash memory.
+1
6/2(9
%QPVTQNNGT (NCUJOGOQT[
0GYWUGT
CRRNKECVKQP RTQITCO 1NFWUGTCRRNKECVKQP
RTQITCO =4GUGVRTQEGUUKPITQWVKPG ?
C/QFGUGNGEVTQWVKPG
D2TQITCOGTCUGTQWVKPG
E%QR[TQWVKPG
F%QR[TQWVKPG
C/QFGUGNGEVTQWVKPG
D2TQITCOGTCUGTQWVKPG
E%QR[TQWVKPG
F%QR[TQWVKPG
4#/ (Step-7) Executing the new user application program
The RESET input pin is driven Low (“0”) to reset the device. The mode setting condition is set for Normal mode. After reset release, the device will start executing the new user application program.
+1
6/2(9
(NCUJOGOQT[
ψ 4'5'6
%QPVTQNNGT 1NFWUGTCRRNKECVKQP
RTQITCO =4GUGVRTQEGUUKPITQWVKPG ?
C/QFGUGNGEVTQWVKPG
D2TQITCOGTCUGTQWVKPG
E%QR[TQWVKPG
F%QR[TQWVKPG
%QPFKVKQPHQT
GPVGTKPI0QTOCN
OQFG
4#/ Page 243
2007-10-15
TMP91FW60
14.5.2 (1-B) Program/Erase Procedure Example 2
In this example, only the boot program (minimum requirement) is stored in the flash memory and other necessary routines are supplied from the controller.
(Step-1)Environment setup
First, the condition (e.g. pin status) for entering User Boot mode must be set and the I/O bus for transferring data must be determined. Then, the device's peripheral circuitry must be designed and a corresponding program must be written. Before mounting the device on the board, it is necessary to write the
following two routines into one on the sectors in the flash memory.
(a)Mode select routine:
Selects Normal mode or User Boot mode.
(b)Transfer routine:
Loads the program/erase routine from an external source.
The following routines are prepared on the controller.
(c)Program/erase routine:
Programs/erases the flash memory.
(d)Copy routine 1:
Copies routines (a) and (b) into the internal RAM or external memory.
(e)Copy routine 2:
Copies routines (a) and (b) from the internal RAM or external memory into the flash memory.
0GYWUGTCRRNKECVKQP
RTQITCO +1
E2TQITCOGTCUGTQWVKPG
6/2(9
(NCUJOGOQT[
F%QR[TQWVKPG
G%QR[TQWVKPG
1NFWUGTCRRNKECVKQP
RTQITCO %QPVTQNNGT =4GUGVRTQEGUUKPITQWVKPG ?
C/QFGUGNGEVTQWVKPG 4#/ D6TCPUHGTTQWVKPG
Page 244
2007-10-15
TMP91FW60
(Step-2) Entering User Boot mode (using the reset processing)
The following explanation assumes that these routines are incorporated in the reset processing program.
After reset release, the reset processing program first determines whether or not the device should enter
User Boot mode. If the condition for entering User Boot mode is true, User Boot mode is entered to program/erase the flash memory.
0GYWUGTCRRNKECVKQP
RTQITCO +1
6/2(9
(NCUJOGOQT[
E2TQITCOGTCUGTQWVKPG
ψ4'5'6 1NFWUGTCRRNKECVKQP
RTQITCO %QPVTQNNGT %QPFKVKQPHQT
GPVGTKPI7UGT
$QQVOQFG
WUGTURGEKHKGF
=4GUGVRTQEGUUKPITQWVKPG?
C /QFGUGNGEVTQWVKPG F%QR[TQWVKPG
G%QR[TQWVKPG
4#/ D6TCPUHGTTQWVKPG
(Step-3) Copying the program/erase routine to the internal RAM
After the device has entered User Boot mode, the transfer routine (b) transfers the routines (c) to (e)
from the controller to the internal RAM (or external memory). (The routines are copied into the internal
RAM here.)
0GYWUGTCRRNKECVKQP
RTQITCO
E2TQITCOGTCUGTQWVKPG
F%QR[TQWVKPG
6/2(9
(NCUJOGOQT[
G%QR[TQWVKPG
+1
%QPVTQNNGT 1NFWUGTCRRNKECVKQP
RTQITCO E2TQITCOGTCUGTQWVKPG
=4GUGVRTQEGUUKPITQWVKPG ?
F%QR[TQWVKPG
C/QFGUGNGEVTQWVKPG G%QR[TQWVKPG
D6TCPUHGTTQWVKPG
4#/ Page 245
2007-10-15
TMP91FW60
(Step-4) Executing the copy routine 1 in the internal RAM
Control jumps to the internal RAM and the copy routine 1 (d) copies the routines (a) and (b) into the
internal RAM.
0GYWUGTCRRNKECVKQP
RTQITCO E2TQITCOGTCUGTQWVKPG
+1
F%QR[TQWVKPG
G%QR[TQWVKPG
6/2(9
%QPVTQNNGT (NCUJOGOQT[
1NFWUGTCRRNKECVKQP
RTQITCO C/QFGUGNGEVTQWVKPG D6TCPUHGTTQWVKPG
E2TQITCOGTCUGTQWVKPG
=4GUGVRTQEGUUKPITQWVKPG ? F%QR[TQWVKPG
C/QFGUGNGEVTQWVKPG G%QR[TQWVKPG
D6TCPUHGTTQWVKPG
4#/ (Step-5) Erasing the flash memory by the program/erase routine
The program/erase routine (c) erases the old user program area.
0GYWUGTCRRNKECVKQP
RTQITCO E2TQITCOGTCUGTQWVKPG
+1
F%QR[TQWVKPG
6/2(9
(NCUJOGOQT[
G%QR[TQWVKPG
%QPVTQNNGT C/QFGUGNGEVTQWVKPG D6TCPUHGTTQWVKPG
E2TQITCOGTCUGTQWVKPG
'TCUGF
F%QR[TQWVKPG
G%QR[TQWVKPG
4#/ Page 246
2007-10-15
TMP91FW60
(Step-6) Restoring the user boot program in the flash memory
The copy routine (e) copies the routines (a) and (b) from the internal RAM into the flash memory.
0GYWUGTCRRNKECVKQP
RTQITCO E2TQITCOGTCUGTQWVKPG
F%QR[TQWVKPG
+1
6/2(9
(NCUJOGOQT[
G%QR[TQWVKPG
%QPVTQNNGT C/QFGUGNGEVTQWVKPG D6TCPUHGTTQWVKPG
E2TQITCOGTCUGTQWVKPG
=4GUGVRTQEGUUKPITQWVKPG ? F%QR[TQWVKPG
C/QFGUGNGEVTQWVKPG G%QR[TQWVKPG
D6TCPUHGTTQWVKPG
4#/ (Step-7) Writing the new user application program to the flash memory
The program/erase routine (c) in the RAM is executed to load the new user application program from
the controller into the erased area of the flash memory.
0GYWUGTCRRNKECVKQP
RTQITCO E2TQITCOGTCUGTQWVKPG
F%QR[TQWVKPG
+1
G%QR[TQWVKPG
6/2(9
(NCUJOGOQT[
1NFWUGTCRRNKECVKQP
RTQITCO %QPVTQNNGT C/QFGUGNGEVTQWVKPG D6TCPUHGTTQWVKPG
E2TQITCOGTCUGTQWVKPG
=4GUGVRTQEGUUKPITQWVKPG?
F%QR[TQWVKPG
C/QFGUGNGEVTQWVKPG G%QR[TQWVKPG
D6TCPUHGTTQWVKPG
4#/ Page 247
2007-10-15
TMP91FW60
(Step-8) Executing the new user application program
The RESET input pin is driven Low (“0”) to reset the device. The mode setting condition is set for Normal mode. After reset release, the device will start executing the new user application program.
+1
6/2(9
(NCUJOGOQT[
ψ4'5'6 1NFWUGTCRRNKECVKQP
RTQITCO %QPFKVKQPHQT GPVGTKPI0QTOCN
OQFG
=4GUGVRTQEGUUKPITQWVKPG?
C/QFGUGNGEVTQWVKPG %QPVTQNNGT 4#/ D6TCPUHGTTQWVKPG
Page 248
2007-10-15
TMP91FW60
14.6 Flash Memory Command Sequences
The operation of the flash memory is comprised of six commands, as shown in Table 14-20. Addresses specified
in each command sequence must be in an area where the flash memory is mapped. For details, see Table 14-3.
Table 14-20 Command Sequences
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
6th Bus
Write Cycle
Addr.
Data
Addr.
Data
1
Single Word Program
AAAH
AAH
554H
55H
AAAH
A0H
PA
(Note1)
PD
(Note1)
2
Sector Erase
(8KB Erase)
AAAH
AAH
554H
55H
AAAH
80H
AAAH
AAH
554H
55H
SA
(Note2)
30H
3
Chip Erase
(All Erase)
AAAH
AAH
554H
55H
AAAH
80H
AAAH
AAH
554H
55H
AAAH
10H
4
Product ID Entry
AAAH
AAH
554H
55H
AAAH
90H
Product ID Exit
xxH
F0H
Product ID Exit
AAAH
AAH
554H
55H
AAAH
F0H
Read Protect Set
AAAH
AAH
554H
55H
AAAH
A5H
77EH
F0H
(Note3)
Write Protect Set
AAAH
AAH
554H
55H
AAAH
A5H
77EH
0FH
(Note3)
5
6
Note 1: PA = Program Word address, PD = Program Word data
Set the address and data to be programmed. Even-numbered addresses should be specified here.
Note 2: SA = Sector Erase address, Each sector erase range is selected by address A23 to A13.
Note 3: When apply read protect and write protect, be sure to program the data of 00H.
Table 14-21 Hardware Sequence Flags
Status
Single Word Program
During auto operation
Sector Erase/Chip Erase
Read Protect Set/Write Protect
Set
D7
D6
D7
Toggle
0
Toggle
Cannot be
used
Toggle
Note: D15 to D8 and D5 to D0 are “don't care”.
Page 249
2007-10-15
TMP91FW60
14.6.1 Single Word Program
The Single Word Program command sequence programs the flash memory on a word basis. The address and
data to be programmed are specified in the 4th bus write cycle. It takes a maximum of 60 us to program a single word. Another command sequence cannot be executed until the write operation has completed. This can be
checked by reading the same address in the flash memory repeatedly until the same data is read consecutively.
While a write operation is in progress, bit 6 of data is toggled each time it is read.
Note:To rewrite data to Flash memory addresses at which data (including FFFFH) is already written, make sure to
erase the existing data by “sector erase” or “chip erase” before rewriting data.
14.6.2 Sector Erase (8-Kbyte Erase)
The Sector Erase command sequence erases 8 Kbytes of data in the flash memory at a time. The flash memory address range to be erased is specified in the 6th bus write cycle. For the address range of each sector, see
Table 14-3. This command sequence cannot be used in Programmer mode.
It takes a maximum of 75 ms to erase 8 Kbytes. Another command sequence cannot be executed until the
erase operation has completed. This can be checked by reading the same address in the flash memory repeatedly until the same data is read consecutively. While a erase operation is in progress, bit 6 of data is toggled
each time it is read.
14.6.3 Chip Erase (All Erase)
The Chip Erase command sequence erases the entire area of the flash memory.
It takes a maximum of 300 ms to erase the entire flash memory. Another command sequence cannot be executed until the erase operation has completed. This can be checked by reading the same address in the flash
memory repeatedly until the same data is read consecutively. While a erase operation is in progress, bit 6 of
data is toggled each time it is read.
Erase operations clear data to FFH.
14.6.4 Product ID Entry
When the Product ID Entry command is executed, Product ID mode is entered. In this mode, the vendor ID,
flash macro ID, flash size ID, and read/write protect status can be read from the flash memory. In Product ID
mode, the data in the flash memory cannot be read.
14.6.5 Product ID Exit
This command sequence is used to exit Product ID mode.
Page 250
2007-10-15
TMP91FW60
14.6.6 Read Protect Set
The Read Protect Set command sequence applies read protection on the flash memory. When read protection
is applied, the flash memory cannot be read in Programmer mode and the RAM Transfer command cannot be
executed in Single Boot mode.
To cancel read protection, it is necessary to execute the Chip Erase command sequence. To check whether or
not read protection is applied, read xxx77EH in Product ID mode. It takes a maximum of 60 us to set read protection on the flash memory. Another command sequence cannot be executed until the read protection setting
has completed. This can be checked by reading the same address in the flash memory repeatedly until the same
data can be read consecutively. While a read protect operation is in progress, bit 6 of data is toggled each time
it is read.
14.6.7 Write Protect Set
The Write Protect Set command sequence applies write protection on the flash memory. When write protection is applied, the flash memory cannot be written to in Programmer mode and the RAM Transfer command
cannot be executed in Single Boot mode.
To cancel write protection, it is necessary to execute the Chip Erase command sequence. To check whether
or not write protection is applied, read xxx77EH in Product ID mode. It takes a maximum of 60 us to set write
protection. Another command sequence cannot be executed until the write protection setting has completed.
This can be checked by reading the same address in the flash memory repeatedly until the same data can be
read consecutively. While a write protect operation is in progress, bit 6 of data is toggled each time it is read.
14.6.8 Hardware Sequence Flags
The following hardware sequence flags are available to check the auto operation execution status of the flash
memory.
1. Data polling (D7)
When data is written to the flash memory, D7 outputs the complement of its programmed data until
the write operation has completed. After the write operation has completed, D7 outputs the proper
cell data. By reading D7, therefore, the operation status can be checked. While the Sector Erase or
Chip Erase command sequence is being executed, D7 outputs “0”. After the command sequence is
completed, D7 outputs “1” (cell data). Then, the data written to all the bits can be read after waiting
for 1 us.
When read/write protection is applied, the data polling function cannot be used. Instead, use the
toggle bit (D6) to check the operation status.
2. Toggle bit (D6)
When the Flash Memory Program, Sector Erase, Chip Erase, Write Protect Set, or Read Protect Set
command sequence is executed, bit 6 (D6) of the data read by read operations outputs “0” and “1”
alternately each time it is read until the processing of the executed command sequence has completed. The toggle bit (D6) thus provides a software means of checking whether or not the processing
of each command sequence has completed. Normally, the same address in the flash memory is read
repeatedly until the same data is read successively. The initial read of the toggle bit always returns
“1”.
Note:The flash memory incorporated in the TMP91FW60 does not have an exceed-time-limit bit (D5). It is therefore
necessary to set the data polling time limit and toggle bit polling time limit so that polling can be stopped if the
time limit is exceeded.
Page 251
2007-10-15
TMP91FW60
14.6.9 Data Read
Data is read from the flash memory in byte units or word units. It is not necessary to execute a command
sequence to read data from the flash memory.
14.6.10Programming the Flash Memory by the Internal CPU
The internal CPU programs the flash memory by using the command sequences and hardware sequence flags
described above. However, since the flash memory cannot be read during auto operation mode, the program/
erase routine must be executed outside of the flash memory.
The CPU can program the flash memory either by using Single Boot mode or by using a user-created protocol in Single Chip mode (User Boot).
1. Single Boot:
The microcontroller is started up in Single Boot mode to program the flash memory by the internal
boot ROM program. In this mode, the internal boot ROM is mapped to an area including the interrupt
vector table, in which the boot ROM program is executed. The flash memory is mapped to an address
area different from the boot ROM area. The boot ROM program loads data into the flash memory by
serial transfer. In Single Boot mode, interrupts must be disabled including non-maskable interrupts
(NMI, etc.).
For details, see " 14.4 Single Boot Mode "
2. User Boot:
In this method, the flash memory is programmed by executing a user-created routine in Single
Chip mode (normal operation mode). In this mode, the user-created program/erase routine must also
be executed outside of the flash memory. It is also necessary to disable interrupts including nonmaskable interrupts.
The user should prepare a flash memory program/erase routine (including routines for loading
write data and writing the loaded data into the flash memory). In the main program, normal operation
is switched to flash memory programming operation to execute the flash memory program/erase routine outside of the flash memory area. For example, the flash memory program/erase routine may be
transferred from the flash memory to the internal RAM and executed there or it may be prepared and
executed in external memory.
For details, see " 14.5 User Boot Mode (in Single Chip Mode) ".
Page 252
2007-10-15
TMP91FW60
Flowcharts: Flash memory access by the internal CPU
Single Word Program
5VCTV
2TQITCOEQOOCPFUGSWGPEG
(See the flowchart below)
6QIINGDKV
&
Timeout(60Ǵs)
9QTFTGCF
Addr. = 2TQITCOCFFTGUU
4GCFFCVCOCVEJGF
RTQITCOFCVC!
No
Yes
9QTFTGCF
Addr. = 2TQITCOCFFTGUU
4GCFFCVCOCVEJGF
RTQITCOFCVC!
No
Yes
Address = Address + 2
(Even-numbered address/
word units)
No
.CUVCFFTGUU!
Yes
2TQITCOGPF
#DPQTOCNGPF
2TQITCO%QOOCPF5GSWGPEG
#FFTGUU&CVC
xxxAAAH/AAH
xxx554H/55H
xxxAAAH/A0H
'XGPPWODGTGFRTQITCOCFFTGUU
#
RTQITCOFCVC
YQTFWPKVU
Page 253
2007-10-15
TMP91FW60
Chip Erase/Sector Erase
5VCTV 'TCUGEQOOCPFUGSWGPEG 5GGVJGHNQYEJCTVDGNQY
6KOGQWV %JKROU5GEVQTOU
6IINGDKV
&
4GCFFCVCDNCPM!
0QVG
0Q ;GU 'TCUGGPF #DPQTOCNGPF
0QVG+P%JKR'TCUGYJGVJGTQTPQVVJGGPVKTGHNCUJOGOQT[KUDNCPMKUEJGEMGF
+P5GEVQT'TCUGYJGVJGTQTPQVVJGUGNGEVGFUGEVQTKUDNCPMKUEJGEMGF
5GEVQT'TCUG%QOOCPF5GSWGPEG #FFTGUU&CVC
%JKR'TCUG%QOOCPF5GSWGPEG #FFTGUU&CVC
ZZZ###*##* ZZZ###*##* ZZZ **
ZZZ* *
ZZZ###** ZZZ###** ZZZ###*##* ZZZ###*##* ZZZ**
ZZZ **
ZZZ###** 5GEVQTCFFTGUU* Page 254
2007-10-15
TMP91FW60
Read/Write Protect Set
Start
Protect Set command sequence
(See the flowchart below)
Timeout (60 μs)
Toggle bit (D6)
Product ID Entry
Byte read (D7 to D0)
Addr. = xxx77EH
Product ID Exit
Read data matched
program data?
No
Yes
Abnormal end
Protect Set end
Protect Set Command Sequence
(Address/Data)
xxxAAAH/AAH
xxx554H/55H
xxxAAAH/A5H
Set read protect
xxx77EH/F0H
Set write protect
xxx77EH/0FH
Set both read protect and write protect
xxx77EH/00H
Page 255
2007-10-15
TMP91FW60
Data Polling (D7)
5VCTV $[VGTGCF &㨪& 0QVG
#FFT8#
8#8CNKF#FFTGUU
0Q &&CVC!
;GU
1RGTCVKQPGPF
Toggle Bit (D6)
5VCTV $[VGTGCF
&VQ&0QVG
#FFT8#
$[VGTGCF
&VQ&0QVG
#FFT8#
;GU & 6QIING !
0Q 1RGTCVKQPGPF
Note:Hardware sequence flags are read from the flash memory in byte units or word units.
VA:In Single Word Program, VA denotes the address to be programmed.
In Sector Erase, VA denotes any address in the selected sector.
In Chip Erase, VA denotes any address in the flash memory.
In Read Protect Set, VA denotes the protect set address (xx77EH).
In Write Protect Set, VA denotes the protect set address (xx77EH).
Page 256
2007-10-15
TMP91FW60
Product ID Entry
5VCTV ZZZ###*##* ZZZ**
ZZZ###** 9CKVHQTPUGEQTNQPIGT
+&#EEGUUCPF'ZKV6KOG/CZPUGE
‫ޓޓޓ‬㨇2TQFWEV+&OQFGUVCTV㨉
2TQFWEV+&TGCF 5GGVJGVCDNGDGNQY
8GPFQT+& (NCUJOCETQ+&
(NCUJUK\G+&
4GCF9TKVG 2TQVGEVUVCVWU
4GCF8CNWGUKP2TQFWEV+&/QFG #FFTGUU 4GCF8CNWG
ZZZZ*
*
ZZZZ*
*
ZZZZ*
(*
ZZZ'* &CVCRTQITCOOGFYJGPRTQVGEVKQPKUUGV 9JGPRTQVGEVKQPKUPQVUGV((*
Product ID Exit
5VCTV 5VCTV ZZZ###* ##* ZZZZZZ*(* 9CKVHQTPUGEQTNQPIGT
+&#EEGUUCPF'ZKV6KOG/CZPUGE
ZZZ* * ZZZ###*(* 2TQFWEV+&OQFGGPF 9CKVHQTPUGEQTNQPIGT
+&#EEGUUCPF'ZKV6KOG/CZPUGE
2TQFWEV+&OQFGGPF
Page 257
2007-10-15
TMP91FW60
(Example: Program to be loaded and executed in RAM)
Erase the flash memory (chip erase) and then write 0706H to address FE0000H.
;#### Flash memory chip erase processing ####
ld
XIX, 0xFE0000
; set start address
CHIPERASE:
ld
(0xFE0AAA), 0xAA
;1st Bus Write Cycle
ld
(0xFE0554), 0x55
;2nd Bus Write Cycle
ld
(0xFE0AAA), 0x80
;3rd Bus Write Cycle
ld
(0xFE0AAA), 0xAA
;4th Bus Write Cycle
ld
(0xFE0554), 0x55
;5th Bus Write Cycle
ld
(0xFE0AAA), 0x10
;6th Bus Write Cycle
cal
TOGGLECHK
; check toggle bit
CHIPERASE _ LOOP:
ld
WA, (XIX+)
; read data from flash memory
cp
WA, 0xFFFF
; blank data?
j
ne,CHIPERASE _ ERR
; if not blank data, jump to error processing
cp
XIX, 0xFFFFFF
; end address (0xFFFFFF)?
j
ULT,CHIPERASE _ LOOP
; check entire memory area and then end loop processing
;#### Flash memory program processing ####
ld
XIX, 0xFE0000
; set program address
ld
WA, 0x0706
; set program data
ld
(0xFE0AAA), 0xAA
;1st Bus Write Cycle
ld
(0xFE0554), 0x55
;2nd Bus Write Cycle
PROGRAM:
ld
(0xFE0AAA), 0xA0
;3rd Bus Write Cycle
ld
(XIX), WA
;4th Bus Write Cycle
cal
TOGGLECHK
; check toggle bit
ld
BC, (XIX)
; read data from flash memory
cp
WA, BC
j
ne, PROGRAM _ ERR
; if programmed data cannot be read, error is determined
ld
BC, (XIX)
; read data from flash memory
cp
WA, BC
j
ne, PROGRAM _ ERR
; if programmed data cannot be read, error is determined
PROGRAM _ END:
j
PROGRAM _ END
; program operation end
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;#### Toggle bit (D6) check processing ####
TOGGLECHK:
ld
L, (XIX)
and
L, 0y01000000
; check toggle bit (D6)
ld
H, L
; save first toggle bit data
TOGGLECHK1:
ld
L, (XIX)
and
L, 0y01000000
cp
L, H
; toggle bit = toggled?
j
z, TOGGLECHK2
; if not toggled, end processing
ld
H, L
; save current toggle bit state
j
TOGGLECHK1
; recheck toggle bit
; check toggle bit (D6)
TOGGLECHK2:
ret
;#### Error processing ####
CHIPERASE _ ERR:
j
CHIPERASE _ ERR
; chip erase error
PROGRAM _ ERR:
j
PROGRAM _ ERR
; program error
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(Example: Program to be loaded and executed in RAM)
Erase data at addresses FF0000H to FF1FFFH (sector erase) and then write 0706H to address FF0000H.
;#### Flash memory sector erase processing ####
ld
XIX, 0xFF0000
; set start address
SECTORERASE:
ld
(0xFE0AAA), 0xAA
;1st Bus Write Cycle
ld
(0xFE0554), 0x55
;2nd Bus Write Cycle
ld
(0xFE0AAA), 0x80
;3rd Bus Write Cycle
ld
(0xFE0AAA), 0xAA
;4th Bus Write Cycle
ld
(0xFE0554), 0x55
;5th Bus Write Cycle
ld
(XIX), 0x30
;6th Bus Write Cycle
cal
TOGGLECHK
; check toggle bit
SECTORERASE _ LOOP:
ld
WA, (XIX+)
; read data from flash memory
cp
WA, 0xFFFF
; blank data?
j
ne,SECTORERASE _ ERR
; if not blank data, jump to error processing
cp
XIX, 0xFF1FFF
; end address (0xFF1FFF)?
j
ULT,SECTORERASE _ LOOP
; check erased sector area and then end loop processing
;#### Flash memory program processing ####
ld
XIX, 0xFF0000
; set program address
ld
WA, 0x0706
; set program data
ld
(0xFE0AAA), 0xAA
;1st Bus Write Cycle
ld
(0xFE0554), 0x55
;2nd Bus Write Cycle
PROGRAM:
ld
(0xFE0AAA), 0xA0
;3rd Bus Write Cycle
ld
(XIX), WA
;4th Bus Write Cycle
cal
TOGGLECHK
; check toggle bit
ld
BC, (XIX)
; read data from flash memory
cp
WA, BC
j
ne, PROGRAM _ ERR
; if programmed data cannot be read, error is determined
ld
BC, (XIX)
; read data from flash memory
cp
WA, BC
j
ne, PROGRAM _ ERR
; if programmed data cannot be read, error is determined
PROGRAM _ END:
j
PROGRAM _ END
; program operation end
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;#### Toggle bit (D6) check processing ####
TOGGLECHK:
ld
L, (XIX)
and
L, 0y01000000
; check toggle bit (D6)
ld
H, L
; save first toggle bit data
TOGGLECHK1:
ld
L, (XIX)
and
L, 0y01000000
cp
L, H
; toggle bit = toggled?
j
z, TOGGLECHK2
; If not toggled, end processing
ld
H, L
; save current toggle bit state
j
TOGGLECHK1
; Recheck toggle bit
; check toggle bit (D6)
TOGGLECHK2:
ret
;#### Error processing ####
SECTORERASE _ ERR:
j
SECTORERASE _ ERR
; sector erase error
PROGRAM _ ERR:
j
PROGRAM _ ERR
; program error
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(Example: Program to be loaded and executed in RAM)
Set read protection and write protection on the flash memory.
;#### Flash Memory Protect Set processing ####
ld
XIX, 0xFE077E
; set protect address
PROTECT:
ld
(0xFE0AAA), 0xAA
;1st Bus Write Cycle
ld
(0xFE0554), 0x55
;2nd Bus Write Cycle
ld
(0xFE0AAA), 0xA5
;3rd Bus Write Cycle
ld
(XIX), 0x00
;4th Bus Write Cycle
cal
TOGGLECHK
; check toggle bit
cal
PID _ ENTRY
;
ld
A, (XIX)
; read protected address
lcal
PID _ EXIT
;
cp
A, 0x00
;(0xFE077E)=0x00?
j
ne, PROTECT _ ERR
; protected?
PROTECT _ END:
j
PROTECT _ END
; protect set operation completed
PROTECT _ ERR:
j
PROTECT _ ERR
; protect set error
;#### Product ID Entry processing ####
PID _ ENTRY:
ld
(0xFE0AAA), 0xAA
;1st Bus Write Cycle
ld
(0xFE0554), 0x55
;2nd Bus Write Cycle
ld
(0xFE0AAA), 0x90
;3rd Bus Write Cycle
; --- wait for 300 nsec or longer (execute NOP instruction [200nsec/@fFPH=20MHz] two times) --nop
; wait for 400 nsec
nop
ret
;#### Product ID Exit processing ####
PID _ EXIT:
ld
(0xFE0000), 0xF0
;1st Bus Write Cycle
; --- wait for 300 nsec or longer (execute NOP instruction [200nsec/@fFPH=20MHz] two times) --nop
nop
; wait for 400 nsec
ret
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;#### Toggle bit (D6) check processing ####
TOGGLECHK:
ld
L, (XIX)
and
L, 0y01000000
; check toggle bit (D6)
ld
H, L
; save first toggle bit data
TOGGLECHK1:
ld
L, (XIX)
and
L, 0y01000000
cp
L, H
; toggle bit = toggled?
j
z, TOGGLECHK2
; if not toggled, end processing
ld
H, L
; save current toggle bit state
j
TOGGLECHK1
; recheck toggle bit
; check toggle bit (D6)
TOGGLECHK2:
ret
(Example: Program to be loaded and executed in RAM)
Read data from address FE0000H.
;#### Flash memory read processing ####
READ:
ld
WA, (0xFE0000)
; read data from flash memory
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15. Electrical Characteristics
15.1 Absolute Maximum Ratings
Parameter
Symbol
Pin name
Rating
Unit
Supply voltage
VCC
−0.5 to 6.0
V
Input voltage
VIN
−0.5 to VCC + 0.5
V
Output current (Per pin)
IOL1
P5, P6, P96, P97
2
mA
Output current (Per pin)
IOL2
P0, P1, P2, P3, P4, P7, P8, P90-P95,
PA, PB, PZ
5
mA
Output current (Per pin)
IOH1
P5, P6, P96, P97
−2
mA
Output current (Per pin)
IOH2
P0, P1, P2, P3, P4, P7, P8, P90-P95,
PA, PB, PZ
−5
mA
Output current (Total)
∑ IOL
80
mA
Output current (Total)
∑ IOH
−80
mA
Power dissipation (TOPR = 85°C)
PD
600
mW
Soldering temperature (10 s)
TSOLDER
260
°C
Storage temperature
TSTG
−65 to 150
°C
Operating temperature
TOPR
−40 to 85
°C
Note: Absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded
under the worst possible conditions. The equipment manufacturer should design so that no absolute maximum rating value
is exceeded. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect
device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning.
Solderability of lead free products
Test Parameter
Test Condition
Use of Sn-37Pb solder Bath
Solder bath temperature 230 °C, Dipping time 5 [s]
The number of times One, Use of R-type flux
Solderability
Use of Sn-3.0Ag-0.5 Cu solder Bath
Solder bath temperature 245°C, Dipping time 5 [s]
The number of times One, Use of R-type flux (use of lead free)
Page 264
Note
Pass:
solderability rate until forming
≥ 95%
2007-10-15
TMP91FW60
15.2 DC Electrical Characteristics
Parameter
Symbol
(AVCC = DVCC)
fc = 4 to 20 MHz
fs = 30 to 34 kHz
(AVSS = DVSS = 0V)
Power
supply
voltage
for erase/program operations of
flash memory
(AVCC = DVCC)
Condition
VCC
Min
Typ.
4.5
fc = 4 to 20 MHz
TOPR = -10 to 40 °C
Max
Unit
5.5
V
4.75
5.25
(AVSS = DVSS = 0V)
Low-level
input voltage
High-level
input voltage
P00 to P17(AD0 to AD15)
VIL
0.8
P20 to P27, PZ0 to PZ3
VIL1
0.3 VCC
RESET, NMI, P30 to PB3
VIL2
AM0, AM1
VIL3
0.3
0.2 VCC
VCC = 4.5 to 5.5 V
−0.3
X1
VIL4
P00 to P17(AD0 to AD15)
VIH
2.2
P20 to P27, PZ0 to PZ3
VIH1
0.7 VCC
RESET, NMI, P30 to PB3
VIH2
AM0, AM1
VIH3
X1
VIH4
Low-level output voltage
VOL
VCC = 4.5 to 5.5 V
VOH
0.75 VCC
VCC + 0.3
V
0.45
V
0.8 VCC
IOL = 1.6 mA
(VCC = 4.5 to 5.5 V)
(VCC = 4.5 to 5.5 V)
4.2
V
IOH = −1.6 mA
(VCC = 4.5 to 5.5 V)
2.4
Input leakage current
ILI
0.0 ≤ VIN ≤ VCC
0.02
±5
Output leakage current
ILO
0.2 ≤ VIN ≤ VCC − 0.2
0.05
± 10
Power down voltage
(while RAM is being backed up in STOP mode)
VSTOP
RESET pull-up resistor
RRST
VIL2 = 0.2 VCC
2.0
5.5
V
VCC = 4.5 to 5.5 V
50
230
kΩ
10
pF
Pin capacitance
fc = 1 MHz
Schmitt width
RESET, NMI, INT0
VTH
VCC = 4.5 to 5.5 V
0.4
Programmable pull-up resistor
RKH
VCC = 4.5 to 5.5 V
50
VCC = 4.5 to 5.5 V
IDLE2
fc = 20 MHz
IDLE1
SLOW (Note 2)
VCC = 4.5 to 5.5 V
ICC
fs = 32.768 kHz
1.0
TOPR ≤ 70°C
25
35
8
15
3.5
8
80
100
IDDP-P
kΩ
mA
μA
10
VCC = 4.5 to
0.5
5.5 V
TOPR ≤ 85°C
Peak current for Intermittent operation (Note 3,4)
V
230
TOPR ≤ 50°C
STOP
μA
VIH2 = 0.8 VCC
CIO
NORMAL (Note 2)
V
VCC − 0.3
IOH = −400 μA
High-level output voltage
0.25 VCC
VDD = 5.5 V
25
μA
50
−
20
−
mA
Note 1: Typical values show those at TOPR = 25°C and VDD = 5 V.
Note 2: ICC measurement conditions (NORMAL, SLOW): All functions are operational; output pins are open and input pins are
level fixed. Data and address bus CL = 30 pF loaded.
Note 3: When a program is executing in the flash memory or when data is being read from the flash memory, the flash memory
operates in an intermittent manner, causing peak currents in the operation current, as shown in Figure 15-1.
In this case, the supply current ICC (in NORMAL and SLOW modes) is defined as the sum of the average peak current
and MCU current.
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Note 4: When designing the power supply, make sure that peak currents can be supplied. In SLOW1 mode, the difference
between the peak current and the average current becomes large.
1 machine cycle (4/fc or 4/fs)
Program coutner (PC)
n
n+1
n+2
n+3
Momentary flash current
I DDP-P
[mA]
Max. current
Typ. current
Sum of average
momentary flash current
and MCU current
MCU current
Figure 15-1 Intermittent Operation of Flash Memory
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TMP91FW60
15.3 AC Characteristics
15.3.1 VCC = 5.0 V ± 10%
fFPH = 20MHz
Variable
No.
Parameter
Symbol
Unit
Min
Max
Min
Max
tFPH
50.0
31250
50.0
ns
1
fFPH period (= x)
2
A0 to A15 valid
→ ALE falling
tAL
0.5 x −15
10
ns
3
ALE falling → A0 to A15 hold
tLA
0.5 x −15
10
ns
4
ALE high pulse width
tLL
x −20
30
ns
5
ALE falling → RD/WR falling
tLC
0.5 x −20
5
ns
6
RD rising → ALE rising
tCLR
0.5 x −15
10
ns
7
WR rising → ALE rising
tCLW
x −15
35
ns
8
A0 to A15 valid → RD/WR falling
tACL
x −25
25
ns
9
A0 to A21 valid → RD/WR falling
tACH
1.5 x −50
25
ns
10
RD rising → A0 to A21 hold
tCAR
0.5 x −20
5
ns
11
WR rising → A0 to A21 hold
tCAW
x −20
30
ns
12
A0 to A15 valid → D0 to D15 input
tADL
3.0 x −45
105
ns
13
A0 to A21 valid → D0 to D15 input
tADH
3.5 x −35
140
ns
14
RD falling → D0 to D15 input
tRD
2.0 x −40
60
ns
15
RD low pulse width
tRR
2.0x −20
80
ns
16
RD rising → D0 to D15 hold
tHR
0
0
ns
17
RD rising → A0 to A15 output
tRAE
x −15
35
ns
18
WR low pulse width
tWW
1.5x −20
55
ns
19
D0 to D15 valid → WR rising
tDW
1.5x −50
25
ns
20
WR rising → D0 to D15 hold
tWD
x −15
35
ns
21
A0 to A23 valid to WAIT input ((1+N) WAIT mode)
tAWH
22
A0 to A15 valid to WAIT input ((1+N) WAIT mode)
tAWL
23
WAIT hold after RD/WR asserted((1+N) WAIT mode)
tCW
24
A0 to A21 valid → Port input
tAPH
25
A0 to A21 valid → Port hold
tAPH2
26
A0 to A21 valid → Port valid
tAP
3.5x − 90
3.0x − 80
2.0x + 0
85
ns
70
ns
100
3.5x −120
3.5x
ns
55
175
3.5x + 100
ns
ns
275
ns
AC measuring conditions
• Output level:High 0.7VCC/Low 0.3VCC, CL = 50 pF
• Input level:High 0.9VCC/Low 0.1VCC
Note:Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for
CPU core. The period of fFPH depends on the clock gear setting or the selection of high-/low-oscillator frequency.
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15.3.2 Read cycle
tFPH
fFPH
A0~A23
CS0~CS3
tAWH
R/W
tCW
tAWL
WAIT
tAPH2
tAPH
Port Input
tCAR
tADH
RD
tACH
AD0~AD15
tRR
tADL
tRD
A0~A15
tAL
ALE
tACL
tLC
tRAE
tHR
D0~D15
tCLR
tLA
tLL
Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS
are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also
note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact
your local Toshiba sales representative.
Figure 15-2 Read cycle
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TMP91FW60
15.3.3 Write cycle
fFPH
A0~A23
CS0~CS3
R/W
WAIT
tAP
Port Output ᵈ)
tCAW
tWW
WR, HWR
tDW
AD0~AD15
tWD
D0~D15
A0~A15
tCLW
ALE
Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WA and CS are
not enabled. Therefore, the waveform diagram should be regarded as depicting internal operation. Please also note that the
timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local
Toshiba sales representative.
Figure 15-3 Write cycle
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TMP91FW60
15.4 AD Conversion Characteristics
AVCC = VCC, AVSS = VSS
Parameter
Symbol
Variable
Min
Typ.
Max
Unit
VCC − 1.5 V
VCC
VCC
V
VSS
VSS + 0.2 V
V
VREFH
V
1.44
2.00
mA
0.02
5.0
μA
± 1.0
± 4.0
LSB
Analog reference voltage (+)
VREFH
Analog reference voltage (−)
AVSS
VSS
Analog input voltage range
VAIN
AVSS
Analog current for analog
reference voltage
<VREFON> = 1
IREF
VCC = 4.5 to 5.5 V
(AVSS = 0 V)
<VREFON> = 0
Error
(Not including quantizing errors)
−
Note 1: 1LSB = (VREFH − AVSS)/1024 [V]
Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz.
Note 3: The value for ICC includes the current which flows through the AVCC pin.
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15.5 Serial Channel Timing (I/O internal mode)
15.5.1 SCLK input mode
Variable
Parameter
20 MHz
Unit
Min
tSCY
SCLK period
16 MHz
Symbol
Max
16x
Min
Max
Min
Max
800
1000
ns
(VCC = 5V ± 10%)
115
165
ns
tSCY/2 − 4x −85
Output data → SCLK rising/falling edge*
tOSS
SCLK rising/falling edge* → Output data hold
tOHS
tSCY/2 + 2x + 0
500
625
ns
SCLK rising/falling edge* → Input data hold
tHSR
3x + 10
160
198
ns
SCLK rising/falling edge* → Valid data input*
tSRD
Valid data input → SCLK rising/falling edge*
tRDS
tSCY − 0
800
0
1000
0
0
ns
ns
Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The
period of fFPH depends on the clock gear setting or the selection of high-/low-oscillator frequency.
15.5.2 SCLK output mode
Variable
Parameter
20 MHz
16 MHz
Symbol
Unit
Min
Max
8192x
Min
Max
0.8
410
Min
Max
1.0
512
μs
SCLK period
tSCY
16x
Output data → SCLK rising/falling edge*
tOSS
tSCY/2 − 40
360
460
ns
SCLK rising/falling edge* → Output data
hold
tOHS
tSCY/2 − 40
360
460
ns
SCLK rising/falling edge* → Input data hold
tHSR
0
0
0
ns
SCLK rising/falling edge* → Valid data
input
tSRD
Valid data input → SCLK rising/falling
edge*
tRDS
tSCY − 1x − 90
1x + 90
660
140
847
153
ns
ns
Note 1: *: SCLK rising/falling edge:The rising edge is used in SCLK rising mode.
The falling edge is used in SCLK falling mode.
Note 2: 20 MHz and 16 MHz values are calculated from tSCY = 16x case.
Note 3: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The
period of fFPH depends on the clock gear setting or the selection of high-/low-oscillator frequency.
tSCY
SCLK
(rising edge)
SCLK
(falling edge)
tOSS
Output data
TXD
Input data
RXD
tOHS
0
1
tSRD
2
3
tRDS tHSR
0
1
2
3
Valid
Valid
Valid
Valid
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TMP91FW60
15.6 Event Counter
TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0,TB1IN1, TB2IN0,TB2IN1, TB3IN0,TB3IN1, TB4IN0,TB4IN1
Variable
Parameter
20 MHz
16 MHz
Symbol
Unit
Min
Max
Min
Max
Min
Max
Clock period
tVCK
8x + 100
500
600
ns
Clock low-level width
tVCKL
4x + 40
240
290
ns
Clock high-level width
tVCKH
4x + 40
240
290
ns
Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The
period of fFPH depends on the clock gear setting or the selection of high-/low-oscillator frequency.
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15.7 Interrupt and Capture
15.7.1 NMI, INT0 interrupts
Variable
Parameter
20 MHz
16 MHz
Symbol
Unit
Min
Max
Min
Max
Min
Max
NMI, INT0 low-level width
tINTAL
4x + 40
240
290
ns
NMI, INT0 high-level width
tINTAH
4x + 40
240
290
ns
Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The
period of fFPH depends on the clock gear setting or the selection of high-/low-oscillator frequency.
15.7.2 INT1 to INT10 interrupts, capture
INT1 to INT10 input pulse width depend on the system clock selection and clock selection for prescaler.
Below table show pulse width of each operation clock.
System Clock
Selection
SYSCR1
<SYSCK>
Clock Selection for
Prescaler SYSCR0
<PRCK1>
tINTBH
(INT1 to INT10 high level pulse width)
Variable
fFPH = 20MHz
Variable
fFPH = 20 MHz
Min
Min
Min
Min
0 (fFPH)
8x + 100
500
8x + 100
500
1 (fc/16)
128xc + 0.1
6.5
128xc + 0.1
6.5
0 (fFPH)
8x + 0.1
244.3
8x + 0.1
244.3
0 (fc)
1 (fc)
tINTBL
(INT1 to INT10 low level pulse width)
Unit
ns
us
Note 1: “xc” shows period of clock fc in high frequency oscillator.
Note 2: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The
period of fFPH depends on the clock gear setting or the selection of high-/low-oscillator frequency.
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15.8 SCOUT Pin AC Characteristics
Variable
Parameter
20 MHz
16 MHz
Symbol
Condition
Min
Max
Min
Max
Min
Unit
Max
Low-level width
tSCH
0.5T − 15
10
16
VCC ≥ 4.5V
ns
High-level width
tSCL
0.5T − 15
10
16
VCC ≥ 4.5V
ns
Note: T = Period of SCOUT
Measuring conditions
Output level: High = 0.7 VCC, Low = 0.3 VCC, CL = 10 pF
tSCH
tSCL
SCOUT
15.9 Flash Characteristics
15.9.1 Write/Retention Characteristics
(VSS = 0 V)
Parameter
Condition
Min
Typ.
Max.
Unit
−
−
100
Times
VSS = 0 V
Number of guaranteed writes to flash memory
fc = 4 to 20 MHz
TOPR = −10 to 40°C
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15.10 Recommended Oscillating Conditions
The TMP91FW60 has been evaluated by the oscillator vender below. Use this information when selecting external
parts.
X1
X2
XT1
Rd
Rd
C1
C2
(1) High-frequency Oscillation
XT2
C1
C2
(2) Low-frequency Oscillation
Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are
greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be
mounted.
Note 2: When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend
electrically shielding the package in order to maintain normal operating condition.
Note 3: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For
up-to-date information, please refer to the following URL:
http://www.murata.co.jp/search/index.html
Page 275
2007-10-15
TMP91FW60
16. Table of SFR’s
The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 4-Kbyte
address space from 000000H to 000FFFH.
1. I/O ports
2. I/O port control
3. Interrupt control
4. Chip select/wait control
5. Clock control
6. 8-bit timer
7. 16-bit timer
8. UART/serial channel
9. I2C bus interface
10. AD converter
11. Watchdog timer
12. Special timer for CLOCK
13. Program patch logic
Page 276
2007-10-15
TMP91FW60
Table 16-1 SFR Address Map (PORT, INTC, CS/WAIT)
[1]PORT
Address
0000H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
P0
P1
P0CR
P1CR
P1FC
P2
P2CR
P2FC
P3
P3FC2
P3CR
P3FC
Address
Name
0010H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Address
0020H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
P4
P4FC2
P4CR
P4FC
P5
P5CR
P5FC
P6
P6CR
P6FC
P7
P7CR
P7FC
Name
P8
P8CR
P8FC
P9
P9CR
P9FC
PA
PACR
PAFC
PB
PBFC2
PBCR
PBFC
[2]INTC
Address
Name
Address
Name
0080H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
0070H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH PZ
EH PZCR
FH PZFC
0030H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH ODE
Address
Name
DMA0V
DMA1V
DMA2V
DMA3V
INTCLR
DMAR
DMAB
IIMC
[3]CS/WAIT
Address
0090H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
INTE0AD
INTE12
INTE34
INTE56
INTE78
INTE910
INTETA01
INTETA23
INTETA45
INTETB0
INTETB1
INTETB2
INTETB3
INTETB4
INTETB01V
INTETB23V
Address
Name
00A0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
INTETB4VRTC
INTES0
INTES1
INTES2
INTESBI01
INTETC01
INTETC23
Address
00C0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
B0CS
B1CS
B2CS
B3CS
BEXCS
MSAR0
MAMR0
MSAR1
MAMR1
MSAR2
MAMR2
MSAR3
MAMR3
Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
Page 277
2007-10-15
TMP91FW60
Table 16-2 SFR Address Map (CGEAR, TMRA, TMRB)
[4] CGEAR
Address
00E0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
[5] TMRA
Name
SYSCR0
SYSCR1
SYSCR2
EMCCR0
EMCCR1
Address
Name
Address
0100H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
00F0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TA01RUN
TA0REG
TA1REG
TA01MOD
TA1FFCR
TA23RUN
TA2REG
TA3REG
TA23MOD
TA3FFCR
[6] TMRB
Address
0110H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Address
01A0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TA45RUN
TA4REG
TA5REG
TA45MOD
TA5FFCR
Name
TB2RUN
TB2MOD
TB2FFCR
TB2RG0L
TB2RG0H
TB2RG1L
TB2RG1H
TB2CP0L
TB2CP0H
TB2CP1L
TB2CP1H
Address
0180H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TB0RUN
TB0MOD
TB0FFCR
TB0RG0L
TB0RG0H
TB0RG1L
TB0RG1H
TB0CP0L
TB0CP0H
TB0CP1L
TB0CP1H
Address
01B0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TB3RUN
TB3MOD
TB3FFCR
TB3RG0L
TB3RG0H
TB3RG1L
TB3RG1H
TB3CP0L
TB3CP0H
TB3CP1L
TB3CP1H
Address
0190H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TB1RUN
TB1MOD
TB1FFCR
TB1RG0L
TB1RG0H
TB1RG1L
TB1RG1H
TB1CP0L
TB1CP0H
TB1CP1L
TB1CP1H
Address
01C0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TB4RUN
TB4MOD
TB4FFCR
TB4RG0L
TB4RG0H
TB4RG1L
TB4RG1H
TB4CP0L
TB4CP0H
TB4CP1L
TB4CP1H
Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
Page 278
2007-10-15
TMP91FW60
Table 16-3 SFR Address Map (UART/SIO, I2C, ADC, WDT, RTC, ROMC)
[8] I2C
[7] UART/SIO
Address
0200H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
SC0BUF
SC0CR
SC0MOD0
BR0CR
BR0ADD
SC0MOD1
SC1BUF
SC1CR
SC1MOD0
BR1CR
BR1ADD
SC1MOD1
[9]10bit ADC
Address
02B0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Address
0210H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
SC2BUF
SC2CR
SC2MOD0
BR2CR
BR2ADD
SC2MOD1
[10] WDT
Name
ADCCR1
ADCCR2
ADCDRL
ADCDRH
Address
0240H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
SBI0CR1
SBI0DBR
I2C0AR
SBI0CR2/SBI0SR
SBI0BR
SBI0CR0
SBI1CR1
SBI1DBR
I2C1AR
SBI1CR2/SBI1SR
SBI1BR
SBI1CR0
[11] RTC
Address
Name
0300H WDMOD
1H WDCR
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Address
Name
0310H RTCCR
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
[12] ROMC
Address
0400H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
ROMCMP00
ROMCMP01
ROMCMP02
ROMSUB0L
ROMSUB0H
ROMCMP10
ROMCMP11
ROMCMP12
ROMSUB1L
ROMSUB1H
Address
0410H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
ROMCMP20
ROMCMP21
ROMCMP22
ROMSUB2L
ROMSUB2H
ROMCMP30
ROMCMP31
ROMCMP32
ROMSUB3L
ROMSUB3H
Address
0420H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
ROMCMP40
ROMCMP41
ROMCMP42
ROMSUB4L
ROMSUB4H
ROMCMP50
ROMCMP51
ROMCMP52
ROMSUB5L
ROMSUB5H
Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
Page 279
2007-10-15
TMP91FW60
(1)
I/O Ports
Symbol
P0
Name
Port 0
Address
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
P11
P10
P21
P20
P31
P30
R/W
00H
Data from external port (Output latch register is undefined.)
P17
P1
Port 1
P16
P15
P14
01H
P13
P12
R/W
Data from external port (Output latch register is cleared to “0”.)
P27
P2
Port 2
P26
P25
P24
P23
P22
R/W
06H
Data from external port (Output latch register is set to “1”.)
P3
P4
P5
Port 3
Port 4
Port 5
0CH
10H
–
–
–
–
P33
P32
–
–
–
–
R/W
Data from external port
(Output latch register is set to “1”.)
–
–
–
–
–
–
–
P44
–
–
–
R/W
P43
P42
P41
–
–
–
Data from external port
(Output latch register is set to “1”.)
–
–
–
0 (Output latch register): Pull-up resistor OFF
1 (Output latch register): Pull-up resistor ON
P57
P56
P55
P54
14H
P53
P52
P40
P51
P50
P61
P60
P71
P70
R/W
Data from external port (Output latch register is set to “1”.)
P67
P6
Port 6
P66
P65
P64
18H
P63
P62
R/W
Data from external port (Output latch register is set to “1”.)
P7
P8
Port 7
Port 8
1CH
–
–
P75
–
–
–
–
–
Data from external port (Output latch register is set to “1”.)
P87
P86
P85
P74
P73
P84
20H
P83
P72
P82
P81
P80
P91
P90
PA1
PA0
R/W
Data from external port (Output latch register is set to “1”.)
P97
P9
Port 9
P96
P95
P94
24H
P93
P92
R/W
Data from external port (Output latch register is set to “1”.)
PA
PB
PZ
Port A
Port B
Port Z
28H
2CH
–
–
–
–
–
–
–
–
PA3
R/W
–
–
–
–
Data from external port
(Output latch register is set to “1”.)
–
–
–
–
–
–
–
–
R/W
–
–
–
–
Data from external port
(Output latch register is set to “1”.)
–
–
–
–
–
–
–
–
–
–
–
–
7DH
PB3
PA2
PZ3
PB2
PB1
PZ2
PZ1
PZ0
1
1
R/W
Data from external port
(Output latch register is
set to “1”.)
0 (Output latch register):
Pull-up resistor OFF
1 (Output latch register):
Pull-up resistor ON
Page 280
PB0
output mode
2007-10-15
TMP91FW60
(2) I/O Port control
Symbol
Name
Address
7
6
5
4
3
2
1
0
P07C
P06C
P05C
P04C
P03C
P02C
P01C
P00C
0
0
0
0
0
0
0
0
02H
P0CR
Port 0
control
W
(RMW instructions are prohibited.)
0: Input 1: Output (When access to external, become AD7 to AD0 and this register is cleared to “0”.)
P17C
P16C
P15C
P14C
0
0
0
0
P17F
P16F
P15F
P14F
0
0
0
0
P27C
P26C
P25C
P24C
0
0
0
0
P27F
P26F
P25F
P24F
0
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P13C
P12C
P11C
P10C
0
0
0
0
P13F
P12F
P11F
P10F
0
0
0
0
04H
P1CR
Port 1
control
W
(RMW instructions are prohibited.)
<<Refer to column of P1FC>>
05H
P1FC
Port 1
function
W
(RMW instructions are prohibited.)
P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8
P23C
P22C
P21C
P20C
0
0
0
0
P23F
P22F
P21F
P20F
0
0
0
0
P31C
P30C
0
0
08H
P2CR
Port 2
control
W
(RMW instructions are prohibited.)
<<Refer to column of P2FC>>
09H
P2FC
Port 2
function
W
(RMW instructions are prohibited.)
P2FC/P2CR = 00: Input, 01: Output, 10: A7 to A0, 11: A23 to A16
0EH
P3CR
Port 3
control
tions are pro-
–
–
–
–
–
–
–
–
–
–
–
–
0FH
Port 3
function
P32C
0
0
W
(RMW instruchibited.)
P3FC
P33C
<<Refer to column of
P3FC>>
P33F
tions are prohibited.)
–
–
–
–
P32F
0
port
01:output
port
11:TB3OUT1
Port 3
function 2
P30F
0
0
0
P32F/
P32C=
00:input
port
01:output
<<Refer to column of
P3FC2>>
port
10: WAIT
11:TB3OUT0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P31F2
(RMW instructions are prohibited.)
–
–
–
–
–
–
0
0
port
001:output
port
010:TB3IN1
/INT4
101: SCL0
Page 281
P30F2
W
P31F2/
P31F/
P31C=
000:input
0DH
P3FC2
P31F
W
P33F/
P33C=
00:input
(RMW instruc-
<<Refer to column of
P3FC2>>
P30F2/
P30F/
P30C=
000:input
port
001:output
port
010:TB3IN0
/INT3
101: SDA0
2007-10-15
TMP91FW60
Symbol
Name
Address
7
6
5
4
3
2
1
0
–
–
–
P44C
P43C
P42C
P41C
P40C
(RMW instruc-
–
–
–
tions are pro-
–
–
–
0
0
–
–
–
–
–
–
(RMW instruc-
–
–
–
tions are pro-
–
–
–
–
–
–
12H
P4CR
Port 4
control
W
0
0
0
hibited.)
<<Refer to column of P4FC2>>
P44F
P43F
P42F
P41F
P40F
0
0
13H
P4FC
Port 4
function
W
0
0
0
hibited.)
<<Refer to column of P4FC2>>
–
–
–
–
P43F2
–
–
–
–
–
W
–
–
–
–
–
0
–
0
0
P44F,P44C=
P43F2,P43F
,P43C=
000 :input
P42F,P42C=
P41F2,P41F
P40F2,P40F
00: input
, P41C =
, P40C =
000: input
port
001:output
port
011: CS0
101: SCOUT
11H
P4FC2
Port 4
function 2
(RMW instruc-
00: input
tions are pro-
port
hibited.)
–
–
–
prort
11:ALE
P57C
P56C
P55C
port
001: output
port
011:CS1
101:TXD2
port
port
11:CS2
011:CS3
101:SCLK2
P54C
000: input
01: output
001:output
P40F2
W
port
port
01: output
P41F2
P53C
P52C
P51C
P50C
0
0
0
0
P52F
P51F
P50F
16H
P5CR
Port 5
control
W
(RMW instructions are pro-
0
0
0
0
hibited.)
0: Input 1: Output
P57F
P56F
P55F
P54F
17H
P5FC
Port 5
function
(RMW instructions are prohibited.)
P53F
W
0
P57 input
0: disable
1: enable
P67C
0
0
P56 input
0: disable
1: enable
P66C
0
P55 input
0: disable
1: enable
0
P54 input
0: disable
1: enable
P65C
0
P53 input
0: disable
1: enable
P64C
0
P52 input
0: disable
1: enable
0
P51 input
0: disable
1: enable
P50 input
0: disable
1: enable
P63C
P62C
P61C
P60C
0
0
0
0
P62F
P61F
P60F
1AH
P6CR
Port 6
control
W
(RMW instructions are pro-
0
0
0
0
hibited.)
0: Input 1: Output
P67F
P66F
P65F
P64F
1BH
P6FC
Port 6
function
(RMW instructions are prohibited.)
P63F
W
0
P67 input
0: disable
1: enable
0
0
P66 input
0: disable
1: enable
–
–
(RMW instruc-
–
–
tions are pro-
–
–
–
–
–
–
–
–
–
–
0
P65 input
0: disable
1: enable
P64 input
0: disable
1: enable
P75C
P74C
0
0
P63 input
0: disable
1: enable
0
P62 input
0: disable
1: enable
P73C
0
P61 input
0: disable
1: enable
P60 input
0: disable
1: enable
P72C
P71C
P70C
0
0
0
P71F
–
1EH
P7CR
Port 7
control
W
0
0
0
hibited.)
1FH
P7FC
Port 7
function
0: Input 1: Output
P75F
P74F
W
–
P72F
–
W
–
(RMW instructions are prohibited.)
–
–
0
0: Port
1: INT0
Page 282
0
0: Port
1: TA5OUT
–
–
0
0
0: Port
0: Port
–
1: TA3OUT
1: TA1OUT
–
2007-10-15
TMP91FW60
Symbol
Name
Address
7
6
5
4
P87C
P86C
P85C
P84C
3
2
1
0
P83C
P82C
P81C
P80C
0
0
0
0
P83F
P82F
P81F
P80F
0
0
22H
P8CR
Port 8
control
W
(RMW instructions are pro-
0
0
0
0
hibited.)
0: Input 1: Output
P87F
P86F
P85F
P84F
W
23H
P8FC
Port 8
function
(RMW instruc-
0
0
tions are prohibited.)
1: TB1OUT1
0: port
0: port
1: TB1OUT0
P97C
P96C
0
0
0: port
0: port
1: TB1IN1,
1: TB1IN0,
INT8
P95C
INT7
0
0
0: port
0: port
1: TB0IN1,
1: TB0IN0,
0: port
1: TB0OUT1
0: port
1: TB0OUT0
P93C
P92C
P91C
P90C
0
0
0
0
P92F
–
P90F
–
W
P94C
INT6
INT5
26H
P9CR
Port 9
control
W
(RMW instructions are pro-
1
1
0
0
hibited.)
0: Input 1: Output
P97F
Port 9
function
(RMW instructions are prohibited.)
P95F
W
27H
P9FC
P96F
0
Port
0: disable
1: enable
–
P93F
–
0
0
Port
0: disable
1: enable
0: port
1: SCLK1
W
–
–
0
0
0: port
1: TXD1
output
0: port
1: SCLK0
output
output
–
–
–
–
(RMW instruc-
–
–
–
–
tions are pro-
–
–
–
–
–
–
–
–
–
–
–
–
2BH
–
–
–
–
(RMW instruc-
–
–
–
–
–
–
–
–
–
PA3C
PA2C
0
0
PA3F
PA2F
0
0
0: port
1: TXD0
–
output
PA1C
PA0C
0
0
2AH
PACR
Port A
control
W
hibited.)
PAFC
Port A
function
0: Input 1: Output
PA1F
PA0F
0
0
0
0:port
1: TB2OUT0
0: port
1: TB2IN1,
INT2
0: port
1: TB2IN0,
INT1
PB3C
PB2C
PB1C
PB0C
0
0
0
0
W
tions are prohibited.)
–
–
–
–
(RMW instruc-
–
–
–
–
tions are pro-
–
–
–
–
–
–
–
–
–
–
–
–
(RMW instruc-
–
–
–
–
tions are pro-
–
–
–
–
0: port
1:
TB2OUT1
2EH
PBCR
Port B
control
W
hibited.)
<<Refer to column of PBFC2>>
PB3F
PB2F
0
0
PB1F
PB0F
0
0
2FH
PBFC
Port B
function
W
hibited.)
–
–
–
–
–
–
–
–
–
<<Refer to column of PBFC2>>
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
PB2F, PB2C
=
00: input
port
01: output
port
11:TB4OUT0
PB1F2,PB1
F, PB1C =
000: input
port
001: output
port
010: TB4IN1
/INT10
101: SCL1
PB0F2,PB0
F, PB0C =
000: input
port
001:output
port
010: TB4IN0
/INT9
101: SDA1
2DH
PBFC2
Port B
function 2
(RMW instructions are prohibited.)
–
–
–
Page 283
–
PB3F, PB3C
=
00: input
port
01: output
port
11:TB4OUT1
PB1F2
PB0F2
W
2007-10-15
TMP91FW60
Symbol
Name
Address
7
6
5
4
3
PZ3C
–
–
–
–
(RMW instruc-
–
–
–
–
tions are pro-
–
–
–
–
–
–
–
–
2
1
PZ2C
0
–
–
–
–
–
–
–
–
PZ1F
PZ0F
7EH
PZCR
Port Z
control
W
0
0
hibited.)
7FH
PZFC
Port Z
function
–
–
–
–
–
–
–
–
–
–
–
–
ODE
PZ3F
PZ2F
W
(RMW instructions are prohibited.)
Open-drain
control
register
0:Input 1:Output
–
–
–
–
–
ODEB1
ODEB0
ODE93
0
0
0
–
0
0: port
1:R/ W
ODE90
0
0: port
1: HWR
0
0
0: port
1: WR
0: port
1: RD
ODE41
ODE31
ODE30
0
0
0
R/W
3FH
–
–
0
0: CMOS output 1:Open drain output
Page 284
2007-10-15
TMP91FW60
(3) Interrupt control
Symbol
Name
Address
7
6
5
4
3
2
INTAD
INTE0AD
Interrupt
enable
0 & AD
IADC
90H
IADM2
IADM1
R
0
IADM0
R/W
0
0
1: INTAD
I0C
I0M2
R
INTE12
Interrupt
enable
2/1
91H
0
Interrput level
I2M1
0
0
1: INT0
I2M0
R/W
0
0
1: INT2
Interrupt
enable
4/3
I4C
92H
I1C
I1M2
0
INTE56
Interrupt
enable
6/5
93H
I4M2
I4M1
0
I4M0
Interrupt
enable
8/7
I8C
94H
0
I3C
I3M2
I6M1
0
0
0
0
I6M0
I5C
I5M2
INTE910
Interrupt
enable
10 / 9
95H
0
0
I8M1
R/W
0
1: INT5
I8M0
R/W
0
0
0
I7C
0
I7M2
INTETA01
ITA1C
96H
0
I10M0
ITA1M2
0
0
0
I9C
0
INTETA23
ITA3C
ITA1M1
ITA1M0
0
97H
R
0
ITA3M1
0
0
1: INTTA3
ITA0C
0
INTETA45
ITA5C
98H
ITA5M2
0
1: INTTA5
ITA5M1
0
Interrput level
Page 285
ITA0M2
0
ITA0M1
ITA0M0
R/W
0
0
0
Interrput level
ITA2C
ITA2M2
0
ITA2M1
ITA2M0
R/W
0
1: INTTA2
0
0
Interrput level
INTTA4 (TMRA4)
ITA5M0
R/W
0
0
Interrput level
R
0
Interrput level
R
I9M0
INTTA2 (TMRA2)
ITA3M0
INTTA5 (TMRA5)
Interrupt
enable
timer A
5/4
I9M1
R/W
0
1: INTTA0
R/W
0
I9M2
R
Interrput level
ITA3M2
0
INTTA0 (TMRA0)
INTTA3 (TMRA3)
Interrupt
enable
timer A
3/2
0
Interrput level
1: INT9
R/W
1: INTTA1
I7M0
R/W
R
0
Interrput level
R
I7M1
INT9
I10M1
INTTA1(TMRA1)
Interrupt
enable
timer A
1/0
0
Interrput level
1: INT7
R/W
1: INT10
0
R
Interrput level
0
I5M0
INT7
I8M2
R
0
I5M1
R
0
Interrput level
I10M2
0
Interrput level
INT10
I10C
I3M0
R/W
1: INT3
R/W
0
R
0
I3M1
INT5
I6M2
1: INT8
0
Interrput level
INT8
INTE78
0
R
Interrput level
1: INT6
I1M0
R/W
1: INT1
R/W
R
0
I1M1
0
INT6
I6C
0
INT3
R
0
0
R
0
Interrput level
1: INT4
I0M0
Interrput level
INT4
INTE34
I0M1
INT1
I2M2
R
0
0
R/W
INT2
I2C
1
INT0
ITA4C
ITA4M2
R
0
0
1: INTTA4
ITA4M1
ITA4M0
R/W
0
0
0
Interrput level
2007-10-15
TMP91FW60
Symbol
Name
Address
7
6
5
ITB01C
ITB01M2
4
3
2
ITB01M0
ITB00C
ITB00M2
INTTB01(TMRB0)
INTETB0
Interrupt
enable
TMRB 0
99H
ITB01M1
R
0
0
R
0
Interrput level
1: INTTB01
0
Interrupt
enable
TMRB 1
ITB11C
9AH
ITB11M2
ITB11M1
R
0
0
0
ITB11M0
ITB10C
0
Interrput level
INTETB2
Interrupt
enable
TMRB 2
9BH
ITB21M2
ITB21M1
R
0
0
0
ITB20C
Interrupt
enable
TMRB 3
ITB31C
9CH
ITB31M2
ITB31M1
R
0
0
0
0
ITB31M0
INTETB4
Interrupt
enable
TMRB 4
9DH
ITB41M1
R
0
0
0
ITB30C
0
ITB40C
Interrupt
enable
TMRB 0/1
(Over flow)
ITF1C
9EH
ITF1M2
ITF1M1
R
0
0
0
0
INTETB23V
ITF3C
ITF1M0
9FH
ITF3M1
R
0
0
0
ITF0C
0
ITF2C
INTETB4VRTC
(Over flow)/
INTRTC
IRTCC
A0H
IRTCM2
R
0
1: INTRTC
ITB30M0
0
0
Interrput level
ITB40M2
ITB40M1
ITB40M0
R/W
0
0
0
Interrput level
ITF0M2
ITF0M1
ITF0M0
R/W
0
0
0
Interrput level
ITF2M2
0
ITF2M1
ITF2M0
R/W
0
0
0
Interrput level
1:INTTBOF2
INTTBOF4(TMRB4 over flow)
IRTCM1
IRTCM0
R/W
0
0
R
0
INTRTC
Interrupt
enable
TMRB4
ITB30M1
INTTBOF2(TMRB2 over flow)
ITF3M0
Interrput level
1: INTTBOF3
0
R/W
1:INTTBOF0
R/W
0
ITB30M2
R
Interrput level
ITF3M2
0
INTTBOF1(TMRB0 over flow)
INTTBOF3(TMRB3 over flow)
Interrupt
enable
TMRB 2/3
(Over flow)
ITB20M0
Interrput level
1: INTTB40
R/W
1: INTTBOF1
ITB20M1
R/W
0
R
0
INTTBOF1(TMRB1 over flow)
INTETB01V
0
INTTB40(TMRB4)
ITB41M0
Interrput level
1: INTTB41
ITB20M2
1: INTTB30
R/W
0
0
Interrput level
R
Interrput level
ITB41M2
ITB10M0
INTTB30(TMRB3)
INTTB41(TMRB4)
ITB41C
0
1: INTTB20
R/W
1: INTTB31
ITB10M1
R/W
R
0
INTTB31(TMRB3)
INTETB3
0
INTTB20(TMRB2)
ITB21M0
Interrput level
1: INTTB21
ITB10M2
1: INTTB10
R/W
0
0
Interrput level
R
INTTB21(TMRB2)
ITB21C
ITB00M0
INTTB10(TMRB1)
R/W
1: INTTB11
ITB00M1
R/W
0
1: INTTB00
INTTB11(TMRB1)
INTETB1
0
INTTB00(TMRB0)
R/W
0
1
0
Interrput level
Page 286
ITF4C
ITF4M2
R
0
0
1:INTTBOF4
ITF4M1
ITF4M0
R/W
0
0
0
Interrput level
2007-10-15
TMP91FW60
Symbol
Name
Address
7
6
ITX0C
ITX0M2
5
4
3
2
ITX0M1
ITX0M0
IRX0C
IRX0M2
INTTX0
INTES0
Interrupt
enable
serial 0
A1H
R
0
0
1: INTTX0
Interrupt
enable
serial 1
ITX1C
A2H
Interrput level
ITX1M2
0
R/W
0
0
0
ITX1M0
0
IRX1C
IRX1M2
INTES2
Interrupt
enable
serial 2
A3H
0
0
0
0
0
1: INTTX2
Interrupt
enable
SBI 0/1
ISBI1C
A4H
ITX2M0
IRX0C
IRX2M2
ISBI1M2
0
0
ISBI1M0
0
ISBI0C
ISBI0M2
INTETC01
Interrupt
enable
TC 0/1
A5H
0
0
0
0
0
ITC1M0
ITC0C
ITC0M2
0
Interrupt
enable
TC 2/3
ITC3C
A6H
ITC3M2
R
0
1: INTTC3
ITC0M0
R/W
0
1: INTTC0
0
Interrput level
INTTC2
ITC3M1
ITC3M0
R/W
0
ITC0M1
0
INTTC3
INTETC23
0
Interrput level
R
0
Interrput level
1: INTTC1
0
1: INTSBI0
R/W
0
ISBI0M0
R/W
INTTC0
ITC1M1
R
ISBI0M1
R
Interrput level
ITC1M2
0
Interrput level
INTTC1
ITC1C
0
INTSBI0
ISBI1M1
0
IRX2M0
R/W
0
1: INTRX2
R/W
1: INTSBI1
IRX2M1
R
0
Interrput level
R
0
Interrput level
INTSBI1
INTESBI01
0
1: INTRX1
R/W
0
IRX1M0
R/W
INTRX2
ITX2M1
R
IRX1M1
R
Interrput level
ITX2M2
0
Interrput level
INTTX2
ITX2C
0
1: INTRX0
R/W
1: INTTX1
IRX0M0
INTRX1
ITX1M1
R
IRX0M1
R
0
INTTX1
INTES1
0
INTRX0
R/W
0
1
0
Interrput level
Page 287
ITC2C
ITC2M2
R
0
0
1: INTTC2
ITC2M1
ITC2M0
R/W
0
0
0
Interrput level
2007-10-15
TMP91FW60
Symbol
DMA0V
DMA1V
DMA2V
DMA3V
INTCLR
DMAR
DMAB
Name
DMA0
Start
Vector
DMA1
Start
Vector
DMA2
Start
Vector
DMA3
Start
Vector
Interrupt
Clear
Control
DMA
Software
Request
Register
DMA
Burst
Register
Address
80H
81H
82H
83H
88H
(RMW instructions are prohibited.)
89H
(RMW instructions are prohibited.)
8AH
7
6
5
4
3
2
1
0
–
–
DMA0V5
DMA0V4
DMA0V3
DMA0V2
DMA0V1
DMA0V0
–
–
–
–
–
–
–
–
0
0
0
DMA1V2
DMA1V1
DMA1V0
–
–
–
–
–
–
–
–
0
0
0
DMA2V2
DMA2V1
DMA2V0
–
–
–
–
–
–
–
–
0
0
0
DMA3V2
DMA3V1
DMA3V0
–
–
–
–
–
–
–
–
0
0
0
CLRV2
CLRV1
CLRV0
–
–
–
–
–
–
–
–
0
0
0
–
–
DMAR1
DMAR0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
R/W
0
0
0
DMA0 start vector
DMA1V5
DMA1V4
DMA1V3
0
0
0
DMA2V5
DMA2V4
DMA2V3
R/W
DMA1 start vector
R/W
0
0
0
DMA3V5
DMA3V4
DMA3V3
DMA2 start vector
R/W
0
0
0
DMA3 start vector
CLRV5
CLRV4
CLRV3
W
0
0
0
Interrupt vector
DMAR3
DMAR2
0
0
R/W
1: DMA software request
DMAB3
DMAB2
DMAB1
DMAB0
0
0
R/W
0
0
–
I0EDGE
I0LE
NMIREE
0
0
0
0
1: DMA burst request
W
IIMC
Interrupt
input
mode
control
8CH
(RMW instructions are prohibited.)
Always
write “0”.
–
–
–
–
INT0
EDGE
0: Rising
1: Falling
INT0
mode
0: Edge
1: Level
1:Operates even
on rising/
falling
edge of
NMI
Page 288
2007-10-15
TMP91FW60
(4) Chip select / wait control
Symbol
Name
Address
7
6
5
4
3
2
1
0
B0E
–
–
–
B0OM1
B0OM0
B0BUS
B0W2
B0W1
B0W0
0
0
0
0
0
0
W
B0CS
B1CS
Block 0
CS/WAIT
control
register
Block 1
CS/WAIT
control
register
C0H
0
W
tions are prohibited.)
C1H
0: Disable
1: Enable
–
B1E
–
W
–
0
–
–
B2E
B2M
B1OM1
B1OM0
B1BUS
0
0
0
Chip select output waveform selection
00: For ROM/SRAM
01: Don’t care
10: Don’t care
11: Don’t care
tions are pro-
0: Disable
1: Enable
Data bus
width
0: 16 bits
1: 8 bits
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
B1W2
B1W1
B1W0
0
0
0
W
(RMW instruchibited.)
Number of waits
Chip select output waveform selection
00: For ROM/SRAM
01: Don’t care
10: Don’t care
11: Don’t care
(RMW instruc-
B2OM1
Number of waits
Data bus
width
0: 16 bits
1: 8 bits
B2OM0
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
B2BUS
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
B2W2
B2W1
B2W0
0
0
0
W
B2CS
B3CS
BEXCS
Block 2
CS/WAIT
control
register
Block 3
CS/WAIT
control
register
External
CS/WAIT
control
register
C2H
1
(RMW instructions are prohibited.)
C3H
0: Disable
1: Enable
0
CS2 area
selection
0:16Mbyte
area
1: CS area
B3E
–
W
–
0
–
(RMW instructions are prohibited.)
C7H
0
0: Disable
1: Enable
–
–
–
–
–
0
Chip select output waveform selection
00: ROM/SRAM
01: Don't care
10: Don't care
11: Don't care
B3OM1
B3OM0
0
Number of waits
Data bus
width
0: 16 bits
1: 8 bits
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
B3BUS
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
B3W2
B3W1
B3W0
0
0
0
W
0
0
Chip select output waveform selection
00: For ROM/SRAM
01: Don’t care
10: Don’t care
11: Don’t care
0
Number of waits
Data bus
width
0: 16 bits
1: 8 bits
–
–
BEXBUS
–
–
–
–
–
–
0
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
BEXW2
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
BEXW1
BEXW0
0
0
W
(RMW instruc-
0
Number of waits
tions are prohibited.)
–
–
–
Page 289
–
Data bus
width
0: 16 bits
1: 8 bits
000: 2 WAIT
001: 1 WAIT
010: 1 WAIT+N
011: 0 WAIT
100:
101:
110:
111:
Reserved
3 WAIT
4 WAIT
8 WAIT
2007-10-15
TMP91FW60
Symbol
Name
MSAR0
Memory
address
register 0
Address
7
6
5
4
S23
S22
S21
S20
3
2
1
0
S19
S18
S17
S16
1
1
1
1
V16
V15
V14~V9
V8
1
1
1
1
R/W
C8H
1
1
1
1
Determine A23 to A16 of start address
MAMR0
Memory
address
mask
register 0
V20
MSAR1
V18
V17
R/W
C9H
1
1
1
1
Set size of CS0 area
S23
Memory
address
register 1
V19
S22
S21
0: Used for address compare
S20
S19
S18
S17
S16
1
1
1
1
V17
V16
V15~V9
V8
1
1
1
1
R/W
CAH
1
1
1
1
Determine A23 to A16 of start address
MAMR1
Memory
address
mask
register 1
V21
MSAR2
V19
V18
R/W
CBH
1
1
1
1
Set size of CS1 area
S23
Memory
address
register 2
V20
S22
S21
0: Used for address compare
S20
S19
S18
S17
S16
1
1
1
1
V18
V17
V16
V15
1
1
1
1
R/W
CCH
1
1
1
1
Determine A23 to A16 of start address
MAMR2
Memory
address
mask
register 2
V22
MSAR3
V20
V19
R/W
CDH
1
1
1
1
Set size of CS2 area
S23
Memory
address
register 3
V21
S22
S21
0: Used for address compare
S20
S19
S18
S17
S16
1
1
1
1
V18
V17
V16
V15
1
1
1
1
R/W
CEH
1
1
1
1
Determine A23 to A16 of start address
MAMR3
Memory
address
mask
register 3
V22
V21
V20
V19
R/W
CFH
1
1
1
1
Set size of CS3 area
Page 290
0: Used for address compare
2007-10-15
TMP91FW60
(5) Clock control
Symbol
Name
Address
7
6
5
4
3
2
1
0
XEN
XTEN
RXEN
RXTEN
RSYSCK
WUEF
PRCK1
R/W
1
SYSCR0
SYSCR1
System
clock
control
register 0
System
clock
control
register 1
E0H
0
1
0
0
Selects
clock after
release of
STOP
mode
0:fc
1:fs
SYSCK
GEAR2
0
0
Lowfrequency
oscillator
0:Stop
1:Oscillation
–
–
–
–
–
–
–
–
–
–
–
–
E1H
–
Select
prescaler
clock
0:fFPH
1:fc/16
GEAR2
GEAR2
0
0
R/W
Select gear value of high frequency (fc)
000:fc
001:fc/2
010:fc/4
011:fc/8
100:fc/16
101:reserved
110:reserved
111:reserved
–
–
–
–
–
SCOSEL
WUPTM1
WUPTM0
HALTM1
HALTM0
–
DRVE
–
R/W
0
1
1
1
–
0
–
Pin state
control in
STOP
mode
0: I/O off
1:Remains
the state
before
HALT
–
–
–
0
1
1
R/W
0
Select warm-up time for
oscillator
E2H
–
00:218/inputted frequency
Select
SCOUT
0:fs
1:fSYS
01:28/inputted frequency
10:214/inputted frequency
HALT mode
00:reserved
01:STOP mode
10:IDLE1 mode
11:IDLE2 mode
11:216/inputted frequency
PROTECT
–
–
–
0
1
0
R
EMCCR0
EMCCR1
EMC
control
register 0
EMC
control
register 1
0
E3H
–
Select system clock
0: fc
1: fs
–
SYSCR2
0
Lowfrequency
oscillator
(fs) after
release of
STOP
mode
0:Stop
1:Oscillation
Highfrequency
oscillator
0:Stop
1:Oscillation
–
System
clock
control
register 1
0
Warm-up
timer control
0 Write:
Don't care
1 Write:
Start
warm-up
0 Read:
End warmup
1 Read:
Do not end
warm-up
Highfrequency
oscillator
(fc) after
release of
STOP
mode
0:Stop
1:Oscillation
–
–
Protect
flag
0:OFF
1:ON
–
R/W
Write "0".
Write "1".
Write "0".
0
Write "0".
Write "0".
Write "1".
Write "1".
Protect OFF by writing "1FH".
Protect ON by writing except "1FH".
E4H
Page 291
2007-10-15
TMP91FW60
(6) 8-bit timer
Symbol
TA01RUN
TA0REG
TA1REG
Name
8-bit
timer
RUN
8-bit
timer
register 0
8-bit
timer
register 1
Address
100H
7
6
5
4
3
2
TA0RDE
–
–
–
I2TA01
TA01PRUN
R/W
–
–
–
0
–
–
–
Double
buffer
0: Disable
1: Enable
–
–
0
TA1RUN
TA0RUN
R/W
0
IDLE2
0: Stop
1: Operate
–
102H
1
0
TMRA01
prescaler
0
0
Up counter
(UC1)
Up counter
(UC0)
0: Stop and clear
1: Run (count up)
–
(RMW instruc-
W
tions are prohibited.)
0
103H
–
(RMW instruc-
W
tions are pro-
0
hibited.)
TA01M1
TA01M0
PWM01
PWM00
TA1CLK1
TA1CLK0
TA0CLK1
TA0CLK0
0
0
0
R/W
TA01MOD
TA1FFCR
8-bit
timer
source
CLK &
mode
8-bit
timer
frip-flop
control
0
104H
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
0
0
PWM cycle
00: Reserved
Input clock for TMRA1
00: TA0TRG
01: φT1
10: φT16
11: φT256
01: 26
10: 27
11: 28
–
–
–
–
–
–
–
–
–
–
–
–
105H
–
–
–
Page 292
0
–
Input clock for TMRA0
00: TA0IN pin
01: φT1
10: φT4
11: φT16
TA1FFC1
TA1FFC0
1
1
TA1FFIE
TA1FFIS
0
0
TA1FF
control for
inversion
0: Disable
1: Enable
TA1FF
inversion
select
0: TMRA0
1: TMRA1
R/W
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don’t care
2007-10-15
TMP91FW60
Symbol
TA23RUN
TA2REG
TA3REG
Name
8-bit
timer
RUN
8-bit
timer
register 0
8-bit
timer
register 1
Address
108H
7
6
5
4
3
2
TA2RDE
–
–
–
I2TA23
TA23PRUN
R/W
–
–
–
0
–
–
–
Double
buffer
0: Disable
1: Enable
–
–
0
TA3RUN
TA2RUN
R/W
0
IDLE2
0: Stop
1: Operate
–
10AH
1
0
TMRA23
prescaler
0
0
Up counter
(UC3)
Up counter
(UC2)
0: Stop and clear
1: Run (count up)
–
(RMW instruc-
W
tions are prohibited.)
0
10BH
–
(RMW instruc-
W
tions are pro-
0
hibited.)
TA23M1
TA23M0
PWM21
PWM20
TA3CLK1
TA3CLK0
TA2CLK1
TA2CLK0
0
0
0
R/W
TA23MOD
TA3FFCR
8-bit
timer
source
CLK &
mode
8-bit
timer
frip-flop
control
0
10CH
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
0
0
PWM cycle
00: Reserved
Input clock for TMRA3
00: TA2TRG
01: φT1
10: φT16
11: φT256
01: 26
10: 27
11: 28
–
–
–
–
–
–
–
–
–
–
–
–
10DH
–
–
–
Page 293
0
–
Input clock for TMRA2
00: Reserved
01: φT1
10: φT4
11: φT16
TA3FFC1
TA3FFC0
1
1
TA3FFIE
TA3FFIS
0
0
TA3FF
control for
inversion
0: Disable
1: Enable
TA3FF
inversion
select
0: TMRA2
1: TMRA3
R/W
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don’t care
2007-10-15
TMP91FW60
Symbol
TA45RUN
TA4REG
TA5REG
Name
8-bit
timer
RUN
8-bit
timer
register 0
8-bit
timer
register 1
Address
110H
7
6
5
4
3
2
TA4RDE
–
–
–
I2TA45
TA45PRUN
R/W
–
–
–
0
–
–
–
Double
buffer
0: Disable
1: Enable
–
–
0
TA5RUN
TA4RUN
R/W
0
IDLE2
0: Stop
1: Operate
–
112H
1
0
TMRA45
prescaler
0
0
Up counter
(UC5)
Up counter
(UC4)
0: Stop and clear
1: Run (count up)
–
(RMW instruc-
W
tions are prohibited.)
0
113H
–
(RMW instruc-
W
tions are pro-
0
hibited.)
TA45M1
TA45M0
PWM41
PWM40
TA5CLK1
TA5CLK0
TA4CLK1
TA4CLK0
0
0
0
R/W
TA45MOD
TA5FFCR
8-bit
timer
source
CLK &
mode
8-bit
timer
frip-flop
control
0
114H
0
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
0
0
PWM cycle
00: Reserved
Input clock for TMRA5
00: TA4TRG
01: φT1
10: φT16
11: φT256
01: 26
10: 27
11: 28
–
–
–
–
–
–
–
–
–
–
–
–
115H
–
–
–
Page 294
0
–
Input clock for TMRA4
00: TA4IN pin
01: φT1
10: φT4
11: φT16
TA5FFC1
TA5FFC0
1
1
TA5FFIE
TA5FFIS
0
0
TA5FF
control for
inversion
0: Disable
1: Enable
TA5FF
inversion
select
0: TMRA4
1: TMRA5
R/W
00: Invert TA5FF
01: Set TA5FF
10: Clear TA5FF
11: Don’t care
2007-10-15
TMP91FW60
(7) 16-bit timer
Symbol
Name
Address
7
TB0RDE
6
5
4
3
–
–
–
I2TB0
–
–
–
–
R/W
TB0RUN
16-bit
timer
control
0
180H
0
Double
Buffer
0: Disable
1: Enable
Always
write 0.
TB0CT1
–
TB0ET1
R/W
TB0MOD
16-bit
timer
source
CLK &
mode
0
182H
(RMW instructions are pro-
TB0CP0I
1
TB0FF1 inversion trigger
0: Trigger disable
1: Trigger enable
hibited.)
Invert when
UC0
matches
with
TB0RG1H/L
Invert when
UC0 is
loaded into
TB0CP1H/L
TB0FF1C1
TB0FF1C0
Software
capture
control
0: Software
capture
1: Undefined
TB0C1T1
1
TB0FFCR
TB0RG0L
TB0RG0H
TB0RG1L
TB0RG1H
16-bit
timer
register 0L
16-bit
timer
register 0H
16-bit
timer
register 1L
16-bit
timer
register 1H
0
IDLE2
0: Stop
1: Operate
–
TB0CPM1
TB0CPM0
0
0
0
TB0PRUN
–
TB0RUN
–
R/W
0
–
0
–
Up counter
(UC0)
TB0CLK1
TB0CLK0
0
0
TMRB0
prescaler
0: Stop and Clear
1: Run (count up)
TB0CLE
R/W
Capture timing
00: Disable
INT5 occurs at rising edge
01: TB0IN0↑ TB0IN1↑
INT5 occurs at rising edge
10: TB0IN0↑ TB0IN0↓
INT5 occurs at falling edge
11: TA1OUT↑ TA1OUT↓
INT5 occurs at rising edge
TB0C0T1
W*
16-bit
timer
frip-flop
control
1
R/W
W*
0
2
TB0E1T1
0
Up counter
control
0: Clear
disable
1: Clear
enable
TB0E0T1
TMRB0 input clock
select
00: TB0IN0 pin input
01: φT1
10: φT4
11: φT16
TB0FF0C1
R/W
1
0
0
TB0FF0C0
W*
0
0
1
1
183H
(RMW instructions are prohibited.)
TB0FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
TB0FF0 inversion trigger
0: Disable
1: Enable
Invert when
UC0 is
loaded into
TB0CP1H/L.
Invert when
UC0
matches
TB0RG1H/L.
Invert when
UC0 is
loaded into
TB0CP0H/L.
Invert when
UC0
matches
TB0RG0H/L.
TB0FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
–
188H
(RMW instruc-
W
tions are pro-
Undefined
hibited.)
189H
–
(RMW instruc-
W
tions are prohibited.)
Undefined
18AH
–
(RMW instruc-
W
tions are prohibited.)
Undefined
18BH
–
(RMW instruc-
W
tions are prohibited.)
Undefined
18CH
R
–
TB0CP0L
Capture
register 0L
Undefined
–
TB0CP0H
Capture
register 0H
18DH
R
Undefined
–
TB0CP1L
Capture
register 1L
18EH
R
Undefined
–
TB0CP1H
Capture
register 1H
18FH
R
Undefined
Page 295
2007-10-15
TMP91FW60
Symbol
Name
Address
7
TB1RDE
6
5
4
3
–
–
–
I2TB1
–
–
–
–
R/W
TB1RUN
16-bit
timer
control
0
190H
0
Double
Buffer
0: Disable
1: Enable
Always
write 0.
TB1CT1
–
TB1ET1
R/W
TB1MOD
16-bit
timer
source
CLK &
mode
0
192H
(RMW instructions are pro-
1
TB1FF1 inversion trigger
0: Trigger disable
1: Trigger enable
hibited.)
Invert when
UC1
matches
with
TB1RG1H/L
TB1FF1C1
TB1FF1C0
Software
capture
control
0: Software
capture
1: Undefined
TB1C1T1
1
TB1FFCR
TB1RG0L
TB1RG0H
TB1RG1L
TB1RG1H
16-bit
timer
register 0L
16-bit
timer
register 0H
16-bit
timer
register 1L
16-bit
timer
register 1H
0
IDLE2
0: Stop
1: Operate
–
TB1CPM1
TB1CPM0
0
0
0
TB1PRUN
–
TB1RUN
–
R/W
0
–
0
–
Up counter
(UC1)
TB1CLK1
TB1CLK0
0
0
TMRB1
prescaler
0: Stop and Clear
1: Run (count up)
TB1CLE
R/W
Capture timing
00: Disable
INT7 occurs at rising edge
01: TB1IN0↑ TB1IN1↑
INT7 occurs at rising edge
10: TB1IN0↑ TB1IN0↓
INT7 occurs at falling edge
11: TA1OUT↑ TA1OUT↓
INT7 occurs at rising edge
TB1C0T1
W*
16-bit
timer
frip-flop
control
1
R/W
W*
0
Invert when
UC1 is
loaded into
TB1CP1H/L
TB1CP0I
2
TB1E1T1
0
Up counter
control
0: Clear
disable
1: Clear
enable
TB1E0T1
TMRB1 input clock
select
00: TB1IN0 pin input
01: φT1
10: φT4
11: φT16
TB1FF0C1
R/W
1
0
0
TB1FF0C0
W*
0
0
1
1
193H
(RMW instructions are prohibited.)
TB1FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
TB1FF0 inversion trigger
0: Disable
1: Enable
Invert when
UC1 is
loaded into
TB1CP1H/L.
Invert when
UC1 is
loaded into
TB1CP0H/L.
Invert when
UC1
matches
TB1RG1H/L.
Invert when
UC1
matches
TB1RG0H/L.
TB1FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
–
198H
(RMW instruc-
W
tions are pro-
Undefined
hibited.)
–
199H
(RMW instruc-
W
tions are prohibited.)
Undefined
19AH
–
(RMW instruc-
W
tions are prohibited.)
Undefined
19BH
–
(RMW instruc-
W
tions are prohibited.)
Undefined
19CH
R
–
TB1CP0L
Capture
register 0L
Undefined
–
TB1CP0H
Capture
register 0H
19DH
R
Undefined
–
TB1CP1L
Capture
register 1L
19EH
R
Undefined
–
TB1CP1H
Capture
register 1H
19FH
R
Undefined
Page 296
2007-10-15
TMP91FW60
Symbol
Name
Address
7
TB2RDE
6
5
4
3
–
–
–
I2TB2
–
–
–
–
R/W
TB2RUN
16-bit
timer
control
0
1A0H
0
Double
Buffer
0: Disable
1: Enable
Always
write 0.
TB2CT1
–
TB2ET1
R/W
TB2MOD
16-bit
timer
source
CLK &
mode
0
1A2H
(RMW instructions are pro-
1
TB2FF1 inversion trigger
0: Trigger disable
1: Trigger enable
hibited.)
Invert when
UC2
matches
with
TB2RG1H/L
TB2FF1C1
TB2FF1C0
Software
capture
control
0: Software
capture
1: Undefined
TB2C1T1
1
TB2FFCR
TB2RG0L
TB2RG0H
TB2RG1L
TB2RG1H
16-bit
timer
register 0L
16-bit
timer
register 0H
16-bit
timer
register 1L
16-bit
timer
register 1H
0
IDLE2
0: Stop
1: Operate
–
TB2CPM1
TB2CPM0
0
0
0
TB2PRUN
–
TB2RUN
–
R/W
0
–
0
–
Up counter
(UC2)
TB2CLK1
TB2CLK0
0
0
TMRB2
prescaler
0: Stop and Clear
1: Run (count up)
TB2CLE
R/W
Capture timing
00: Disable
INT1 occurs at rising edge
01: TB2IN0↑ TB2IN1↑
INT1 occurs at rising edge
10: TB2IN0↑ TB2IN0↓
INT1 occurs at falling edge
11: TA1OUT↑ TA1OUT↓
INT1 occurs at rising edge
TB2C0T1
W*
16-bit
timer
frip-flop
control
1
R/W
W*
0
Invert when
UC2 is
loaded into
TB2CP1H/L
TB2CP0I
2
TB2E1T1
0
Up counter
control
0: Clear
disable
1: Clear
enable
TB2E0T1
TMRB2 input clock
select
00: TB2IN0 pin input
01: φT1
10: φT4
11: φT16
TB2FF0C1
R/W
1
0
0
TB2FF0C0
W*
0
0
1
1
1A3H
(RMW instructions are prohibited.)
TB2FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
TB2FF0 inversion trigger
0: Disable
1: Enable
Invert when
UC2 is
loaded into
TB2CP1H/L.
Invert when
UC2 is
loaded into
TB2CP0H/L.
Invert when
UC2
matches
TB2RG1H/L.
Invert when
UC2
matches
TB2RG0H/L.
TB2FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
–
1A8H
(RMW instruc-
W
tions are pro-
Undefined
hibited.)
–
1A9H
(RMW instruc-
W
tions are prohibited.)
Undefined
1AAH
–
(RMW instruc-
W
tions are prohibited.)
Undefined
1ABH
–
(RMW instruc-
W
tions are prohibited.)
Undefined
1ACH
R
–
TB2CP0L
Capture
register 0L
Undefined
–
TB2CP0H
Capture
register 0H
1ADH
R
Undefined
–
TB2CP1L
Capture
register 1L
1AEH
R
Undefined
–
TB2CP1H
Capture
register 1H
1AFH
R
Undefined
Page 297
2007-10-15
TMP91FW60
Symbol
Name
Address
7
TB3RDE
6
5
4
3
–
–
–
I2TB3
–
–
–
–
R/W
TB3RUN
16-bit
timer
control
0
1B0H
0
Double
Buffer
0: Disable
1: Enable
Always
write 0.
TB3CT1
–
TB3ET1
R/W
0
TB3MOD
16-bit
timer
source
CLK &
mode
1B2H
(RMW instructions are pro-
TB3CP0I
1
TB3FF1 inversion trigger
0: Trigger disable
1: Trigger enable
hibited.)
Invert when
UC3 is
loaded into
TB3CP1H/L
Invert when
UC3
matches
with
TB3RG1H/L
TB3FF1C1
TB3FF1C0
Software
capture
control
0: Software
capture
1: Undefined
TB3FFCR
TB3RG0L
TB3RG0H
TB3RG1L
TB3RG1H
16-bit
timer
frip-flop
control
16-bit
timer
register 0L
16-bit
timer
register 0H
16-bit
timer
register 1L
16-bit
timer
register 1H
0
IDLE2
0: Stop
1: Operate
–
TB3CPM1
TB3CPM0
0
0
0
TB3PRUN
–
TB3RUN
–
R/W
0
–
0
–
Up counter
(UC3)
TB3CLK1
TB3CLK0
0
0
TMRB3
prescaler
0: Stop and Clear
1: Run (count up)
TB3CLE
R/W
Capture timing
00: Disable
INT3 occurs at rising edge
01: TB3IN0↑ TB3IN1↑
INT3 occurs at rising edge
10: TB3IN0↑ TB3IN0↓
INT3 occurs at falling edge
11: TA3OUT↑ TA3OUT↓
0
Up counter
control
0: Clear
disable
1: Clear
enable
TMRB3 input clock
select
00: TB3IN0 pin input
01: φT1
10: φT4
11: φT16
INT3 occurs at rising edge
TB3C1T1
TB3C0T1
0
0
W*
1
1
R/W
W*
0
2
TB3E1T1
TB3E0T1
TB3FF0C1
0
0
1
R/W
1
TB3FF0C0
W*
1
1B3H
(RMW instructions are prohibited.)
TB3FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
TB3FF0 inversion trigger
0: Disable
1: Enable
Invert when
UC3 is
loaded into
TB3CP1H/L.
Invert when
UC3 is
loaded into
TB3CP0H/L.
Invert when
UC3
matches
TB3RG1H/L.
Invert when
UC3
matches
TB3RG0H/L.
TB3FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
–
1B8H
(RMW instruc-
W
tions are prohibited.)
Undefined
1B9H
–
(RMW instruc-
W
tions are prohibited.)
Undefined
1BAH
–
(RMW instruc-
W
tions are pro-
Undefined
hibited.)
–
1BBH
(RMW instruc-
W
tions are prohibited.)
Undefined
1BCH
R
–
TB3CP0L
Capture
register 0L
Undefined
–
TB3CP0H
Capture
register 0H
1BDH
R
Undefined
–
TB3CP1L
Capture
register 1L
1BEH
R
Undefined
–
TB3CP1H
Capture
register 1H
1BFH
R
Undefined
Page 298
2007-10-15
TMP91FW60
Symbol
Name
Address
7
TB4RDE
6
5
4
3
–
–
–
I2TB4
–
–
–
–
R/W
TB4RUN
16-bit
timer
control
0
1C0H
0
Double
Buffer
0: Disable
1: Enable
Always
write 0.
TB4CT1
–
TB4ET1
R/W
TB4MOD
16-bit
timer
source
CLK &
mode
0
1C2H
(RMW instructions are pro-
TB4CP0I
1
TB4FF1 inversion trigger
0: Trigger disable
1: Trigger enable
hibited.)
Invert when
UC4
matches
with
TB4RG1H/L
Invert when
UC4 is
loaded into
TB4CP1H/L
TB4FF1C1
TB4FF1C0
Software
capture
control
0: Software
capture
1: Undefined
TB4C1T1
1
TB4FFCR
TB4RG0L
TB4RG0H
TB4RG1L
TB4RG1H
16-bit
timer
register 0L
16-bit
timer
register 0H
16-bit
timer
register 1L
16-bit
timer
register 1H
0
IDLE2
0: Stop
1: Operate
–
TB4CPM1
TB4CPM0
0
0
0
TB4PRUN
–
TB4RUN
–
R/W
0
–
0
–
Up counter
(UC4)
TB4CLK1
TB4CLK0
0
0
TMRB4
prescaler
0: Stop and Clear
1: Run (count up)
TB4CLE
R/W
Capture timing
00: Disable
INT9 occurs at rising edge
01: TB4IN0↑ TB4IN1↑
INT9 occurs at rising edge
10: TB4IN0↑ TB4IN0↓
INT9 occurs at falling edge
11: TA5OUT↑ TA5OUT↓
INT9 occurs at rising edge
TB4C0T1
W*
16-bit
timer
frip-flop
control
1
R/W
W*
0
2
TB4E1T1
0
Up counter
control
0: Clear
disable
1: Clear
enable
TB4E0T1
TMRB4 input clock
select
00: TB4IN0 pin input
01: φT1
10: φT4
11: φT16
TB4FF0C1
R/W
1
0
0
TB4FF0C0
W*
0
0
1
1
1C3H
(RMW instructions are prohibited.)
TB4FF1 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
TB4FF0 inversion trigger
0: Disable
1: Enable
Invert when
UC4 is
loaded into
TB4CP1H/L.
Invert when
UC4 is
loaded into
TB4CP0H/L.
Invert when
UC4
matches
TB4RG1H/L.
Invert when
UC4
matches
TB4RG0H/L.
TB4FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
Note: Always read as 11.
–
1C8H
(RMW instruc-
W
tions are pro-
Undefined
hibited.)
–
1C9H
(RMW instruc-
W
tions are prohibited.)
Undefined
1CAH
–
(RMW instruc-
W
tions are prohibited.)
Undefined
1CBH
–
(RMW instruc-
W
tions are prohibited.)
Undefined
1CCH
R
–
TB4CP0L
Capture
register 0L
Undefined
–
TB4CP0H
Capture
register 0H
1CDH
R
Undefined
–
TB4CP1L
Capture
register 1L
1CEH
R
Undefined
–
TB4CP1H
Capture
register 1H
1CFH
R
Undefined
Page 299
2007-10-15
TMP91FW60
(8) UART / Serial channel
Symbol
SC0BUF
Name
Serial
channel 0
buffer
Address
7
6
5
4
3
2
1
0
200H
RB7 / TB7
RB6 / TB6
RB5 / TB5
RB4 / TB4
RB3 / TB3
RB2 / TB2
RB1 / TB1
RB0 / TB0
SCLKS
IOC
(RMW instruc-
R (Receiving) / W (Transmission)
tions are pro-
Undefined
hibited.)
RB8
EVEN
R
Undefined
SC0CR
Serial
channel 0
control
PE
R/W
0
OERR
PERR
FERR
R (Cleared to "0" when read)
0
0
0
0
201H
(RMW instructions are prohibited.)
Received
data bit8
Parity
addition
0: Disable
1: Enable
Parity
0: Odd
1: Even
TB8
CTSE
RXE
Overrun
error flag
0: Undetect error
1: Detect
error
Parity error
flag
0: Undetect error
1: Detect
error
WU
R/W
Framing
error flag
0: Undetect error
1: Detect
error
SM1
SM0
0
0
0
0
Edge
selection
for SCLK
pin (I/O
mode)
0: SCLK↑
1: SCLK↓
I/O interface input
clock
selection
0: Baud
rate generator
1: SCLK
pin input
SC1
SC0
0
0
R/W
0
SC0MOD0
Serial
channel 0
mode 0
202H
0
0
0
Handshake
function
0: Disable
1: Enable
Receive
function
0: Disable
1: Enable
Wakeup
function
0: Disable
1: Enable
–
BR0ADDE
BR0CK1
BR0CK0
0
0
0
0
Transmission data
bit8
Serial transmission
mode
00: I/O interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial transmission clock
(UART)
00: Timer TA0TRG
01: Baud rate generator
10: Internal clock fSYS
11: External clock
(SCLK input)
BR0S3
BR0S2
BR0S1
BR0S0
0
0
0
0
R/W
BR0CR
Baud ratel
control
203H
Always
write 0.
BR0ADD
Serial
channel 0
K setting
register
204H
+ (16 - K)/
16 division
0: Disable
1: Enable
–
–
–
–
–
–
–
–
–
–
–
–
SC0MOD1
205H
Setting of the divided frequency “N”
BR0K3
BR0K2
BR0K1
BR0K0
0
0
R/W
0
0
Sets frequency divisor “K”
(Divided by N + (16 - K)/16)
–
–
–
–
I2S0
FDPX0
–
–
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
–
R/W
Serial
channel 0
mode 1
Input clock selection for
baud rate generator
00: φT0
01: φT2
10: φT8
11: φT32
0
IDLE2
0: Stop
1: Run
Duplex
0: Half
1: Full
Page 300
–
–
–
–
2007-10-15
TMP91FW60
Symbol
Name
SC1BUF
Serial
channel 1
buffer
Address
7
6
5
208H
RB7 / TB7
RB6 / TB6
RB5 / TB5
(RMW instructions are pro-
2
1
0
RB4 / TB4
RB3 / TB3
RB2 / TB2
RB1 / TB1
RB0 / TB0
SCLKS
IOC
Undefined
hibited.)
EVEN
R
PE
R/W
Undefined
SC1CR
3
R (Receiving) / W (Transmission)
RB8
Serial
channel 1
control
4
0
OERR
PERR
FERR
R (Cleared to "0" when read)
0
0
0
0
209H
(RMW instructions are prohibited.)
Received
data bit8
Parity
addition
0: Disable
1: Enable
Parity
0: Odd
1: Even
TB8
CTSE
RXE
Overrun
error flag
0: Undetect error
1: Detect
error
Parity error
flag
0: Undetect error
1: Detect
error
WU
R/W
Framing
error flag
0: Undetect error
1: Detect
error
SM1
SM0
0
0
0
0
Edge
selection
for SCLK
pin (I/O
mode)
0: SCLK↑
1: SCLK↓
I/O interface input
clock
selection
0: Baud
rate generator
1: SCLK
pin input
SC1
SC0
0
0
R/W
0
SC1MOD0
Serial
channel 1
mode 0
20AH
Transmission data
bit8
–
0
0
0
Handshake
function
0: Disable
1: Enable
Receive
function
0: Disable
1: Enable
Wakeup
function
0: Disable
1: Enable
BR1ADDE
BR1CK1
BR1CK0
Serial transmission
mode
00: I/O interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial transmission clock
(UART)
00: Timer TA0TRG
01: Baud rate generator
10: Internal clock fSYS
11: External clock
(SCLK input)
BR1S3
BR1S2
BR1S1
BR1S0
0
0
0
0
R/W
0
BR1CR
Baud ratel
control
20BH
Always
write “0”.
BR1ADD
Serial
channel 1
K setting
register
20CH
0
+ (16 - K)/
16 division
0: Disable
1: Enable
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FDPX1
R/W
Serial
channel 1
mode 1
20DH
0
–
I2S1
SC1MOD1
0
Input clock selection for
baud rate generator
00: φT0
01: φT2
10: φT8
11: φT32
0
IDLE2
0: Stop
1: Run
0
Duplex
0: Half
1: Full
Setting of the divided frequency “N”
BR1K3
BR1K2
0
0
BR1K1
BR1K0
0
0
R/W
Sets frequency divisor “K”
(Divided by N + (16 - K)/16)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 301
2007-10-15
TMP91FW60
Symbol
Name
SC2BUF
Serial
channel 2
buffer
Address
7
6
5
210H
RB7 / TB7
RB6 / TB6
RB5 / TB5
(RMW instructions are pro-
2
1
0
RB4 / TB4
RB3 / TB3
RB2 / TB2
RB1 / TB1
RB0 / TB0
SCLKS
IOC
Undefined
hibited.)
EVEN
R
PE
R/W
Undefined
SC2CR
3
R (Receiving) / W (Transmission)
RB8
Serial
channel 2
control
4
0
OERR
PERR
FERR
R (Cleared to "0" when read)
0
0
0
0
211H
(RMW instructions are prohibited.)
Received
data bit8
Parity
addition
0: Disable
1: Enable
Parity
0: Odd
1: Even
TB8
CTSE
RXE
Overrun
error flag
0: Undetect error
1: Detect
error
Parity error
flag
0: Undetect error
1: Detect
error
WU
R/W
Framing
error flag
0: Undetect error
1: Detect
error
SM1
SM0
0
0
0
0
Edge
selection
for SCLK
pin (I/O
mode)
0: SCLK↑
1: SCLK↓
I/O interface input
clock
selection
0: Baud
rate generator
1: SCLK
pin input
SC1
SC0
0
0
R/W
0
SC2MOD0
Serial
channel 2
mode 0
212H
Transmission data
bit8
–
0
0
0
Handshake
function
0: Disable
1: Enable
Receive
function
0: Disable
1: Enable
Wakeup
function
0: Disable
1: Enable
BR2ADDE
BR2CK1
BR2CK0
Serial transmission
mode
00: I/O interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial transmission clock
(UART)
00: Timer TA0TRG
01: Baud rate generator
10: Internal clock fSYS
11: External clock
(SCLK input)
BR2S3
BR2S2
BR2S1
BR2S0
0
0
0
0
R/W
0
BR2CR
Baud ratel
control
213H
Always
write “0”.
BR2ADD
Serial
channel 2
K setting
register
214H
0
+ (16 - K)/
16 division
0: Disable
1: Enable
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FDPX2
R/W
Serial
channel 2
mode 1
215H
0
–
I2S2
SC2MOD1
0
Input clock selection for
baud rate generator
00: φT0
01: φT2
10: φT8
11: φT32
0
IDLE2
0: Stop
1: Run
0
Duplex
0: Half
1: Full
Setting of the divided frequency “N”
BR2K3
BR2K2
0
0
BR2K1
BR2K0
0
0
R/W
Sets frequency divisor “K”
(Divided by N + (16 - K)/16)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 302
2007-10-15
TMP91FW60
(9) I2C bus interface
Symbol
Name
Address
7
6
5
4
3
2
1
0
BC2
BC1
BC0
ACK
–
SCK2
SCK1
SWRMON
/SCK0
W
SBI0CR1
SBI0DBR
Serial bus
interface
control
register 1
SBI
buffer
register
240H
0
0
0
R/W
–
0
–
(RMW instructions are prohibited.)
241H
Number of transferred bits
000: 8 001: 1 010: 2 011: 3
100: 4 101: 5 110: 6 111: 7
DB7
DB6
DB5
(RMW instruc-
Acknowledge clock
0: Disable
1: Enable
–
DB4
DB3
W
0
R/W
0
0/1
<SCK2:0> at write
Internal serial clock selection and software reset monitor
000: 4 001: 5 010: 6 011: 7
100: 8 101: 9 110: 10 111:Reserved
<SWRMON> at read
0: During software reset
DB2
DB1
DB0
SA2
SA1
SA0
ALS
0
0
0
R (Receiving) / W (Transmission)
tions are pro-
Undefined
hibited.)
SA6
SA5
SA4
SA3
W
I2C0AR
I2C bus
address
register
242H
(RMW instruc-
0
0
0
0
0
tions are pro-
Address
recognition
0: Enable
1: Disable
hibited.)
Slave address selection for when device is operating as slave device
MST
TRX
BB
AL/
SBIM1
PIN
AAS/
SBIM0
AD0/
SWRST1
LRB/
SWRST0
0
0
0
GENERAL
CALL
detection
1: Detect
Last
receive bit
monitor
0: “0”
1: “1”
R/W
When read
SBI0SR
Serial bus
interface
status
register
0
0
0
243H
(RMW instructions are pro-
1
Bus status
monitor
0: Free
1: Busy[
INTSBI
request
monitor
0: Request
1: Cancel
Start/stop
condition
0: Start
condition
1: Stop
condition
Cancel
INTSBI
interrupt
request
0: –
1: Cancel
0
Arbitration
lost
detection
monitor
1: Detect
hibited.)
0: Slave
1: Master
When write
SBI0CR2
SBI0BR
0:Receiver
1:Transmit
Serial bus
interface
control
register 2
Serial bus
interface
baud rate
register
244H
hibited.)
W
R/W
–
–
–
0
0
–
–
–
Operation
in IDLE2
mode
0: Stop
1: Operate
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
Always
write “0”
SBI0EN
R/W
SBI0CR0
Serial bus
interface
control
register 0
10: I2C bus mode
11: Reserved
–
–
Software reset generate
Write “10” and “01”, then
an internal reset signal is
generated.
I2SBI0
tions are pro-
–
Serial bus interface
operating mode selection
00: Port mode
01: Reserved
–
(RMW instruc-
–
Slave
address
match
detection
monitor
1:Detect
–
–
–
–
R/W
–
–
0
Always
write “0”
R
247H
(RMW instructions are prohibited.)
0
SBI
operation
0: disable
1: enable
0
Always read "0".
Page 303
2007-10-15
TMP91FW60
Symbol
Name
Address
7
6
5
4
3
2
1
0
BC2
BC1
BC0
ACK
–
SCK2
SCK1
SCK0/
SWRMON
W
SBI1CR1
SBI1DBR
Serial bus
interface
control
register 1
SBI
buffer
register
248H
0
0
0
R/W
–
0
–
(RMW instructions are prohibited.)
249H
Number of transferred bits
000: 8 001: 1 010: 2 011: 3
100: 4 101: 5 110: 6 111: 7
DB7
DB6
DB5
(RMW instruc-
Acknowledge clock
0: Disable
1: Enable
–
DB4
DB3
W
0
R/W
0
0/1
<SCK2:0> at write
Internal serial clock selection and software reset monitor
000: 4 001: 5 010: 6 011: 7
100: 8 101: 9 110: 10 111:Reserved
<SWRMON> at read
0: During software reset
DB2
DB1
DB0
SA2
SA1
SA0
ALS
0
0
0
0
R (Receiving) / W (Transmission)
tions are pro-
ïsíË
hibited.)
SA6
SA5
SA4
SA3
0
0
0
0
W
I2C1AR
I2C bus
address
register
24AH
(RMW instructions are pro-
Address
recognition
0: Enable
1: Disable
hibited.)
Slave address selection for when device is operating as slave device
AL/
SBIM1
AAS/
SBIM0
AD0/
SWRST1
LRB/
SWRST0
1
0
0
0
0
Bus status
monitor
0: Free
1: Busy[
INTSBI
request
monitor
0: Request
1: Cancel
Arbitration
lost
detection
monitor
1: Detect
GENERAL
CALL
detection
1: Detect
Last
receive bit
monitor
0: “0”
1: “1”
Start/stop
condition
0: Start
condition
1: Stop
condition
Cancel
INTSBI
interrupt
request
0: –
1: Cancel
MST
TRX
BB
PIN
0
0
0
R/W
When read
SBI1SR
Serial bus
interface
status
register
24BH
(RMW instructions are prohibited.)
0: Slave
1: Master
When write
SBI1CR2
SBI1BR
0:Receiver
1:Transmit
Serial bus
interface
control
register 2
Serial bus
interface
baud rate
register
24CH
I2SBI1
–
–
–
–
–
–
R/W
–
–
–
–
–
R/W
0
0
tions are pro-
Always
write “0”
0
–
–
–
–
–
Operation
in IDLE2
mode
0: Stop
1: Operate
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
R/W
SBI1CR0
10: I2C bus mode
11: Reserved
Software reset generate
Write “10” and “01”, then
an internal reset signal is
generated.
–
SBI1EN
Serial bus
interface
control
register 0
Serial bus interface
operating mode selection
00: Port mode
01: Reserved
W
(RMW instruchibited.)
Slave
address
match
detection
monitor
1:Detect
Always
write “0”
R
24FH
(RMW instructions are prohibited.)
0
0
0
SBI
operation
0: disable
1: enable
0
0
Always read "0".
Page 304
2007-10-15
TMP91FW60
(10) AD converter
Symbol
Name
Address
7
6
5
ADRS
AMD
4
3
2
AINEN
1
0
0
0
SAIN
R/W
0
ADCCR1
AD
control
register 1
2B0H
0
AD conversion
start
0: 1: AD conversion
start
0
AD operating mode
00: AD operation
disable
01: single mode
10: Reserved
11: Repeat mode
EOCF
ADBF
RSEL
0
0
Analog
input control
0: disable
1: enable
Analog input channel select
0000: AN0 0100: AN4 1000: AN8 1100: AN12
0001: AN1 0101: AN5 1001: AN9 1101: AN13
0010: AN2 0110: AN6 1010: AN10 1110: AN14
0011: AN3 0111: AN7 1011: AN11 1111: AN15
I2AD
ACK
R
ADCCR2
ADCDRL
ADCDRH
When 10-bit
storing
mode
ADCDRH
When 8-bit
storing
mode
AD
control
register 2
2B1H
AD
result
register L
2B2H
0
R/W
0
0
0
AD conversion
end flag
0:Before or
during
conversion
1: Conversion completed
AD conversion
BUSY flag
0: During
stop of AD
conversion
1: During
AD conversion
Storing of
an AD
conversion result
0: 10bit
mode
1: 8bit
mode
AD07
AD06
AD05
0
1
1
0
0
AD conversion time select
IDLE2
control
0:Stop
1:Operation
1010: 78 / fc [s]
1011: 156 / fc [s]
1100: 312 / fc [s]
1101: 624 / fc [s]
1110: 1248 / fc [s]
AD04
AD03
AD02
AD01
AD00
R
0
0
0
0
0
0
0
0
–
–
–
–
–
–
AD09
AD08
R
AD
result
register H
0
0
0
0
0
0
0
0
AD09
AD08
AD07
AD06
AD05
AD04
AD03
AD02
0
0
0
0
2B3H
R
0
0
0
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(11) Watchdog timer
Symbol
Name
Address
7
6
5
WDTE
WDTP1
WDTP0
R/W
0
WDMOD
WDT
mode
register
0
0
4
3
2
1
0
I2WDT
RESCR
–
–
–
–
–
–
–
0
0
–
IDLE2
0: Stop
1: Operate
1: Intermally connects WDT
out to the
reset pin
R/W
Select detecting time
300H
WDT
control
1: Enable
00: 215/fSYS
01: 217/fSYS
10:
–
219/fSYS
11: 221/fSYS
0
Always
write “0”.
–
301H
WDCR
WDT
control
(RMW instruc-
W
tions are pro-
–
hibited.)
B1H: WDT disable code
4EH: WDT clear code
(12) Special timer for CLOCK
Symbol
RTCCR
Name
RTC
control
register
Address
7
6
5
4
3
2
1
0
RTCSEL1
RTCSEL0
RTCRUN
–
–
–
–
–
R/W
–
–
–
–
0
–
–
–
–
310H
R/W
0
0
0
14
00: 2 /fs
Always
write “0”.
–
–
–
–
01: 213/fs
10: 212/fs
0: Stop &
clear
1: Count
11: 211/fs
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(13) Program patch logic
Symbol
ROMCMP00
Name
Address
compare
register 00
Address
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
W
(RMW instructions are pro-
0
0
0
–
0
0
0
0
–
hibited.)
Target ROM address (Lower 7 bits)
ROMC15
ROMCMP01
Address
compare
register 01
–
400H
ROMC14
ROMC13
ROMC12
–
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
ROMC02
ROMC01
401H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Middle 8 bits)
ROMC23
ROMCMP02
Address
compare
register 02
ROMC22
ROMC21
ROMC20
402H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Upper 8 bits)
ROMS07
ROMSUB0L
Address
substitution
register 0L
ROMS06
ROMS05
ROMS04
404H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Lower 8 bits)
ROMS15
ROMSUB0H
Address
substitution
register 0H
ROMS14
ROMS13
ROMS12
405H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Upper 8 bits)
ROMC07
ROMCMP10
Address
compare
register 10
ROMC06
ROMC05
ROMC04
ROMC03
W
(RMW instructions are pro-
0
0
0
–
0
0
0
0
–
hibited.)
Target ROM address (Lower 7 bits)
ROMC15
ROMCMP11
Address
compare
register 11
–
408H
ROMC14
ROMC13
ROMC12
–
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
409H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Middle 8 bits)
ROMC23
ROMCMP12
Address
compare
register 12
ROMC22
ROMC21
ROMC20
40AH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Upper 8 bits)
ROMS07
ROMSUB1L
Address
substitution
register 1L
ROMS06
ROMS05
ROMS04
40CH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Lower 8 bits)
ROMS15
ROMSUB1H
Address
substitution
register 1H
ROMS14
ROMS13
ROMS12
40DH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Upper 8 bits)
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Symbol
ROMCMP20
Name
Address
compare
register 20
Address
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
W
(RMW instructions are pro-
0
0
0
–
0
0
0
0
–
hibited.)
Target ROM address (Lower 7 bits)
ROMC15
ROMCMP21
Address
compare
register 21
–
410H
ROMC14
ROMC13
ROMC12
–
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
ROMC02
ROMC01
411H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Middle 8 bits)
ROMC23
ROMCMP22
Address
compare
register 22
ROMC22
ROMC21
ROMC20
412H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Upper 8 bits)
ROMS07
ROMSUB2L
Address
substitution
register 2L
ROMS06
ROMS05
ROMS04
414H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Lower 8 bits)
ROMS15
ROMSUB2H
Address
substitution
register 2H
ROMS14
ROMS13
ROMS12
415H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Upper 8 bits)
ROMC07
ROMCMP30
Address
compare
register 30
ROMC06
ROMC05
ROMC04
ROMC03
W
(RMW instructions are pro-
0
0
0
–
0
0
0
0
–
hibited.)
Target ROM address (Lower 7 bits)
ROMC15
ROMCMP31
Address
compare
register 31
–
418H
ROMC14
ROMC13
ROMC12
–
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
419H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Middle 8 bits)
ROMC23
ROMCMP32
Address
compare
register 32
ROMC22
ROMC21
ROMC20
41AH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Upper 8 bits)
ROMS07
ROMSUB3L
Address
substitution
register 3L
ROMS06
ROMS05
ROMS04
41CH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Lower 8 bits)
ROMS15
ROMSUB3H
Address
substitution
register 3H
ROMS14
ROMS13
ROMS12
41DH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Upper 8 bits)
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Symbol
ROMCMP40
Name
Address
compare
register 40
Address
7
6
5
4
3
2
1
0
ROMC07
ROMC06
ROMC05
ROMC04
ROMC03
ROMC02
ROMC01
W
(RMW instructions are pro-
0
0
0
–
0
0
0
0
–
hibited.)
Target ROM address (Lower 7 bits)
ROMC15
ROMCMP41
Address
compare
register 41
–
420H
ROMC14
ROMC13
ROMC12
–
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
ROMC02
ROMC01
421H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Middle 8 bits)
ROMC23
ROMCMP42
Address
compare
register 22
ROMC22
ROMC21
ROMC20
422H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Upper 8 bits)
ROMS07
ROMSUB4L
Address
substitution
register 4L
ROMS06
ROMS05
ROMS04
424H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Lower 8 bits)
ROMS15
ROMSUB4H
Address
substitution
register 4H
ROMS14
ROMS13
ROMS12
425H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Upper 8 bits)
ROMC07
ROMCMP50
Address
compare
register 50
ROMC06
ROMC05
ROMC04
ROMC03
W
(RMW instructions are pro-
0
0
0
–
0
0
0
0
–
hibited.)
Target ROM address (Lower 7 bits)
ROMC15
ROMCMP51
Address
compare
register 51
–
428H
ROMC14
ROMC13
ROMC12
–
ROMC11
ROMC10
ROMC09
ROMC08
0
0
0
0
ROMC19
ROMC18
ROMC17
ROMC16
0
0
0
0
ROMS03
ROMS02
ROMS01
ROMS00
0
0
0
0
ROMS11
ROMS10
ROMS09
ROMS08
0
0
0
0
429H
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Middle 8 bits)
ROMC23
ROMCMP52
Address
compare
register 52
ROMC22
ROMC21
ROMC20
42AH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Target ROM address (Upper 8 bits)
ROMS07
ROMSUB5L
Address
substitution
register 5L
ROMS06
ROMS05
ROMS04
42CH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Lower 8 bits)
ROMS15
ROMSUB5H
Address
substitution
register 5H
ROMS14
ROMS13
ROMS12
42DH
W
(RMW instructions are pro-
0
0
0
0
hibited.)
Patch code (Upper 8 bits)
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17. I/O Port Equivalent-circuit Diagrams
• How to read circuit diagrams
The circuit diagrams in this chapter are drawn using the same gate symbols as for the 74HCxx series standard CMOS logic ICs.
The signal named STOP has a unique function. This signal goes active-high if the CPU sets the HALT bit
when the HALTM[1:0] field in the SYSCR2 register is programmed to 01 (e.g., STOP mode) and the drive
enable (DRVE) bit in the same register is cleared. If the DRVE bit is set, the STOP signal remains inactive (at
logic 0).
• The input protection circuit has a resistor in the range of several tens to several hundreds of ohms.
17.1 Equivalent circuit Diagrams
1. P0 (AD0 to AD7), P1 (AD8 to AD15, A8 to A15), P2 (A16 to A23, A0 to A7)
VCC
1WVRWVFCVC
P-ch
1WVRWVGPCDNG
STOP
N-ch
+PRWV1WVRWV
+PRWVFCVC
+PRWVGPCDNG
2. PZ0 (RD), PZ1 (WR)
Vcc
1WVRWVFCVC
P-ch
1WVRWV
STOP
N-ch
3. P5 (AN0 to AN7), P6 (AN8 to AN15)
#PCNQIKPRWV
EJCPPGNUGNGEV
#PCNQIKPRWV
VCC
1WVRWVFCVC
P-ch
1WVRWVGPCDNG
STOP
N-ch
+PRWVFCVC
+PRWV1WVRWV
+PRWVGPCDNG
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4. PZ2 (HWR), PZ3 (R/W), P44(ALE)
Vcc
1WVRWVFCVC
P-ch
1WVRWVGPCDNG
STOP
Vcc
2TQITCOOCDNG
RWNNWRTGUKUVQT
N-ch
+PRWV1WVRWV
+PRWVFCVC
+PRWVGPCDNG
5. P40(CS0/SCOUT), P41(CS1/TXD2), P42(CS2/RXD2), P43(CS3/SCLK2/CTS2)
Vcc
1WVRWVFCVC
P-ch
1WVRWVGPCDNG
STOP
Vcc
2TQITCOOCDNG
RWNNWRTGUKUVQT
N-ch
+PRWV1WVRWV
+PRWVFCVC
+PRWVGPCDNG
6. P75 (INT0)
Vcc
1WVRWVFCVC
P-ch
1WVRWVGPCDNG
STOP
N-ch
+PRWV1WVRWV
+PRWVFCVC
UEJOKVVVTKIIGT
7. P32(WAIT/TB3OUT0), P33(TB3OUT1), P70(TA0IN), P71(TA1OUT), P72(TA3OUT), P73(TA4IN),
P74(TA5OUT), P80 to P87,P91(RXD0), P92(SCLK0/CTS0), P94(RXD1), P95(SCLK1/CTS1), PA0 to
PA3,PB2(TB4OUT0), PB3(TB4OUT1)
VCC
1WVRWVFCVC
P-ch
1WVRWVGPCDNG
STOP
N-ch
+PRWV1WVRWV
+PRWVFCVC
+PRWVGPCDNG
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8. P30(TB3IN0/INT3/SDA0), P31(TB3IN1/INT4/SCL0), P90(TXD0), P93(TXD1), PB0(TB4IN0/INT9/
SDA1), PB1(TB4IN1/INT10/SCL1)
Vcc
1WVRWVFCVC
P-ch
1RGPFTCKP
QWVRWVGPCDNG
N-ch
STOP
+PRWV1WVRWV
+PRWVFCVC
+PRWVGPCDNG
9. P96 (XT1), P97 (XT2)
+PRWVGPCDNG
+PRWVFCVC
%NQEM
Vcc
1WVRWVFCVC
1UEKNNCVQTEKTEWKV
P-ch
P97(XT2)
1WVRWVGPCDNG
࡞
N-ch
+PRWVGPCDNG
+PRWVFCVC
Vcc
1WVRWVFCVC
P-ch
P96(XT1)
1WVRWVGPCDNG
N-ch
STOP
.QYHTGSWGPE[QUEKNNCVQTGPCDNG
10. NMI
+PRWV
NMI
5EJOKVVVTKIIGT
11. AM0 to AM1
+PRWV
12. RESET
Vcc
P-ch
+PRWV
4GUGV
5EJOKVVVTKIIGT
WDTOUT
4GUGVGPCDNG
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13. X1, X2
%NQEM
1UEKNNCVQTEKTEWKV
X2
*KIJHTGSWGPE[
QUEKNNCVQTGPCDNG
P-ch
N-ch
X1
14. VREFH, AVSS
VREFON
P-ch
VREFH
.CFFGTTGUKUVQTU
AVSS
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18. Points to Note and Restrictions
18.1 Notation
a. The notation for built-in I/O registers is as follows register symbol <Bit symbol>
e.g.) TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN.
b. Read-modify-write instructions
An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction.
Example 1:
SET
3, (TA01RUN) ... Set bit3 of TA01RUN.
Example 2:
INC
1, (100H) ... Increment the data at 100H.
•　Examples of read-modify-write instructions on the TLCS-900
Exchange instruction
EX
(mem), R
Arithmetic operations
ADD
(mem), R/#
ADC
(mem), R/#
SUB
(mem), R/#
SBC
(mem), R/#
INC
#3, (mem)
DEC
#3, (mem)
OR
(mem), R/#
Logic operations
AND
(mem), R/#
XOR
(mem), R/#
Bit manipulation operations
STCF
#3/A, (mem)
RES
#3, (mem)
SET
#3, (mem)
CHG
#3, (mem)
TSET
#3, (mem)
Rotate and shift operations
RLC
(mem)
RRC
(mem)
RL
(mem)
RR
(mem)
SLA
(mem)
SRA
(mem)
SLL
(mem)
SRL
(mem)
RLD
(mem)
RRD
(mem)
c. fOSCH, fc, fs, fFPH, fSYS and one state
The clock frequency input on pins X1 and 2 is called fOSCH or fc.
The clock selected by SYSCR1<SYSCK> is called fFPH. The clock frequency give by fFPH divided by
2 is called fSYS.
One cycle of fSYS is referred to as one state.
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18.2 Points of note
a. AM0 and AM1 pins
This pin is connected to the DVcc pin. Do not alter the level when the pin is active.
b. EMU0 and EMU1 pins
Open pins.
c. HALT mode (IDLE1)
When IDLE1 mode (in which oscillator operation only occurs) is used, set RTCCR<RTCRUN> to 0
stop the Special timer for CLOCK before the HALT instructions is executed.
d. Warm-up counter
The warm-up counter operates when STOP mode is released, even if the system is using an external
oscillator. As a result a time equivalent to the warm-up time elapses between input of the release request
and output of the system clock.
e. Programmable pull-up/pull-down resistances
The programmable pull-up/pull-down resistor can be turned ON/OFF by a program when the ports are
set for use as input ports. When the ports are set for use as output ports, they cannot be turned ON/OFF by
a program.
The data registers (e.g., P4) are used to turn the pull-up/pull-down resistors ON/OFF. Consequently
read-modify-write instructions are prohibited.
f. Watchdog timer
The watchdog timer starts operation immediately after a reset is released. When the watchdog timer is
not to be used, disable it.
When the bus is released, neither internal memory nor internal I/O can be accessed. However, the internal I/O continues to operate. Hence the watchdog timer continues to run. Therefore be careful about the
bus releasing time and set the detection timer of watchdog timer.
g. CPU (Micro DMA)
Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers in the CPU
(e.g., the transfer source address register (DMASn)).
h. Undefined SFR
The value of an undefined bit in an SFR is undefined when read.
i. POP SR instruction
Please execute the POP SR instruction during DI condition.
j. Clocks for serial channels (SIO)
As for the serial channels SIO0, SIO1 and SIO2, a baud rate generator is unavailable as an input clock
of an I/O interface and a clock for a serial transfer if a prescaler clock is set to fc/16 when
SYSCR0<PRCK1> is "1".
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19. Package Dimension
LQFP100-P-1414-0.50F
Unit: mm
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QFP100-P-1420-0.65A
Unit: mm
Page 317
2007-10-15
Postscript
This is a technical document that describes the operating functions and electrical specifications of the 16bit microcontroller series TLCS-900/L1 (LSI).
Toshiba provides a variety of development tools and basic software to enable efficient software
development.
These development tools have specifications that support advances in microcomputer hardware (LSI) and
can be used extensively. Both the hardware and software are supported continuously with version updates.
The recent advances in CMOS LSI production technology have been phenomenal and microcomputer
systems for LSI design are constantly being improved. The products described in this document may also
be revised in the future. Be sure to check the latest specifications before using.
Toshiba is developing highly integrated, high-performance microcomputers using advanced MOS
production technology and especially well proven CMOS technology.
We are prepared to meet the requests for custom packaging for a variety of application areas.
We are confident that our products can satisfy your application needs now and in the future.