ALSC ASM5P2304BF-2H-08-SR 3.3v zero delay buffer Datasheet

ASM5P2304B
September 2005
rev 0.5
3.3V Zero Delay Buffer
Features
ƒ
has an on-chip PLL, which locks to an input clock,
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
ƒ
ƒ
Multiple low-skew outputs.
ƒ
ƒ
Output-output skew less than 200pS.
ƒ
Device-device skew less than 500pS.
ƒ
Two banks of four outputs.
input-to-output
propagation
delay
is
skew is guaranteed to be less than 200pS.
The ASM5P2304B has two banks of two outputs each.
Multiple ASM5P2304B devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
Less than 200pS Cycle-to-Cycle jitter
500pS.
(-1, -1H, -2, -2H).
ƒ
The
guaranteed to be less than 250pS, and the output-to-output
Configurations Table”.
Input frequency range: 4MHz to 20MHz
be driven to FBK pin, and can be obtained from one of the
outputs.
Multiple configurations - Refer “ASM5P2304B
ƒ
presented on the REF pin. The PLL feedback is required to
Available in space saving, 8-pin 150 mil SOIC
The
Package.
ASM5P2304B
is
available
in
two
different
configurations (Refer “ASM5P2304B Configurations Table).
ƒ
3.3V operation.
ƒ
Advanced 0.35µ CMOS technology.
ƒ
Industrial temperature available.
The ASM5P2304B-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2304B-1H is the high-drive
Functional Description
version of the -1 and the rise and fall times on this device
ASM5P2304B is a versatile, 3.3V zero-delay buffer
obtain REF and 1/2X or 2X frequencies on each output
designed
bank. The exact configuration and output frequencies
to
distribute
are much faster. The ASM5P2304B-2 allows the user to
high-speed
clocks
in
PC,
workstation, datacom, telecom and other high-performance
depend on which output drives the feedback pin.
applications. It is available in an 8 pin package. The part
Block Diagram
FBK
CLKA1
REF
PLL
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM5P2304B
September 2005
rev 0.5
ASM5P2304B Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P2304B-1
Bank A or Bank B
Reference
Reference
ASM5P2304B-1H
Bank A or Bank B
Reference
Reference
ASM5P2304B-2
Bank A
Reference
Reference /2
ASM5P2304B-2
Bank B
2 X Reference
Reference
ASM5P2304B-2H
Bank A
Reference
Reference /2
ASM5P2304B-2H
Bank B
2 X Reference
Reference
Zero Delay and Skew Control
For applications requiring zero input-output delay, all outputs must be equally loaded.
1500
REF-Input to CLKA/CLKB Delay (pS)
1000
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
To close the feedback loop of the ASM5P2304B, the FBK
output delay, all outputs including the one providing
pin can be driven from any of the four available output pins.
feedback should be equally loaded. If input-output delay
The output driving the FBK pin will be driving a total load of
adjustments are required, use the above graph to calculate
7pF plus any additional load that it drives. The relative
loading differences between the feedback output and
loading of this output (with respect to the remaining
remaining outputs. For zero output-output skew, be sure to
outputs) can adjust the input output delay. This is shown in
load outputs equally.
the above graph. For applications requiring zero input-
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 13
ASM5P2304B
September 2005
rev 0.5
Pin Configuration
REF
1
CLKA1
2
CLKA2
GND
8
FBK
7
VDD
3
6
CLKB2
4
5
CLKB1
ASM5P2304B
Pin Description for ASM5P2304B
Pin #
Pin Name
Description
1
REF1
2
CLKA12
Buffered clock output, bank A
3
CLKA22
Buffered clock output, bank A
4
GND
5
CLKB12
Buffered clock output, bank B
6
CLKB2 2
Buffered clock output, bank B
7
VDD
3.3V supply
8
FBK
PLL feedback input
Input reference frequency, 5V tolerant input
Ground
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 13
ASM5P2304B
September 2005
rev 0.5
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
-0.5
+7.0
V
DC Input Voltage (Except REF)
-0.5
VDD + 0.5
V
DC Input Voltage (REF)
-0.5
7
V
Storage Temperature
-65
+150
°C
Max. Soldering Temperature (10 sec)
260
°C
Junction Temperature
150
°C
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2000
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
Operating Conditions for ASM5P2304B Commercial Temperature Devices
Parameter
Description
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, from 4MHz to 20MHz
CIN
Min
Max
Unit
3.0
3.6
V
0
70
°C
30
pF
7
pF
3
Input Capacitance
Electrical Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
50.0
µA
IIH
Input HIGH Current
VIN = VDD
100.0
µA
VOL
Output LOW Voltage4
IOL = 8mA (-1, -2)
IOH = 12mA (-1H, -2H)
0.4
V
VOH
Output HIGH Voltage4
IOL = -8mA (-1, -2)
IOH = -12mA (-1H, -2H)
IDD
Supply Current
Unloaded outputs, 20MHz REF (-1,-1H, -2,-2H)
2.0
V
2.4
V
10
Note:
3. Applies to both Ref Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 13
mA
ASM5P2304B
September 2005
rev 0.5
Switching Characteristics for ASM5P2304B Commercial Temperature Devices
Parameter
Description
1/t1
Output Frequency
5
Duty Cycle = (t2 / t1) * 100
(-1, -2, -1H, -2H)
5
Duty Cycle = (t2 / t1) * 100
(-1, -2,-1H, -2H)
5
Output Rise Time
(-1, -2)
5
Output Rise Time
(-1, -2)
5
Output Rise Time
(-1H, -2H)
5
Output Fall Time
(-1, -2)
5
Output Fall Time
(-1, -2)
5
Output Fall Time
(-1H, -2H)
Output-to-output skew on same bank
(-1, -2)
Output-to-output skew (-1H, -2H)
Output bank A -to- output bank B skew
(-1, -2H)
Output bank A to output bank b skew
(-2)
Delay, REF Rising Edge to FBK Rising
5
Edge
30pF load, -1,-1H,-2, -2H devices
Measured at 1.4V, FOUT = 20MHz
30pF load
Measured at 1.4V, FOUT = <20MHz
15pF load
Measured between 0.8V and 2.0V
30pF load
Measured between 0.8V and 2.0V
15pF load
Measured between 0.8V and 2.0V
30pF load
Measured between 2.0V and 0.8V
30pF load
Measured between 2.0V and 0.8V
15pF load
Measured between 2.0V and 0.8V
30pF load
t7
Device-to-Device Skew 5
t8
Output Slew Rate5
Measured at VDD/2 on the FBK pins of
the device
Measured between 0.8V and 2.0V using
Test Circuit #2
Measured at 20MHz, loaded outputs,
15pF load
Measured at 20MHz, loaded outputs,
30pF load
Measured at 20MHz, loaded outputs,
15pF load
Measured at 20MHz, loaded outputs,
30pF load
Measured at 20MHz, loaded outputs,
15pF load
Stable power supply, valid clock
presented on REF and FBK pins
t3
t3
t3
t4
t4
t4
t5
t6
tJ
tJ
tLOCK
Cycle-to-cycle jitter 5
(-1, -1H, -2H)
Cycle-to-cycle jitter 5
(-2)
PLL Lock Time 5
Test Conditions
Min Typ Max Unit
4
20
MHz
40.0
50.0
60.0
%
45.0
50.0
55.0
%
2.20
nS
1.50
nS
1.50
nS
2.20
nS
1.50
nS
1.25
nS
All outputs equally loaded
200
All outputs equally loaded
200
All outputs equally loaded
200
All outputs equally loaded
400
Measured at VDD /2
0
±250
pS
0
500
pS
1
V/nS
175
200
400
pS
375
1.0
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Notice: The information in this document is subject to change without notice.
pS
100
Note:
3.3V Zero Delay Buffer
pS
5 of 13
mS
ASM5P2304B
September 2005
rev 0.5
Operating Conditions for ASM5I2304B Industrial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
-40
85
°C
CL
Load Capacitance, from 4MHz to 20MHz
30
pF
7
pF
CIN
6
Input Capacitance
Note:
6. Applies to both Ref Clock and FBK.
Electrical Characteristics for ASM5I2304B Industrial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
50.0
µA
IIH
Input HIGH Current
VIN = VDD
100.0
µA
VOL
Output LOW Voltage7
IOL = 8mA (-1, -2)
IOH = 12mA (-1H, -2H)
0.4
V
VOH
Output HIGH Voltage7
IOL = -8mA (-1, -2)
IOH = -12mA (-1H, -2H)
IDD
Supply Current
Unloaded outputs, 20MHz REF
(-1, -1H, -2, -2H)
2.0
V
2.4
V
10
Note:
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
6 of 13
mA
ASM5P2304B
September 2005
rev 0.5
Switching Characteristics for ASM5I2304B Industrial Temperature Devices
All parameters are specified with loaded outputs
Parameter
Description
t1
Output Frequency
8
Duty Cycle = (t2 / t1) * 100
(-1, -2, -1H, -2H)
8
Duty Cycle = (t2 / t1) * 100
(-1, -2, -1H, -2H)
8
Output Rise Time
(-1, -2)
8
Output Rise Time
(-1, -2)
8
Output Rise Time
(-1H, -2H)
8
Output Fall Time
(-1, -2)
8
Output Fall Time
(-1, -2)
8
Output Fall Time
(-1H, -2H)
Output-to-output skew on same bank
(-1, -2)8
Output-to-output skew
(-1H, -2H)
Output bank A -to- output bank B skew
(-1, -2H)
Output bank A -to- output bank B skew
(-2)
Delay, REF Rising Edge to FBK Rising
8
Edge
30pF load,-1, -1H,-2, -2H devices
Measured at 1.4V, FOUT = <20MHz
30pF load
Measured at 1.4V, FOUT = <20MHz
15pF load
Measured between 0.8V and 2.0V
30pF load
Measured between 0.8V and 2.0V
15pF load
Measured between 0.8V and 2.0V
30pF load
Measured between 2.0V and 0.8V
30pF load
Measured between 2.0V and 0.8V
15pF load
Measured between 2.0V and 0.8V
30pF load
t7
Device-to-Device Skew 8
t8
Output Slew Rate8
Measured at VDD/2 on the FBK pins of the
device
Measured between 0.8V and 2.0V using
Test Circuit #2
Measured at 20MHz, loaded outputs,
15pF load
Measured at 20MHz, loaded outputs,
30pF load
Measured at 20MHz, loaded outputs,
15pF load
Measured at 20MHz, loaded outputs,
30pF load
Measured at 20MHz, loaded outputs,
15pF load
Stable power supply, valid clock presented
on REF and FBK pins
t3
t3
t3
t4
t4
t4
t5
t6
tJ
tJ
tLOCK
Cycle-to-cycle jitter 8
(-1, -1H, -2H)
Cycle-to-cycle jitter8
(-2)
PLL Lock Time8
Test Conditions
Min Typ Max Unit
4
20
MHz
40.0 50.0 60.0
%
45.0 50.0 55.0
%
2.50
nS
1.50
nS
1.50
nS
2.50
nS
1.50
nS
1.25
ns
All outputs equally loaded
200
All outputs equally loaded
200
All outputs equally loaded
200
All outputs equally loaded
400
pS
Measured at VDD /2
0
±250 pS
0
500
1
V/nS
180
200
400
pS
380
1.0
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Notice: The information in this document is subject to change without notice.
pS
100
Note:
3.3V Zero Delay Buffer
pS
7 of 13
mS
ASM5P2304B
September 2005
rev 0.5
Switching Waveforms
Duty Cycle Timing
t1
t
2
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
OUTPUT
2.0 V
0.8 V
2.0 V
0.8 V
3.3 V
0V
t4
t3
Output - Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Input - Output Propagation Delay
VDD /2
INPUT
VDD /2
OUTPUT
t6
Device - Device Skew
CLKOUT, Device 1
V DD /2
V DD /2
CLKOUT, Device 2
t
7
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
8 of 13
ASM5P2304B
September 2005
rev 0.5
Test Circuits
TEST CIRCUIT # 1
TEST CIRCUIT # 2
VDD
0.1uF
VDD
CLKOUT
CLOAD
VDD
0.1uF
0.1uF
OUTPUTS
GND
GND
1KΩ
OUTPUTS
1KΩ
VDD
0.1uF
GND
GND
For parameter t8 (output skew rate) on -1H devices
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
9 of 13
10pF
ASM5P2304B
September 2005
rev 0.5
Package Information
8-lead (150-mil) SOIC Package
H
E
D
A2
A
C
A1
D
θ
e
L
B
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A1
0.004
0.010
0.10
0.25
A
0.053
0.069
1.35
1.75
A2
0.049
0.059
1.25
1.50
B
0.012
0.020
0.31
0.51
C
0.007
0.010
0.18
0.25
D
0.193 BSC
4.90 BSC
E
0.154 BSC
3.91 BSC
e
0.050 BSC
1.27 BSC
H
0.236 BSC
6.00 BSC
L
0.016
0.050
0.41
1.27
θ
0°
8°
0°
8°
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
10 of 13
ASM5P2304B
September 2005
rev 0.5
Ordering Codes
Ordering Code
Marking
Package Type
Operating Range
ASM5P2304B-1-08-SR
5P2304B-1
8-pin 150-mil SOIC-TAPE & REEL
Commercial
ASM5P2304B-1-08-ST
5P2304B-1
8-pin 150-mil SOIC-TUBE
Commercial
ASM5I2304B-1-08-SR
5I2304B-1
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I2304B-1-08-ST
5I2304B-1
8-pin 150-mil SOIC-TUBE
Industrial
ASM5P2304B-1H-08-SR
5P2304B-1H
8-pin 150-mil SOIC-TAPE & REEL
Commercial
ASM5P2304B-1H-08-ST
5P2304B-1H
8-pin 150-mil SOIC-TUBE
Commercial
ASM5I2304B-1H-08-SR
5I2304B-1H
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I2304B-1H-08-ST
5I2304B-1H
8-pin 150-mil SOIC-TUBE
Industrial
ASM5P2304B-2-08-SR
5P2304B-2
8-pin 150-mil SOIC-TAPE & REEL
Commercial
ASM5P2304B-2-08-ST
5P2304B-2
8-pin 150-mil SOIC-TUBE
Commercial
ASM5I2304B-2-08-SR
5I2304B-2
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I2304B-2-08-ST
5I2304B-2
8-pin 150-mil SOIC-TUBE
Industrial
ASM5P2304B-2H-08-SR
5P2304B-2H
8-pin 150-mil SOIC-TAPE & REEL
Commercial
ASM5P2304B-2H-08-ST
5P2304B-2H
8-pin 150-mil SOIC-TUBE
Commercial
ASM5I2304B-2H-08-SR
5I2304B-2H
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I2304B-2H-08-ST
5I2304B-2H
8-pin 150-mil SOIC-TUBE
Industrial
ASM5P2304BF-1-08-SR
5P2304BF-1
8-pin 150-mil SOIC-TAPE & REEL, Pb free
Commercial
ASM5P2304BF-1-08-ST
5P2304BF-1
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
ASM5I2304BF-1-08-SR
5I2304BF-1
8-pin 150-mil SOIC-TAPE & REEL, Pb free
Industrial
ASM5I2304BF-1-08-ST
5I2304BF-1
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
ASM5P2304BF-1H-08-SR
5P2304BF-1H
8-pin 150-mil SOIC-TAPE & REEL, Pb free
Commercial
ASM5P2304BF-1H-08-ST
5P2304BF-1H
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
ASM5I2304BF-1H-08-SR
5I2304BF-1H
8-pin 150-mil SOIC-TAPE & REEL, Pb free
Industrial
ASM5I2304BF-1H-08-ST
5I2304BF-1H
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
ASM5P2304BF-2-08-SR
5P2304BF-2
8-pin 150-mil SOIC-TAPE & REEL, Pb free
Commercial
ASM5P2304BF-2-08-ST
5P2304BF-2
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
ASM5I2304BF-2-08-SR
5I2304BF-2
8-pin 150-mil SOIC-TAPE & REEL, Pb free
Industrial
ASM5I2304BF-2-08-ST
5I2304BF-2
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
ASM5P2304BF-2H-08-SR
5P2304BF-2H
8-pin 150-mil SOIC-TAPE & REEL, Pb free
Commercial
ASM5P2304BF-2H-08-ST
5P2304BF-2H
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
ASM5I2304BF-2H-08-SR
5I2304BF-2H
8-pin 150-mil SOIC-TAPE & REEL, Pb free
Industrial
ASM5I2304BF-2H-08-ST
5I2304BF-2H
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
ASM5P2304BG-1-08-SR
5P2304BG-1
8-pin 150-mil SOIC-TAPE & REEL, Green
Commercial
ASM5P2304BG-1-08-ST
5P2304BG-1
8-pin 150-mil SOIC-TUBE, Green
Commercial
ASM5I2304BG-1-08-SR
5I2304BG-1
8-pin 150-mil SOIC-TAPE & REEL, Green
Industrial
ASM5I2304BG-1-08-ST
5I2304BG-1
8-pin 150-mil SOIC-TUBE, Green
Industrial
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 13
ASM5P2304B
September 2005
rev 0.5
Ordering Codes (cont’d)
Ordering Code
Marking
Package Type
Operating Range
ASM5P2304BG-1H-08-SR
5P2304BG-1H
8-pin 150-mil SOIC-TAPE & REEL, Green
Commercial
ASM5P2304BG-1H-08-ST
5P2304BG-1H
8-pin 150-mil SOIC-TUBE, Green
Commercial
ASM5I2304BG-1H-08-SR
5I2304BG-1H
8-pin 150-mil SOIC-TAPE & REEL
Industrial
ASM5I2304BG-1H-08-ST
5I2304BG-1H
8-pin 150-mil SOIC-TUBE, Green
Industrial
ASM5P2304BG-2-08-SR
5P2304BG-2
8-pin 150-mil SOIC-TAPE & REEL, Green
Commercial
ASM5P2304BG-2-08-ST
5P2304BG-2
8-pin 150-mil SOIC-TUBE, Green
Commercial
ASM5I2304BG-2-08-SR
5I2304BG-2
8-pin 150-mil SOIC-TAPE & REEL, Green
Industrial
ASM5I2304BG-2-08-ST
5I2304BG-2
8-pin 150-mil SOIC-TUBE, Green
Industrial
ASM5P2304BG-2H-08-SR
5P2304BG-2H
8-pin 150-mil SOIC-TAPE & REEL, Green
Commercial
ASM5P2304BG-2H-08-ST
5P2304BG-2H
8-pin 150-mil SOIC-TUBE, Green
Commercial
ASM5I2304BG-2H-08-SR
5I2304BG-2H
8-pin 150-mil SOIC-TAPE & REEL, Green
Industrial
ASM5I2304BG-2H-08-ST
5I2304BG-2H
8-pin 150-mil SOIC-TUBE, Green
Industrial
Device Ordering Information
A S M 5 P 2 3 0 4 B F - 0 8 - S R
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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ASM5P2304B
September 2005
rev 0.5
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5P2304B
Document Version: 0.5
Alliance Semiconductor Corporation
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Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semicon
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
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All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
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components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
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assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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