TH50VSF2580/2581AASB TENTATIVE TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE DESCRIPTION The TH50VSF2580/2581AASB is a mixed multi-chip package containing a 4,194,304-bit full CMOS SRAM and a 33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration. The power supply for the TH50VSF2580/2581AASB can range from 2.7 V to 3.6 V. The TH50VSF2580/2581AASB can perform simultaneous read/write operations on its flash memory and is available in a 69-pin BGA package, making it suitable for a variety of applications. FEATURES • • • • • • Power supply voltage VCCs = 2.7 V~3.6 V VCCf = 2.7 V~3.6 V Data retention supply voltage VCCs = 1.5 V~3.6 V Current consumption Operating: 45 mA maximum (CMOS level) Standby: 7 µA maximum (SRAM CMOS level) Standby: 10 µA maximum (flash CMOS level) Block erase architecture for flash memory 8 blocks of 8 Kbytes 63 blocks of 64 Kbytes Organization Flash Memory • • CIOF CIOS SRAM VCC VCC 2,097,152 words of 16 bits VCC VSS 2,097,152 words of 16 bits 524,288 words of 8 bits VSS VSS 4,194,304 words of 8 bits 524,288 words of 8 bits • 262,144 words of 16 bits • PIN ASSIGNMENT (TOP VIEW) Function mode control for flash memory Compatible with JEDEC-standard commands Flash memory functions Simultaneous Read/Write operations Auto-Program Auto Chip Erase, Auto Block Erase Auto Multiple-Block Erase Program Suspend/Resume Block-Erase Suspend/Resume Data Polling / Toggle Bit function Block Protection / Boot Block Protection Support for automatic sleep and hidden ROM area Common flash memory interface (CFI) Byte/Word Modes Erase and Program cycles for flash memory 105 cycles (typical) Boot block architecture for flash memory TH50VSF2580AASB: Top boot block TH50VSF2581AASB: Bottom boot block Package P-FBGA69-1209-0.80A3: 0.31 g (typ.) PIN NAMES A0~A21 • A12S CIOF = VCC, CIOS = VCC (×16, ×16) 1 2 3 4 5 6 7 8 9 10 A NC NC B NC NC C NC A7 LB WP/ACC WE A8 A11 D A3 A6 UB RESET CE2S A19 A12 A15 E A2 A5 A18 RY/BY A20 A9 A13 NC A12F Address inputs A12 input for SRAM A12 input for flash memory SA A18 input for SRAM DQ0~DQ15 Data inputs/outputs CE1S , CE2S Chip Enable inputs for SRAM CEF Chip Enable input for flash memory OE Output Enable input WE LB , UB Write Enable input Data byte control input RY/BY Ready/Busy output F NC A1 A4 A17 A10 A14 NC NC RESET Hardware reset input G NC A0 VSS DQ1 DQ6 DU A16 NC WP/ACC H CEF OE DQ9 DQ3 DQ4 J CE1S DQ0 DQ10 VCCf VCCs DQ12 DQ7 DQ8 DQ2 DQ11 CIOS DQ14 K CIOS DQ13 DQ15 CIOF DQ5 VSS Write Protect / Program Acceleration input Word Enable input for SRAM CIOF Word Enable input for flash memory VCCs Power supply for SRAM VCCf Power supply for flash memory L NC NC VSS Ground M NC NC NC Not connected DU Do not use 000707EBA2 • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 2001-10-26 1/50 TH50VSF2580/2581AASB PIN ASSIGNMENT (TOP VIEW) • CIOF = VCC, CIOS = VSS (×16, ×8) 1 A NC B NC C NC 2 4 5 6 7 8 9 10 NC NC A7 DU WP/ACC WE A8 A11 D A3 A6 DU RESET CE2S A19 A12 A15 E A2 A5 A18 RY/BY A20 A9 A13 NC F NC A1 A4 A17 A10 A14 NC NC G NC A0 VSS DQ1 DQ6 SA A16 NC H CEF OE DQ9 DQ3 DQ4 J CE1S DQ0 DQ10 VCCf VCCs DQ12 DQ7 DQ8 DQ2 DQ11 CIOS DQ14 K • 3 DQ13 DQ15 CIOF DQ5 VSS L NC NC M NC NC CIOF = VSS, CIOS = VSS (×8, ×8) 1 2 3 4 5 6 7 8 9 10 A NC NC B NC NC C NC D E F NC G NC A7 DU WP/ACC WE A8 A11 A3 A6 DU RESET CE2S A20 A13 A2 A5 A19 RY/BY A21 A1 A4 A18 A9 A14 NC A10 A15 NC NC DQ6 A12S A17 NC DU A12F CIOF VSS A0 VSS DQ1 H CEF OE DU DQ3 DQ4 J CE1S DQ0 DU VCCf VCCs DU DQ7 DU DQ2 DU CIOS DQ5 DU K A16 L NC NC M NC NC Note: A12F and A12S should be wired together and used as a single A12 pin. 000707EBA2 • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 2001-10-26 2/50 TH50VSF2580/2581AASB BLOCK DIAGRAM VSS VCCf A0~A21 A0~A21 WP/ACC RESET CEF DQ0~DQ15 (DQ0~DQ7) 32-Mbit Flash Memory RY/BY CIOF DQ0~DQ15 VSS VCCs A0~A17 SA WE OE CE1S 4-Mbit SRAM Memory DQ0~DQ15 (DQ0~DQ7) CE2S UB LB CIOS MODE SELECTION OPERATION MODE CEF CE1S CE2S OE WE RESET UB LB WP/ACC DQ0~DQ7 DQ8~DQ15 L H X L H H X X X DOUT DOUT L X L L H H X X X DOUT DOUT H L H L H H L L X DOUT DOUT H L H L H H H L X DOUT Hi-Z H L H L H H L H X Hi-Z DOUT L H X H L H X X X DIN DIN L X L H L H X X X DIN DIN H L H X L H L L X DIN DIN H L H X L H H L X DIN Hi-Z H L H X L H L H X Hi-Z DIN X H X H H X X X X Hi-Z Hi-Z X X L H H X X X X Hi-Z Hi-Z H X X H H X X X X Hi-Z Hi-Z H X X X X X H H X Hi-Z Hi-Z Flash Standby H X X X X H X X X S S Flash Hardware Reset / Standby X X X X X L X X X S S X H X X X X X X X F F X X L X X X X X X F F Flash Read SRAM Read Flash Write SRAM Write Flash Output Disable SRAM Output Disable SRAM Standby Notes: L = VIL; H = VIH; X = VIH or VIL F: Depends on flash memory operation mode. S: Depends on SRAM operation mode. When CIOS = VCC and CIOF = VCC, Word Mode is selected for both SRAM and flash memory. Does not apply when CEF = CE1S = VIL and CE2S = VIH at the same time. 2001-10-26 3/50 TH50VSF2580/2581AASB ID CODE TABLE CODE TYPE (1) A20~A12 A6 A1 A0 * L L L 0098H TH50VSF2580AASB * L L H 009AH TH50VSF2581AASB * L L H 009CH L H L Data Manufacturer Code CODE (HEX) Device Code Verify Block Protect BA (2) (3) Notes: * = VIH or VIL, L = VIL, H = VIH (1) DQ8~DQ15 are Hi-Z in Byte mode (2) BA: Block Address (3) 0001H - Protected Block 0000H - Unprotected Block 2001-10-26 4/50 TH50VSF2580/2581AASB COMMAND SEQUENCES BUS FIRST BUS SECOND BUS THIRD BUS FOURTH BUS FIFTH BUS SIXTH BUS COMMAND WRITE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE SEQUENCE CYCLES Addr. Addr. REQ’D Read/Reset Read/Reset 1 Word 3 Addr. Data XXXH F0H 555H AAAH 555H Word 555H 2AAH 3 Byte Word Program Suspend Program Resume 4 Word Erase Byte Auto Block Word Erase Byte 555H 1 6 BK BK (3) (3) 555H AAH 555H (3) 1 BK Block Erase Resume 1 BK Block Protect 4 XXXH Word (3) AAH 2AAH AAH 2AAH 60H BPA (9) 555H 2AAH Set Byte Word Mode Entry Byte Hidden ROM Word Program Byte Hidden ROM Word Erase Byte Hidden ROM Mode Exit Word 3 4 6 90H AAH 555H 555H 4 555H AAH (3) (3) (3) + PA (4) ID (5) 555H (6) PD (7) 555H 80H 55H 555H 555H AAH AAAH 80H AAAH 555H 2AAH 55H 555H AAH AAAH 2AAH 555H 10H AAAH 55H BA 55H BA (8) 30H 555H 60H PA (6) XXXH 2AAH 2AAH AAH 2AAH BK 2AAH 40H BPA 90H BPA (9) BPD (10) (3) + 555H BK (3) + (9) BPD (10) AAAH 55H 555H 20H AAAH PD F0H (7) (13) 55H 555H 88H AAAH 55H 555H A0H PA (6) PD (7) AAAH 55H 555H AAH XXXH 555H 80H AAAH 55H 555H 555H 555H AAH AAAH 90H XXXH 2AAH (8) 30H 555H 00H AAAH + 55H BK A0H (2) + AAAH 555H AAAH BK 55H 555H AAAH 2 Byte 555H A0H AAAH Byte Command XXXH IA RD AAAH 555H AAAH Word Query AAH AAAH 2 55H 55H Word Hidden ROM 90H (1) Data AAAH 2AAH Fast Program Fast Program Reset RA Data 30H AAH XXXH F0H Data B0H 555H 2 (3) 555H BK 555H AAAH Fast Program BK 555H Byte 3 Addr. 30H 555H 3 555H Data AAAH 55H 2AAH Addr. B0H AAAH Block Erase Suspend 55H 555H AAAH 6 Data 555H AAAH 1 Auto Chip AAH AAAH Byte Verify Block Protect 2AAH Byte ID Read Auto-Program AAH Addr. + 98H CA (11) CD (12) AAH • Byte mode when VIL is inputted to CIOF, and addresses are A21~A0 • Write mode when VIH is inputted to CIOF, and addresses are A20~A0 • Valid addresses are A10~A0 when a command is entered. (1) RA: Read Address (6) PA: Program Address (2) RD: Read Data (7) PD: Program Data (3) BK: Bank Address = A20~A15 (4) IA: Bank Address and ID Read Address (A6, A1, A0) (8) BA: Block Address = A20~A12 (9) BPA: Block Address and ID Read Address (A6, A1, A0) Bank Address = A20~A15 Manufacturer Code = (0, 0, 0) Block Address = A20~A12 Device Code = (0, 0, 1) ID Read Address = (0, 1, 0) (5) ID: ID Data (10) BPD: Verify Data 0098H - Manufacturer Code (11) CA: CFI Address 009AH - Device Code (TH50VSF2580AASB) (12) CD: CFI Data 009CH - Device Code (TH50VSF2581AASB) (13) F0H: 00H is valid too 0001H - Protected Block Notes: The system should generate the following address patterns: Word Mode: 555H or 2AAH on address pins A10~A0 Byte Mode: AAAH or 555H on address pins A10~A0, A12F DQ8~DQ15 are ignored in Word Mode. 2001-10-26 5/50 TH50VSF2580/2581AASB BLOCK ERASE ADDRESS TABLES (1) TH50VSF2580AASB (top boot block) BLOCK ADDRESS BANK # ADDRESS RANGE BLOCK # BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BYTE MODE WORD MODE BA0 L L L L L L * * * 000000H~00FFFFH 000000H~007FFFH BA1 L L L L L H * * * 010000H~01FFFFH 008000H~00FFFFH BA2 L L L L H L * * * 020000H~02FFFFH 010000H~017FFFH BA3 L L L L H H * * * 030000H~03FFFFH 018000H~01FFFFH BA4 L L L H L L * * * 040000H~04FFFFH 020000H~027FFFH BA5 L L L H L H * * * 050000H~05FFFFH 028000H~02FFFFH BA6 L L L H H L * * * 060000H~06FFFFH 030000H~037FFFH BA7 L L L H H H * * * 070000H~07FFFFH 038000H~03FFFFH BA8 L L H L L L * * * 080000H~08FFFFH 040000H~047FFFH BA9 L L H L L H * * * 090000H~09FFFFH 048000H~04FFFFH BA10 L L H L H L * * * 0A0000H~0AFFFFH 050000H~057FFFH BA11 L L H L H H * * * 0B0000H~0BFFFFH 058000H~05FFFFH BA12 L L H H L L * * * 0C0000H~0CFFFFH 060000H~067FFFH BA13 L L H H L H * * * 0D0000H~0DFFFFH 068000H~06FFFFH BA14 L L H H H L * * * 0E0000H~0EFFFFH 070000H~077FFFH BA15 L L H H H H * * * 0F0000H~0FFFFFH 078000H~07FFFFH BA16 L H L L L L * * * 100000H~10FFFFH 080000H~087FFFH BA17 L H L L L H * * * 110000H~11FFFFH 088000H~08FFFFH BA18 L H L L H L * * * 120000H~12FFFFH 090000H~097FFFH BA19 L H L L H H * * * 130000H~13FFFFH 098000H~09FFFFH BA20 L H L H L L * * * 140000H~14FFFFH 0A0000H~0A7FFFH BA21 L H L H L H * * * 150000H~15FFFFH 0A8000H~0AFFFFH BA22 L H L H H L * * * 160000H~16FFFFH 0B0000H~0B7FFFH BA23 L H L H H H * * * 170000H~17FFFFH 0B8000H~0BFFFFH BA24 L H H L L L * * * 180000H~18FFFFH 0C0000H~0C7FFFH BA25 L H H L L H * * * 190000H~19FFFFH 0C8000H~0CFFFFH BA26 L H H L H L * * * 1A0000H~1AFFFFH 0D0000H~0D7FFFH BA27 L H H L H H * * * 1B0000H~1BFFFFH 0D8000H~0DFFFFH BA28 L H H H L L * * * 1C0000H~1CFFFFH 0E0000H~0E7FFFH BA29 L H H H L H * * * 1D0000H~1DFFFFH 0E8000H~0EFFFFH BA30 L H H H H L * * * 1E0000H~1EFFFFH 0F0000H~0F7FFFH BA31 L H H H H H * * * 1F0000H~1FFFFFH 0F8000H~0FFFFFH BK0 BK1 BK2 BK3 2001-10-26 6/50 TH50VSF2580/2581AASB BLOCK ADDRESS BANK # ADDRESS RANGE BLOCK # BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BYTE MODE WORD MODE BA32 H L L L L L * * * 200000H~20FFFFH 100000H~107FFFH BA33 H L L L L H * * * 210000H~21FFFFH 108000H~10FFFFH BA34 H L L L H L * * * 220000H~22FFFFH 110000H~117FFFH BA35 H L L L H H * * * 230000H~23FFFFH 118000H~11FFFFH BA36 H L L H L L * * * 240000H~24FFFFH 120000H~127FFFH BA37 H L L H L H * * * 250000H~25FFFFH 128000H~12FFFFH BA38 H L L H H L * * * 260000H~26FFFFH 130000H~137FFFH BA39 H L L H H H * * * 270000H~27FFFFH 138000H~13FFFFH BA40 H L H L L L * * * 280000H~28FFFFH 140000H~147FFFH BA41 H L H L L H * * * 290000H~29FFFFH 148000H~14FFFFH BA42 H L H L H L * * * 2A0000H~2AFFFFH 150000H~157FFFH BA43 H L H L H H * * * 2B0000H~2BFFFFH 158000H~15FFFFH BA44 H L H H L L * * * 2C0000H~2CFFFFH 160000H~167FFFH BA45 H L H H L H * * * 2D0000H~2DFFFFH 168000H~16FFFFH BA46 H L H H H L * * * 2E0000H~2EFFFFH 170000H~177FFFH BA47 H L H H H H * * * 2F0000H~2FFFFFH 178000H~17FFFFH BA48 H H L L L L * * * 300000H~30FFFFH 180000H~187FFFH BA49 H H L L L H * * * 310000H~31FFFFH 188000H~18FFFFH BA50 H H L L H L * * * 320000H~32FFFFH 190000H~197FFFH BA51 H H L L H H * * * 330000H~33FFFFH 198000H~19FFFFH BA52 H H L H L L * * * 340000H~34FFFFH 1A0000H~1A7FFFH BA53 H H L H L H * * * 350000H~35FFFFH 1A8000H~1AFFFFH BA54 H H L H H L * * * 360000H~36FFFFH 1B0000H~1B7FFFH BA55 H H L H H H * * * 370000H~37FFFFH 1B8000H~1BFFFFH BA56 H H H L L L * * * 380000H~38FFFFH 1C0000H~1C7FFFH BA57 H H H L L H * * * 390000H~39FFFFH 1C8000H~1CFFFFH BA58 H H H L H L * * * 3A0000H~3AFFFFH 1D0000H~1D7FFFH BA59 H H H L H H * * * 3B0000H~3BFFFFH 1D8000H~1DFFFFH BA60 H H H H L L * * * 3C0000H~3CFFFFH 1E0000H~1E7FFFH BA61 H H H H L H * * * 3D0000H~3DFFFFH 1E8000H~1EFFFFH BA62 H H H H H L * * * 3E0000H~3EFFFFH 1F0000H~1F7FFFH BK4 BK5 BK6 BK7 2001-10-26 7/50 TH50VSF2580/2581AASB BLOCK ADDRESS BANK # ADDRESS RANGE BLOCK # BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BYTE MODE WORD MODE BA63 H H H H H H L L L 3F0000H~3F1FFFH 1F8000H~1F8FFFH BA64 H H H H H H L L H 3F2000H~3F3FFFH 1F9000H~1F9FFFH BA65 H H H H H H L H L 3F4000H~3F5FFFH 1FA000H~1FAFFFH BA66 H H H H H H L H H 3F6000H~3F7FFFH 1FB000H~1FBFFFH BA67 H H H H H H H L L 3F8000H~3F9FFFH 1FC000H~1FCFFFH BA68 H H H H H H H L H 3FA000H~3FBFFFH 1FD000H~1FDFFFH BA69 H H H H H H H H L 3FC000H~3FDFFFH 1FE000H~1FEFFFH BA70 H H H H H H H H H 3FE000H~3FFFFFH 1FF000H~1FFFFFH BK8 2001-10-26 8/50 TH50VSF2580/2581AASB (2) TH50VSF2581AASB (bottom boot block) BLOCK ADDRESS BANK # ADDRESS RANGE BLOCK # BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BYTE MODE WORD MODE BA0 L L L L L L L L L 000000H~001FFFH 000000H~000FFFH BA1 L L L L L L L L H 002000H~003FFFH 001000H~001FFFH BA2 L L L L L L L H L 004000H~005FFFH 002000H~002FFFH BA3 L L L L L L L H H 006000H~007FFFH 003000H~003FFFH BA4 L L L L L L H L L 008000H~009FFFH 004000H~004FFFH BA5 L L L L L L H L H 00A000H~00BFFFH 005000H~005FFFH BA6 L L L L L L H H L 00C000H~00DFFFH 006000H~006FFFH BA7 L L L L L L H H H 00E000H~00FFFFH 007000H~007FFFH BA8 L L L L L H * * * 010000H~01FFFFH 008000H~00FFFFH BA9 L L L L H L * * * 020000H~02FFFFH 010000H~017FFFH BA10 L L L L H H * * * 030000H~03FFFFH 018000H~01FFFFH BA11 L L L H L L * * * 040000H~04FFFFH 020000H~027FFFH BA12 L L L H L H * * * 050000H~05FFFFH 028000H~02FFFFH BA13 L L L H H L * * * 060000H~06FFFFH 030000H~037FFFH BA14 L L L H H H * * * 070000H~07FFFFH 038000H~03FFFFH BA15 L L H L L L * * * 080000H~08FFFFH 040000H~047FFFH BA16 L L H L L H * * * 090000H~09FFFFH 048000H~04FFFFH BA17 L L H L H L * * * 0A0000H~0AFFFFH 050000H~057FFFH BA18 L L H L H H * * * 0B0000H~0BFFFFH 058000H~05FFFFH BA19 L L H H L L * * * 0C0000H~0CFFFFH 060000H~067FFFH BA20 L L H H L H * * * 0D0000H~0DFFFFH 068000H~06FFFFH BA21 L L H H H L * * * 0E0000H~0EFFFFH 070000H~077FFFH BA22 L L H H H H * * * 0F0000H~0FFFFFH 078000H~07FFFFH BA23 L H L L L L * * * 100000H~10FFFFH 080000H~087FFFH BA24 L H L L L H * * * 110000H~11FFFFH 088000H~08FFFFH BA25 L H L L H L * * * 120000H~12FFFFH 090000H~097FFFH BA26 L H L L H H * * * 130000H~13FFFFH 098000H~09FFFFH BA27 L H L H L L * * * 140000H~14FFFFH 0A0000H~0A7FFFH BA28 L H L H L H * * * 150000H~15FFFFH 0A8000H~0AFFFFH BA29 L H L H H L * * * 160000H~16FFFFH 0B0000H~0B7FFFH BA30 L H L H H H * * * 170000H~17FFFFH 0B8000H~0BFFFFH BK0 BK1 BK2 BK3 2001-10-26 9/50 TH50VSF2580/2581AASB BLOCK ADDRESS BANK # ADDRESS RANGE BLOCK # BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BYTE MODE WORD MODE BA31 L H H L L L * * * 180000H~18FFFFH 0C0000H~0C7FFFH BA32 L H H L L H * * * 190000H~19FFFFH 0C8000H~0CFFFFH BA33 L H H L H L * * * 1A0000H~1AFFFFH 0D0000H~0D7FFFH BA34 L H H L H H * * * 1B0000H~1BFFFFH 0D8000H~0DFFFFH BA35 L H H H L L * * * 1C0000H~1CFFFFH 0E0000H~0E7FFFH BA36 L H H H L H * * * 1D0000H~1DFFFFH 0E8000H~0EFFFFH BA37 L H H H H L * * * 1E0000H~1EFFFFH 0F0000H~0F7FFFH BA38 L H H H H H * * * 1F0000H~1FFFFFH 0F8000H~0FFFFFH BA39 H L L L L L * * * 200000H~20FFFFH 100000H~107FFFH BA40 H L L L L H * * * 210000H~21FFFFH 108000H~10FFFFH BA41 H L L L H L * * * 220000H~22FFFFH 110000H~117FFFH BA42 H L L L H H * * * 230000H~23FFFFH 118000H~11FFFFH BA43 H L L H L L * * * 240000H~24FFFFH 120000H~127FFFH BA44 H L L H L H * * * 250000H~25FFFFH 128000H~12FFFFH BA45 H L L H H L * * * 260000H~26FFFFH 130000H~137FFFH BA46 H L L H H H * * * 270000H~27FFFFH 138000H~13FFFFH BA47 H L H L L L * * * 280000H~28FFFFH 140000H~147FFFH BA48 H L H L L H * * * 290000H~29FFFFH 148000H~14FFFFH BA49 H L H L H L * * * 2A0000H~2AFFFFH 150000H~157FFFH BA50 H L H L H H * * * 2B0000H~2BFFFFH 158000H~15FFFFH BA51 H L H H L L * * * 2C0000H~2CFFFFH 160000H~167FFFH BA52 H L H H L H * * * 2D0000H~2DFFFFH 168000H~16FFFFH BA53 H L H H H L * * * 2E0000H~2EFFFFH 170000H~177FFFH BA54 H L H H H H * * * 2F0000H~2FFFFFH 178000H~17FFFFH BA55 H H L L L L * * * 300000H~30FFFFH 180000H~187FFFH BA56 H H L L L H * * * 310000H~31FFFFH 188000H~18FFFFH BA57 H H L L H L * * * 320000H~32FFFFH 190000H~197FFFH BA58 H H L L H H * * * 330000H~33FFFFH 198000H~19FFFFH BA59 H H L H L L * * * 340000H~34FFFFH 1A0000H~1A7FFFH BA60 H H L H L H * * * 350000H~35FFFFH 1A8000H~1AFFFFH BA61 H H L H H L * * * 360000H~36FFFFH 1B0000H~1B7FFFH BA62 H H L H H H * * * 370000H~37FFFFH 1B8000H~1BFFFFH BK4 BK5 BK6 BK7 2001-10-26 10/50 TH50VSF2580/2581AASB BLOCK ADDRESS BANK # ADDRESS RANGE BLOCK # BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BYTE MODE WORD MODE BA63 H H H L L L * * * 380000H~38FFFFH 1C0000H~1C7FFFH BA64 H H H L L H * * * 390000H~39FFFFH 1C8000H~1CFFFFH BA65 H H H L H L * * * 3A0000H~3AFFFFH 1D0000H~1D7FFFH BA66 H H H L H H * * * 3B0000H~3BFFFFH 1D8000H~1DFFFFH BA67 H H H H L L * * * 3C0000H~3CFFFFH 1E0000H~1E7FFFH BA68 H H H H L H * * * 3D0000H~3DFFFFH 1E8000H~1EFFFFH BA69 H H H H H L * * * 3E0000H~3EFFFFH 1F0000H~1F7FFFH BA70 H H H H H H * * * 3F0000H~3FFFFFH 1F8000H~1FFFFFH BK8 2001-10-26 11/50 TH50VSF2580/2581AASB BLOCK SIZE TABLE (1) TH50VSF2580AASB (top boot block) BLOCK # BLOCK SIZE BYTE MODE WORD MODE BA0~BA7 64 Kbytes 32 Kwords BA8~BA15 64 Kbytes BA16~BA23 BANK # BANK SIZE BLOCK COUNT BYTE MODE WORD MODE BK0 512 Kbytes 256 Kwords 8 32 Kwords BK1 512 Kbytes 256 Kwords 8 64 Kbytes 32 Kwords BK2 512 Kbytes 256 Kwords 8 BA24~BA31 64 Kbytes 32 Kwords BK3 512 Kbytes 256 Kwords 8 BA32~BA39 64 Kbytes 32 Kwords BK4 512 Kbytes 256 Kwords 8 BA40~BA47 64 Kbytes 32 Kwords BK5 512 Kbytes 256 Kwords 8 BA48~BA55 64 Kbytes 32 Kwords BK6 512 Kbytes 256 Kwords 8 BA56~BA62 64 Kbytes 32 Kwords BK7 448 Kbytes 224 Kwords 7 BA63~BA70 8 Kbytes 4 Kwords BK8 64 Kbytes 32 Kwords 8 (2) TH50VSF2581AASB (bottom boot block) BLOCK # BLOCK SIZE BYTE MODE WORD MODE BA0~BA7 8 Kbytes 4 Kwords BA8~BA14 64 Kbytes BA15~BA22 BANK # BANK SIZE BLOCK COUNT BYTE MODE WORD MODE BK0 64 Kbytes 32 Kwords 8 32 Kwords BK1 448 Kbytes 224 Kwords 7 64 Kbytes 32 Kwords BK2 512 Kbytes 256 Kwords 8 BA23~BA30 64 Kbytes 32 Kwords BK3 512 Kbytes 256 Kwords 8 BA31~BA38 64 Kbytes 32 Kwords BK4 512 Kbytes 256 Kwords 8 BA39~BA46 64 Kbytes 32 Kwords BK5 512 Kbytes 256 Kwords 8 BA47~BA54 64 Kbytes 32 Kwords BK6 512 Kbytes 256 Kwords 8 BA55~BA62 64 Kbytes 32 Kwords BK7 512 Kbytes 256 Kwords 8 BA63~BA70 64 Kbytes 32 Kwords BK8 512 Kbytes 256 Kwords 8 2001-10-26 12/50 TH50VSF2580/2581AASB ABSOLUTE MAXIMUM RATINGS SYMBOL VCC PARAMETER VCCs/VCCf Supply Voltage (1) VIN Input Voltage VDQ Input/Output Voltage Topr Operating Temperature PD Power Dissipation Tsolder Soldering Temperature (10s) RANGE UNIT −0.3~4.6 V −0.3~4.6 V −0.5~VCC + 0.5 (≤ 4.6) V -40~85 °C 0.6 W 260 °C 100 mA (2) IOSHORT Output Short Circuit Current NEW Erase/Program Cycling Capability 100,000 Cycles Tstg Storage Temperature −55~125 °C (1) −2.0 V for pulse width ≤ 20 ns (2) Output shorted for no more than one second. No more than one output shorted at a time HARDWARE SEQUENCE FLAGS STATUS DQ7 DQ6 DQ5 DQ3 DQ2 RY/BY DQ 7 Toggle 0 0 1 0 Data Data Data Data Data Hi-Z 0 Toggle 0 0 Toggle 0 Not-selected 0 Toggle 0 0 1 0 Selected 0 Toggle 0 1 Toggle 0 Not-selected 0 Toggle 0 1 1 0 Selected 1 1 0 0 Toggle Hi-Z Not-selected Data Data Data Data Data Hi-Z Selected DQ 7 Toggle 0 0 Toggle 0 Not-selected DQ 7 Toggle 0 0 1 0 DQ 7 Toggle 1 0 1 0 0 Toggle 1 1 NA 0 DQ 7 Toggle 1 0 NA 0 Auto Programming (1) Read in Program Suspend (2) Selected Erase Hold Time In Auto Erase In Progress (3) Auto Erase Read In Erase Suspend Programming Auto Programming Time Limit Exceeded Auto Erase Programming in Erase Suspend Notes: DQ outputs cell data and RY/BY goes High-Impedence when the operation has been completed. DQ0 and DQ1 pins are reserved for future use. 0 is output on DQ0, DQ1 and DQ4. (1) Data output from an address to which Write is being performed are undefined. (2) Output when the block address selected for Auto Block Erase is specified and data is read from there. During Auto Chip Erase, all blocks are selected. (3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is read from there. 2001-10-26 13/50 TH50VSF2580/2581AASB RECOMMENDED DC OPERATING CONDITIONS (Ta = -40°~85°C) SYMBOL PARAMETER MIN TYP. MAX VCCs/VCCf Power Supply Voltage 2.7 3.6 VIH Input High-Level Voltage 2.2 VCC + 0.3 −0.3 VCC × 0.2 (1) UNIT VIL Input Low-Level Voltage VDH Data Retention Voltage for SRAM 1.5 3.6 VLKO Flash Low-Lock Voltage 2.3 2.5 VACC High Voltage for WP/ACC 8.5 9.5 VID High Voltage for RESET 11.4 12.6 MIN TYP. MAX UNIT 15 pF 20 pF V (1) −2.0 V for pulse width ≤ 20 ns CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER CONDITION CIN Input Capacitance VIN = GND COUT Output Capacitance VOUT GND = Note: These parameters are sampled periodically and are not tested for every device. 2001-10-26 14/50 TH50VSF2580/2581AASB DC CHARACTERISTICS (Ta = -40°~85°C, VCCs/VCCf = 2.7 V~3.6 V) SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT ±1 µA IIL Input Leakage Current VIN = 0 V~VCC ISOH SRAM Output High Current VOH = VCCs − 0.5 V −0.5 mA ISOL SRAM Output Low Current VOL = 0.4 V 2.1 mA IFOH1 Flash Output High Current (TTL) VOH = 2.4 V −0.4 mA Flash Output High Current (CMOS) VOH = VCCf × 0.85 −2.5 mA IFOH2 VOH = VCCf − 0.4 V −100 µA IFOL Flash Output Low Current VOL = 0.4 V 4 mA ILO Output Leakage Current VOUT = 0 V~VCC, OE = VIH ±1 µA ICCO1 Flash Average Read Current CEF = VIL, OE = VIH, IOUT = 0 mA, tcycle = tRC(min) 30 mA ICCO2 Flash Average Program/ Erase Current CEF = VIL, OE = VIH, IOUT = 0 mA 15 mA ICCO3 SRAM Average Operating Current ICCO4 CE1S = VIL, CE2S = VIH, OE = VIH, IOUT = 0 mA tcycle = tRC 50 tcycle = 1 MHz 12 CE1S = 0.2 V, OE = VCCs − 0.2 V, CE2S = VCCs − 0.2 V, IOUT = 0 mA tcycle = tRC 45 tcycle = 1 MHz 5 mA mA ICCO5 Flash Average Read-while-Programming Current VIN = VIH/VIL, IOUT = 0 mA, tcycle = tRC(min) 45 mA ICCO6 Flash Average Read-while-Erasing Current VIN = VIH/VIL, IOUT = 0 mA, tcycle = tRC(min) 45 mA ICCO7 Flash Average Program-whileErase-Suspended Current VIN = VIH/VIL, IOUT = 0 mA 15 mA ICCS1 Flash Standby Current CEF = RESET = VCCf or RESET = VSS 10 µA ICCS2 Flash Standby Current (1) (Automatic Sleep Mode ) VIH = VCCf or VIL = VSS 10 µA CE1S = VIH or CE2S = VIL 2 mA Ta = 25°C 0.01 0.5 Ta = −20°~40°C 1 Ta = −20°~85°C 5 Ta = 25°C 0.6 Ta = −20°~85°C 6 0.7 7 20 ICCS3 VCCs = 3.0 V SRAM Standby Current ICCS4 CE1S = VCCs − 0.2 (2) V or CE2S = 0.2 V VCCs = 3 V ± 10% Ta = 25°C VCCs = 3.3 V ± 0.3 V Ta = −20°~85°C IACC High-Voltage Input Current for WP/ACC 8.5 V ≤ VACC ≤ 9.5 V µA mA (1) If the address remains unchanged for 150 ns, the device will enter Automatic Sleep Mode. (2) In Standby Mode, with CE1S ≥ VCCs − 0.2 V, these limits are guaranteed when CE2S ≥ VCCs − 0.2 V or CE2S ≤ 0.2 V, and CIOS ≥ VCCs − 0.2 V or CIOS ≤ 0.2 V. 2001-10-26 15/50 TH50VSF2580/2581AASB AC CHARACTERISTICS (SRAM) (Ta = -40°~85°C, VCCs = 2.7 V~3.6 V) Read cycle SYMBOL PARAMETER MIN MAX tRC Read Cycle Time 90 tACC Address Access Time 90 tCO1 Chip Enable ( CE1S ) Access Time 90 tCO2 Chip Enable (CE2S) Access Time 90 tOE Output Enable Access Time 45 tBA Data Byte Control Access Time 45 tCOE Chip Enable Low to Output Active 5 tOEE Output Enable Low to Output Active 0 tBE Data Byte Control Low to Output Active 0 tOD Chip Enable High to Output Hi-Z 35 tODO Output Enable High to Output Hi-Z 35 tBD Data Byte Control High to Output Hi-Z 35 tOH Output Data Hold Time 10 tCCR CE Recovery Time 0 MIN MAX UNIT ns Write cycle SYMBOL PARAMETER tWC Write Cycle Time 85 tWP Write Pulse Width 55 tCW Chip Enable to End of Write 70 tBW Data Byte Control to End of Write 55 tAS Address Set-up Time 0 tWR Write Recovery Time 0 tODW WE Low to Output Hi-Z 35 tOEW WE High to Output Active 0 tDS Data Set-up Time 35 tDH Data Hold Time 0 UNIT ns AC TEST CONDITIONS PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) VALUES 0.4 V, 2.4 V 5 ns Timing Measurement Reference Level (input) VCCs × 0.5 Timing Measurement Reference Level (output) VCCs × 0.5 Output Load CL (30pF) + 1 TTL gate 2001-10-26 16/50 TH50VSF2580/2581AASB AC CHARACTERISTICS (FLASH MEMORY) READ CYCLE SYMBOL PARAMETER MIN MAX UNIT tRC Read Cycle Time 90 ns tACC Address Access Time 90 ns tCE CEF Access Time 90 ns tOE OE Access Time 40 ns tCEE CEF to Output Low-Z 0 ns tOEE OE to Output Low-Z 0 ns tOEH OE Hold Time 0 ns tOH Output Data Hold Time 0 ns tDF1 CEF to Output Hi-Z 30 ns tDF2 OE to Output Hi-Z 30 ns BLOCK PROTECT SYMBOL PARAMETER MIN MAX UNIT tVPS VID Set-up Time 4 µs tCESP CEF Set-up Time 4 µs tVPH OE Hold Time 4 µs tPPLH WE Low-Level Hold Time 100 µs MIN MAX UNIT Auto-Program Time (Byte Mode) 8* 300 µs Auto-Program Time (Word Mode) 11* 300 µs tPCEW Auto Chip Erase Time 50* 710 s tPBEW Auto Block Erase Time 0.7* 10 s tEW Erase/Program Cycle 10 5 Cycles PROGRAM AND ERASE CHARACTERISTICS SYMBOL PARAMETER tPPW *: typ. 2001-10-26 17/50 TH50VSF2580/2581AASB COMMAND WRITE/PROGRAM/ERASE CYCLE SYMBOL PARAMETER MIN MAX UNIT 120 ns tCMD Command Write Cycle Time tAS Address Set-up Time / BYTE Set-up Time 0 ns tAH Address Hold Time / BYTE Hold Time 50 ns tAHW Address Hold Time from WE High level 20 ns tDS Data Set-up Time 50 ns tDH Data Hold Time 0 ns tWELH WE Low-Level Hold Time ( WE Control) 50 ns tWEHH WE High-Level Hold Time ( WE Control) 20 ns tCES CEF Set-up Time to WE Active ( WE Control) 0 ns tCEH CEF Hold Time from WE High Level 0 ns tCELH CEF Low-Level Hold Time ( CEF Control) 50 ns tCEHH CEF High-Level Hold Time ( CEF Control) 20 ns tWES WE Set-up time to CEF Active ( CEF Control) 0 ns tWEH WE Hold Time from CEF High Level 0 ns tOES OE Set-up Time 0 ns tOEHP OE Hold Time (Toggle, Data Polling) 90 ns tOEHT OE High-Level Hold Time (Toggle) 20 ns tAST Address Set-up Time (Toggle) 0 ns tAHT Address Hold Time (toggle) 0 ns tBEH Erase Hold Time 50 µs tVCS VCCf Set-up Time 500 µs tBUSY Program/Erase Valid to RY/BY Delay 90 ns tRP RESET Low-Level Hold Time 500 ns tREADY RESET Low-Level to Read Mode 20 µs tRB RY/BY Recovery Time 0 ns tRH RESET Recovery Time 50 ns tCEBTS CEF Set-up time BYTE Transition 5 ns tSUSP Program Suspend Command to Suspend Mode 1.5 µs tRESP Program Resume Command to Program Mode 1 µs tSUSE Erase Suspend Command to Suspend Mode 15 µs tRESE Erase Resume Command to Erase Mode 1 µs ( WE Control) ( CEF Control) 2001-10-26 18/50 TH50VSF2580/2581AASB SIMULTANEOUS READ/WRITE OPERATION The TH50VSF2580/2581AASB features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation enables the device to simultaneously write data to or erase data from a bank while reading data from another bank. The TH50VSF2580/2581AASB has a total of nine banks: 1 bank of 0.5 Mbits, 1 bank of 3.5 Mbits and 7 banks of 4 Mbits. Banks can be switched between using the bank addresses (A20~A15). For a description of bank blocks and addresses, please refer to the Block Address Table and Block Size Table. The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table below shows the operation modes in which simultaneous operation can be performed. Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation cannot read data from addresses in the same bank which have not been selected for operation. Data from these addresses can be read using the Program Suspend or Erase Suspend function, however. SIMULTANEOUS READ/WRITE OPERATION STATUS OF BANK ON WHICH OPERATION IS BEING PERFORMED STATUS OF OTHER BANKS Read Mode (1) ID Read Mode Auto-Program Mode (2) Fast Program Mode Program Suspend Mode Read Mode Auto Block Erase Mode (3) Auto Multiple Block Erase Mode Erase Suspend Mode Program Suspend during Erase Suspend CFI Mode (1) Only Command Mode is valid. (2) Including times when Acceleration Mode is in use. (3) If the selected blocks are spread across all nine banks, simultaneous operation cannot be carried out. OPERATION MODES In addition to the Read, Write and Erase Modes, the TH50VSF2520/2581AASB features many functions including block protection and data polling. When incorporating the device into a deign, please refer to the timing charts and flowcharts in combination with the description below. Read Mode To read data from the memory cell array, set the device to Read Mode. In Read Mode the device can perform high-speed random access as asynchronous ROM. The device is automatically set to Read Mode immediately after power-on or on completion of automatic operation. A software reset releases ID Read Mode and the lock state which the device enters if automatic operation ends abnormally, and sets the device to Read Mode. A hardware reset terminates operation of the device and resets it to Read Mode. When reading data without changing the address immediately after power-on, either input a hardware Reset or change CEF from H to L. 2001-10-26 19/50 TH50VSF2580/2581AASB ID Read Mode ID Read mode is used to read the device maker code and device code. The mode is useful for EPROM programmers to automatically identify the device type. In this method, simultaneous operation can be performed. Inputting an ID Read command sets the specified bank to ID Read mode. Banks are specified by inputting the bank address (BK) in the third bus write cycle of the command cycle. To read an ID code, the bank address as well as the ID read address must be specified. From address BK + 00 the maker code is output; from address BK + 01 the device code is output. From other banks, data are output from the memory cells. Inputting a Reset command releases ID Read mode and returns the device to Read mode. Access time in ID Read mode is the same as that in Read mode. For the codes, see the ID Code Table. Standby Mode There are two ways to put the device into Standby Mode. (1) Control using CEF and RESET With the device in Read Mode, input VDD ± 0.3 V to CEF and RESET . The device will enter Standby Mode and the current will be reduced to the standby current (ICCS1). However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. (2) Control using RESET only With the device in Read Mode, input VSS ± 0.3 V to RESET . The device will enter Standby Mode and the current will be reduced to the standby current (ICCS1). Even if the device is in the process of performing simultaneous operation, this method will terminate the current operation and set the device to Standby Mode. This is a hardware reset and is described later. In Standby Mode DQ is put in High-Impedance state. Auto-Sleep Mode This function suppresses power dissipation during reading. If the address input does not change for 150 ns, the device will automatically enter Sleep Mode and the current will be reduced to the standby current (ICCS2). However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new address is output. Output Disable Mode Inputting VIH to OE disables output from the device and sets DQ to High-Impedance. 2001-10-26 20/50 TH50VSF2580/2581AASB Command Write The TH50VSF2580/2581AASB uses the standard JEDEC control commands for a single-power supply E2PROM. A Command Write is executed by inputting the address and data into the Command Register. The command is written by inputting a pulse to WE with CEF = VIL and OE = VIH ( WE control). The command can also be written by inputting a pulse to CEF with WE = VIL ( CEF control). The address is latched on the falling edge of either WE or CEF . The data is latched on the rising edge of either WE or CEF . DQ0~DQ7 are valid for data input and DQ8~DQ15 are ignored. To abort input of the command sequence use the Reset command. The device will reset the Command Register and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device will enter Read Mode. Software Reset Apply a software reset by inputting a Read/Reset command. A software reset returns the device from ID Read Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and clears the Command Register. Hardware Reset A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for tRP, the device abandons the operation which is in progress and enters Read Mode after tREADY. Note that if a hardware reset is applied during data overwriting, such as a Write or Erase operation, data at the address or block being written to at the time of the reset will become undefined. After a hardware reset the device enters Read Mode if RESET = VIH or Standby Mode if RESET = VIL. The DQ pins are High-Impedance when RESET = VIL. After the device has entered Read Mode, Read operations and input of any command are allowed. Comparison between Software Reset and Hardware Reset ACTION SOFTWARE RESET HARDWARE RESET Releases ID Read Mode or CFI Mode. True True Clears the Command Register. True True Releases the lock state if automatic operation has ended abnormally. True True Stops any automatic operation which is in progress. False True Stops any operation other than the above and returns the device to Read Mode. False True BYTE /Word Mode CIOF is used select Word Mode (16 bits) or Byte Mode (8 bits) for the TH50VSF2580/2581AASB. If VIH is input to CIOF, the device will operate in Word Mode. Read data or write commands using DQ0~DQ15. When VIL is input to CIOF, read data or write commands using DQ0~DQ7. A12F is used as the lowest address. DQ8~DQ14 will become High-Impedance. 2001-10-26 21/50 TH50VSF2580/2581AASB Auto-Program Mode The TH50VSF2580/2581AASB can be programmed in either byte or word units. Auto-Program Mode is set using the Program command. The program address is latched on the falling edge of the WE signal and data is latched on the rising edge of the fourth Bus Write cycle (with WE control). Auto programming starts on the rising edge of the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To read the Hardware Sequence flag, specify the address to which the Write is being performed. During Auto-Program execution, a command sequence for the bank on which execution is being performed cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is terminated in this manner, the data written so far is invalid. Any attempt to program a protected block is ignored. In this case the device enters Read Mode 3 µs after the rising edge of the WE signal in the fourth Bus Write cycle. If an Auto-Program operation fails, the device remains in the programming state and does not automatically return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails, the block which contains the address to which data could not be programmed should not be used. The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device error. A cell containing 0 must be erased in order to set it to 1. Fast Program Mode Fast Program is a function which enables execution of the command sequence for the Auto Program to be completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires four cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the Fast Program command. Write in this mode uses the Fast Program command but operation is the same at that for ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read operations can be performed as usual. To exit this mode, the Fast Program Reset command must be input. When the command is input, the device will return to Read Mode. Acceleration Mode The TH50VSF2580/2581AASB features Acceleration Mode which allows write time to be reduced. Applying VACC to WP or ACC automatically sets the device to Acceleration Mode. In Acceleration Mode, Block Protect Mode changes to Temporary Block Unprotect Mode. Write Mode changes to Fast Program Mode. Modes are switched by the WP/ACC signal; thus, there is no need for a Temporary Block Unprotect operation or to set or reset Fast Program Mode. Operation of Write is the same as in Auto-Program Mode. Removing VACC from WP/ACC terminates Acceleration Mode. 2001-10-26 22/50 TH50VSF2580/2581AASB Program Suspend/Resume Mode Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but ignores the command in other modes. When the command is input, the address of the bank on which Write is being performed must be specified. After input of the command, the device will enter Program Suspend Read Mode after tSUSP. During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are the same as usual. After completion of Program Suspend input a Program Resume command to return to Write Mode. When inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or CFI Data Read functions is being used, abort the function before inputting the Resume command. On receiving the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the bank to which data is being written. Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running Program Suspend in Acceleration Mode, VACC must not be released. Auto Chip Erase Mode The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the Hardware Sequence flag. Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional Erase operation must be performed. Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed and the device will enter Read mode 100 µs after the rising edge of the WE signal in the sixth bus cycle. If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take measures to prevent subsequent use of the failed block. 2001-10-26 23/50 TH50VSF2580/2581AASB Auto Block Erase / Auto Multi-Block Erase Modes The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The block address is latched on the falling edge of the WE signal in the sixth bus cycle. The block erase starts as soon as the Erase Hold Time (tBEH) has elapsed after the rising edge of the WE signal. When multiple blocks are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the device will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive rising edge of WE . Once operation starts, all memory cells in the selected block are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which auto-erase operation is being performed must be specified. If the selected blocks are spread across all nine banks, simultaneous operation cannot be carried out. All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing. Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase operation is not executed and the device returns to Read Mode 100 µs after the rising edge of the WE signal in the last bus cycle. If an auto-erase operation fails, the device remains in Erasing state and does not return to Read Mode. The device status is indicated by the Hardware Sequence flag. After a failure either a Reset command or a Hardware Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take measures to prevent subsequent use of the failed block. Erase Suspend / Erase Resume Modes Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block. The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes. When the command is input, the address of the bank on which Erase is being performed must be specified. In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after tSUSE. The device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output will stop toggling and RY/ BY will be set to High-Impedance. Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not been selected for the Auto Block Erase. Data is written in the usual manner. To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of the bank on which the Write was being performed must be specified. On receiving an Erase Resume command, the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend command is input during the Erase Hold Time, the device will return to the state it was in at the start of the Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on RY/ BY . 2001-10-26 24/50 TH50VSF2580/2581AASB Block Protection Block Protection is a function to disable write and erase in block units. Applying VID to RESET and inputting the Block Protect command performs block protection. The first cycle of the command sequence is the Setup command. In the second cycle, the Block Protect command is input, in which a block address and A1 = VIH and A0 = A6 = VIL are input. At this time, the device writes to the block protector circuit, Until write is complete, there must be a wait of tPPLH but the device need not be controlled during this time. In the third cycle, the Verify Block Protect command is input. This command verifies write to the block protector circuit. Read is performed in the fourth cycle. If the protection operation is complete, 01H is output. If other than 01H is output, write is not complete; thus, input the Block Protect command again. Canceling VID to RESET exits this mode. Temporary Block Unprotection The TC58VSF2580/2581AASB has a temporary block unprotection feature which disables block protection for all protected blocks. Unprotection is enabled by applying VID to the RESET pin. Now Write and Erase operations can be performed on all blocks except the boot blocks which have been protected by the Boot Block Protect operation. The device returns to its previous state when VID is removed from the RESET pin. That is, previously protected blocks will be protected again. Verify Block Protect The Verify Block Protect command is used to ascertain whether a block is protected or unprotected. This mode is set by setting A0, A6 and the block address A19~A12 to VIL and setting A1 to VIH. This command should be input before a Read operation is performed. 0001H is output if the block is protected and 0000H is output if the block is unprotected. In Byte Mode DQ8 to DQ15 are in High-Impedance state. Block protection verification can also be carried out using a software command. Boot Block Protection Boot block protection temporarily protects certain boot blocks using a method different from ordinary block protection. Neither VID nor a command sequence is required. Protection is performed simply by inputting VIL on WP/ACC . The target blocks are the two pairs of boot blocks. The top boot blocks are BA69 and BA70; the bottom boot blocks are BA0 and BA1. Inputting VIH on WP/ACC releases the mode. From now on, if it is necessary to protect these blocks, the ordinary Block Protection Mode must be used. 2001-10-26 25/50 TH50VSF2580/2581AASB Hidden ROM Area The TH50VSF2580/2581AASB features a 64-Kbyte hidden ROM area which is separate from the memory cells. The area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot be released, once the block is protected, data in the block cannot be overwritten. The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations are the same as auto operations except that the device is in Hidden ROM Mode. However, regarding write operation, Accelaration mode can not be performed during Hidden ROM mode. To protect the hidden ROM area, use the block protection function. The operation of Block Protect here is the same as a normal Block Protect except that VIH rather than VID is input to RESET . Once the block has been protected, protection cannot be released, even using the temporary block unprotection function. Use Block Protect carefully. Note that in Hidden ROM Mode, simultaneous operation cannot be performed. Therefore, do not attempt to access areas other than the hidden ROM area. To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read Mode. HIDDEN ROM AREA ADDRESS TABLE TYPE BOOT BLOCK ARCHITECTURE BYTE MODE WORD MODE ADDRESS RANGE SIZE ADDRESS RANGE SIZE TH50VSF2580AASB TOP BOOT BLOCK 3F0000H~3FFFFFH 64 Kbytes 1F8000H~1FFFFFH 32 Kwords TH50VSF2581AASB BOTTOM BOOT BLOCK 000000H~00FFFFH 64 Kbytes 000000H~007FFFH 32 Kwords 2001-10-26 26/50 TH50VSF2580/2581AASB COMMON FLASH MEMORY INTERFACE (CFI) The TH50VSF2520/2581AASB conforms to the CFI specifications. To read information from the device, input the Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the Reset command. CFI CODE TABLE ADDRESS A6~A0 DATA DQ15~DQ0 DESCRIPTION 10H 11H 12H 0051H 0052H 0059H ASCII string “QRY” 13H 14H 0002H 0000H Primary OEM command set 2: AMD/FJ standard type 15H 16H 0040H 0000H Address for primary extended table 17H 18H 0000H 0000H Alternate OEM command set 0: none exists 19H 1AH 0000H 0000H Address for alternate OEM extended table 1BH 0027H VDD (min) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV 1CH 0036H VDD (max) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV 1DH 0000H VPP (min) voltage 1EH 0000H VPP (max) voltage 1FH 0004H Typical time-out per single byte/word write (2 µs) 20H 0000H Typical time-out for minimum size buffer write (2 µs) 21H 000AH Typical time-out per individual block erase (2 ms) 22H 0000H Typical time-out for full chip erase (2 ms) 23H 0005H Maximum time-out for byte/word write (2 times typical) 24H 0000H Maximum time-out for buffer write (2 times typical) 25H 0004H Maximum time-out per individual block erase (2 times typical) 26H 0000H Maximum time-out for full chip erase (2 times typical) 27H 0016H Device Size (2 byte) 28H 29H 0002H 0000H Flash device interface description 2: ×8/×16 2AH 2BH 0000H 0000H Maximum number of bytes in multi-byte write (2 ) N N N N N N N N N N 2001-10-26 27/50 TH50VSF2580/2581AASB ADDRESS A6~A0 DATA DQ15~DQ0 DESCRIPTION 2CH 0002H Number of erase block regions within device 2DH 2EH 2FH 30H 0007H 0000H 0020H 0000H Erase Block Region 1 information Bits 0~15: y = block number Bits 16~31: z = block size (z × 256 bytes) 31H 32H 33H 34H 003EH 0000H 0000H 0001H Erase Block Region 2 information 40H 41H 42H 0050H 0052H 0049H ASCII string “PRI” 43H 0031H Major version number, ASCII 44H 0031H Minor version number, ASCII 45H 0000H Address-Sensitive Unlock 0: Required 1: Not required 46H 0002H Erase Suspend 0: Not supported 1: For Read-only 2: For Read & Write 47H 0001H Block Protect 0: Not supported X: Number of blocks per group 48H 0001H Block Temporary Unprotect 0: Not supported 1: Supported 49H 0004H Block Protect/Unprotect scheme 4AH 0001H Simultaneous operation 0: Not supported 1: Supported 4BH 0000H Burst Mode 0: Not supported 4CH 0000H Page Mode 0: Not supported 4DH 0085H VACC (min) voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV 4EH 0095H VACC (max) voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV 4FH 000XH Top/Bottom Boot Block Flag 2: TH50VSF2580AASB 3: TH50VSF2581AASB 50H 0001H Program suspend 0: Not supported 1: Supported 2001-10-26 28/50 TH50VSF2580/2581AASB HARDWARE SEQUENCE FLAGS FOR FLASH MEMORY The TH50VSF2580/2581AASB has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when CEF = OE = VIL in Read Mode. The RY/ BY output can be either High or Low. The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The Hardware Sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data. DQ7 ( DATA polling) During an Auto-Program or auto-erase operation, the device status can be determined using the data polling function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation, DQ7 outputs inverted data during the programming operation and outputs actual data after programming has finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data. When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE signal. DQ6 (Toggle bit 1) The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately outputs a 0 or a 1 for each OE access while CEF = VIL while the device is busy. When the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the operation fails, the DQ6 output toggles. If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around 3 µs. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block, DQ6 will toggle for around 100 µs. It will then stop toggling. After toggling has stopped the device will return to Read Mode. DQ5 (internal time-out) If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the operation has not been completed within the allotted time. Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case DQ5 outputs a 1. Either a hardware reset or a software Reset command is required to return the device to Read Mode. 2001-10-26 29/50 TH50VSF2580/2581AASB DQ3 (Block Erase timer) The Block Erase operation starts 50 µs (the Erase Hold Time) after the rising edge of WE in the last command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time. Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked for erasing. DQ3 outputs a 1 if the Program or Erase operation fails. DQ2 (Toggle bit 2) DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the device is in Erase Suspend Mode. If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle. Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2 output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in Programming Mode, DQ2 will output a 1. RY/BY (READY / BUSY ) The TH50VSF2580/2581AASB has a RY/ BY signal to indicate the device status to the host processor. A 0 (Busy state) indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates that the operation has finished and that the device can now accept a new command. RY/ BY outputs a 0 when an operation has failed. RY/ BY outputs a 0 after the rising edge of WE in the last command cycle. During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/ BY outputs a 1 during an Erase Suspend operation. The output buffer for the RY/ BY pin is an open-drain type circuit, allowing a wired-OR connection. A pull-up resistor must be inserted between VCC and the RY/ BY pin. 2001-10-26 30/50 TH50VSF2580/2581AASB DATA PROTECTION The TH50VSF2580/2581AASB includes a function which guards against malfunction or data corruption. Protection against Program/Erase Caused by Low Supply Voltage To prevent malfunction at power-on or power-down, the device will not accept commands while VCCf is below VLKO. In this state, command input is ignored. If VCCf drops below VLKO during an Auto Operation, the device will terminate Auto-Program execution. In this case, Auto operation is not executed again when VCCf return to recommended VCCf voltage Therefore, command need to be input to execute Auto operation again. When VCCf > VLKO, make up countermeasure to be input accurately command in system side please. Protection against Malfunction Caused by Glitches To prevent malfunction during operation caused by noise from the system, the device will not accept pulses shorter than 3 ns(Typ.) input on WE , CEF or OE . However, if a glitch exceeding 3 ns(Typ.) occurs and the glitch is input to the device malfunction may occur. The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a proper command is input, the device may not operate. To avoid this possibility, clear the Command Register before command input. In an environment prone to system noise, Toshiba recommend input of a software or hardware reset before command input. Protection against Malfunction at Power-on To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CEF = VIL , the device does not latch the command on the first rising edge of WE or CEF . Instead, the device automatically Resets the Command Register and enters Read Mode. 2001-10-26 31/50 TH50VSF2580/2581AASB TIMING DIAGRAMS VIH or VIL Data invalid FLASH READ/ID READ OPERATION tRC Address tACC tCE tOH CEF tOE tDF1 tOEE OE tCEE tDF2 WE tOEH DOUT Output data valid Hi-Z Hi-Z SRAM READ CYCLE (see Note 1) tRC Address tACC CE2S tOH tCO2 tCO1 tOD CE1S tOE tOD OE tBA tODO tBE UB , LB tOEE tCOE DOUT Hi-Z tCOE tBD Output data valid Hi-Z 2001-10-26 32/50 TH50VSF2580/2581AASB SRAM WRITE CYCLE 1 ( WE -CONTROLLED) (see Note 4) tWC Address tAS tWP tWR WE tCW CE2S tCW CE1S tBW UB , LB tODW DOUT tOEW See Note 2 Hi-Z tDS DIN See Note 3 tDH Input data valid See Note 5 See Note 5 SRAM WRITE CYCLE 2 (CE1S -CONTROLLED) (see Note 4) tWC Address tAS tWP tWR WE tCW CE2S tCW CE1S tBW UB , LB tBE tCOE DOUT tODW Hi-Z Hi-Z tDS DIN See Note 5 tDH Input data valid See Note 5 2001-10-26 33/50 TH50VSF2580/2581AASB SRAM WRITE CYCLE 3 (CE2S-CONTROLLED) (see Note 4) tWC Address tAS tWP tWR WE tCW CE2S tCW CE1S tBW UB , LB tBE tCOE DOUT tODW Hi-Z Hi-Z tDS DIN tDH Input data valid See Note 5 See Note 5 SRAM WRITE CYCLE 4 ( UB- and LB -CONTROLLED) (see Note 4) tWC Address tAS tWP tWR WE tCW CE1S tCW CE2S tBW UB , LB tBE tCOE DOUT tODW Hi-Z Hi-Z tDS DIN See Note 5 tDH Input data valid See Note 5 2001-10-26 34/50 TH50VSF2580/2581AASB FLASH COMMAND WRITE OPERATION This is the timing of the Command Write Operation. The timing which is described in the following pages is essentially the same as the timing shown on this page. • WE Control tCMD Command address Address tAS tAH tAHW CEF tCES tCEH WE tWELH tWEHH tDS Command data DIN • tDH CEF Control tCMD Address Command address tAS tAH CEF tCELH tCEHH tWES tWEH WE tDS DIN tDH Command data 2001-10-26 35/50 TH50VSF2580/2581AASB FLASH ID READ OPERATION (Input command sequence) Address 555H 2AAH BK + 555H tCMD BK + 00H BK + 01H tRC CEF OE tOES WE DIN AAH 55H 90H Manufacturer code DOUT Device code Hi-Z ID Read Mode Read Mode (input of ID Read command sequence) (Continued) Address 555H 2AAH 555H tCMD CEF OE WE DIN DOUT AAH 55H F0H Hi-Z ID Read Mode (input of Reset command sequence) Read Mode Note: Word Mode address shown. BK: Bank address 2001-10-26 36/50 TH50VSF2580/2581AASB FLASH AUTO-PROGRAM OPERATION ( WE -CONTROLLED) 555H Address 2AAH 555H PA PA tCMD CEF OE tOEHP tOES tPPW WE AAH DIN 55H DOUT A0H PD Hi-Z DQ7 DOUT tVCS VCCf Note: Word Mode address shown. PA: Program address PD: Program data FLASH AUTO CHIP ERASE / AUTO BLOCK ERASE OPERATION ( WE -CONTROLLED) 555H Address 2AAH 555H 555H 2AAH 555H/BA tCMD CEF OE tOES WE AAH DIN 55H 80H AAH 55H 10H/30H tVCS VCCf Note: Word Mode address shown. BA: Block address for Auto Block Erase operation 2001-10-26 37/50 TH50VSF2580/2581AASB FLASH AUTO-PROGRAM OPERATION (CEF-CONTROLLED) 555H Address 2AAH 555H PA PA tCMD CEF tPPW OE tOEHP tOES WE DIN AAH 55H DOUT A0H PD Hi-Z DQ7 DOUT tVCS VCCf Note: Word Mode address shown. PA: Program address PD: Program data FLASH AUTO CHIP ERASE / AUTO BLOCK ERASE OPERATION ( CEF -CONTROLLED) 555H Address 2AAH 555H 555H 2AAH 555H/BA tCMD CEF OE tOES WE AAH DIN 55H 80H AAH 55H 10H/30H tVCS VCCf Note: Word Mode address shown. BA: Block address for Auto Block Erase operation 2001-10-26 38/50 TH50VSF2580/2581AASB FLASH PROGRAM/ERASE SUSPEND OPERATION RA BK Address CEF OE WE tOE B0H DIN tCE DOUT DOUT Hi-Z Hi-Z tSUSP/tSUSE RY/BY Program/Erase Mode Suspend Mode RA: Read address BK: Bank address FLASH PROGRAM/ERASE RESUME OPERATION Address RA BK PA/BA CEF OE tOES WE tRESP/tRESE tDF1 tDF2 tOE 30H DIN tCE DOUT DOUT Flag Hi-Z Hi-Z RY/BY Suspend Mode Program/Erase Mode PA: Program address BK: Bank address BA: Block address RA: Read address Flag: Hardware Sequence flag 2001-10-26 39/50 TH50VSF2580/2581AASB FLASH RY/BY DURING AUTO-PROGRAM/ERASE OPERATION CEF Command input sequence WE tBUSY During operation RY/BY FLASH HARDWARE RESET OPERATION WE tRB RESET tRP tREADY RY/BY FLASH READ AFTER RESET tRC Address tRH RESET tACC DOUT Hi-Z tOH Output data valid 2001-10-26 40/50 TH50VSF2580/2581AASB FLASH HARDWARE SEQUENCE FLAG ( DATA Polling) Last Command Address tCMD Address PA/BA CE tCE tOE tDF1 OE tOEHP tDF2 WE tPPW /tPCEW /tPBEW tACC tOH Last Command Data DIN DQ7 DQ0~DQ6 DQ7 Valid Valid Invalid Valid Valid tBUSY RY/BY PA: Program address BA: Block address FLASH HARDWARE SEQUENCE FLAG (Toggle bit) Address tAST tAST tAHT CEF tOEHT tCE tAHT OE tOEHP WE tOE DIN Last Command Data Toggle DQ2/6 Toggle Toggle Stop* Toggle Valid tBUSY RY/BY *DQ2/DQ6 stops toggling when auto operation has been completed. 2001-10-26 41/50 TH50VSF2580/2581AASB FLASH BLOCK PROTECT OPERATION BA BA Address tCMD tCMD BA tCMD BA + 1 tRC A0 A1 A6 CEF OE tPPLH WE tVPS VID VIH RESET DIN 60H 60H 40H 60H tOE DOUT Hi-Z 01H* BA: Block address BA + 1: Address of next block *: 01H indicates that block is protected. 2001-10-26 42/50 TH50VSF2580/2581AASB TIMING FOR SWITCHING BETWEEN FLASH AND SRAM MODES CEF tCCR tCCR CE1S CE2S Notes: (1) WE remains High during a Read cycle. (2) If CE1S goes Low (or CE2S goes High) at the same time as or after WE goes Low, the outputs will remain High-Impedance. (3) If CE1S goes High (or CE2S goes Low) at the same time as or before WE goes High, the outputs will remain High-Impedance. (4) If OE is High during a Write cycle, the outputs will remain High-Impedance. (5) Since I/O pins may be in Output state at this point, do not attempt to apply input signals to them. (6) DOUT6 stops toggling when the last command has been completed. 2001-10-26 43/50 TH50VSF2580/2581AASB SRAM DATA RETENTION CHARACTERISTICS (Ta = -40°~85°C) SYMBOL PARAMETER MIN TYP. MAX UNIT 1.5 3.6 V VDH = 3.0 V 5 VDH = 3.6 V 7 0 ns ns VDH Data Retention Supply Voltage for SRAM ICCS4 SRAM Standby Current tCDR Chip-Deselect-to-Data-Retention-Mode Time tr Recovery Time tRC (1) µA (1) Read cycle time CE1S-CONTROLLED DATA RETENTION MODE (see Note 1) VCCs VCCs Data Retention Mode 2.7 V (See Note 2) (See Note 2) VIH CE1S tCDR tr VCCs − 0.2 V GND CE2S-CONTROLLED DATA RETENTION MODE (see Note 3) VCCs VCCs Data Retention Mode 2.7 V CE2S VIH VIL tCDR tr 0.2 V GND Notes: (1) In CE1S -Controlled Data Retention Mode the device enters Minimum Standby Current Mode when CE2S ≤ 0.2 V or CE2S ≥ VCCs − 0.2 V. (2) When CE1S is at VIH (2.2 V), the SRAM standby current is the same as ICCS3 during the transition of VCCs from 3.6 V to 2.4 V. (3) In CE2S-Controlled Data Retention Mode the device enters Minimum Standby Current Mode when CE2S ≤ 0.2 V. 2001-10-26 44/50 TH50VSF2580/2581AASB FLOWCHARTS OF FLASH MEMORY OPERATIONS Auto-Program Start Auto-Program Command Sequence (see below) DATA Polling or Toggle Bit Address = Address + 1 No Last Address? Yes Auto-Program Completed Auto-Program Command Sequence (address/data) 555H/AAH 2AAH/55H 555H/A0H Program Address/Program Data Note: The above command sequence takes place in Word Mode. 2001-10-26 45/50 TH50VSF2580/2581AASB Fast Program Start Fast Program Set Command Sequence (see below) Fast Program Command Sequence (see below) DATA Polling or Toggle Bit Address = Address + 1 No Last Address? Yes Program Sequence (see below) Fast Program Completed Fast Program Set Command Sequence (address/data) Fast Program Command Sequence (address/data) Fast Program Reset Command Sequence (address/data) 555H/AAH XXXH/A0H XXXH/90H 2AAH/55H Program Address/Program Data XXXH/F0H 555H/20H 2001-10-26 46/50 TH50VSF2580/2581AASB Auto Erase Start Auto Erase Command Sequence (see below) DATA Polling or Toggle Bit Auto Erase Completed Auto Chip Erase Command Sequence (address/data) Auto Block / Auto Multi-Block Erase Command Sequence (address/data) 555H/AAH 555H/AAH 2AAH/55H 2AAH/55H 555H/80H 555H/80H 555H/AAH 555H/AAH 2AAH/55H 2AAH/55H 555H/10H Block Address/30H Block Address/30H Block Address/30H Additional address inputs during Auto Multi-Block Erase Note: The above command sequence takes place in Word Mode. 2001-10-26 47/50 TH50VSF2580/2581AASB DQ7 DATA Polling Start Read Byte (DQ0~DQ7) Addr. = VA Yes DQ7 = Data? No No DQ5 = 1? Yes 1) : DQ7 must be rechecked even if DQ5 = 1 because DQ7 may change at the same time as DQ5. 1) Read Byte (DQ0~DQ7) Addr. = VA Yes DQ7 = Data? No Fail Pass DQ6 Toggle Bit Start Read Byte (DQ0~DQ7) Addr. = VA No DQ6 = Toggle? Yes No DQ5 = 1? Yes 1) : DQ6 must be rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time that DQ5 changes to 1. 1) Read Byte (DQ0~DQ7) Addr. = VA DQ6 = Toggle? No Yes Fail Pass VA: Byte address for programming Any of the addresses within the block being erased during a Block Erase operation “Don’t care” during a Chip Erase operation Any address not within the current block during an Erase Suspend operation 2001-10-26 48/50 TH50VSF2580/2581AASB Block Protect Start RESET = VID Wait for 4 µs PLSCNT = 1 Block Protect Command First Bus Write Cycle (XXXH/60H) Set up Address Addr. = BPA Block Protect Command Second Bus Write Cycle (BPA/60H) Wait for 100 µs Block Protect Command Third Bus Write Cycle (XXXH/40H) PLSCNT = PLSCNT + 1 Verify Block Protect No Data = 01H? No Yes Yes Protect Another Block? PLSCNT = 25? Yes Remove VID from RESET No Remove VID from RESET Reset Command Reset Command Device Failed Block Protect Complete BPA: Block Address and ID Read Address (A6, A1, A0) ID Read Address = (0, 1, 0) 2001-10-26 49/50 TH50VSF2580/2581AASB PACKAGE DIMENSIONS Unit: mm 2001-10-26 50/50