TI BQ24745 Smbus-controlled level 2 multi-chemistry battery charger with input current detect comparator Datasheet

bq24745
www.ti.com
SLUS761 – DECEMBER 2007
SMBus-Controlled Level 2 Multi-Chemistry Battery Charger With Input
Current Detect Comparator
UGAT
PHAS
DCIN
27
26
25
24
23
22
ICREF
1
21
VDDP
ACIN
2
20
LGATE
VREF
3
19
PGND
EAO
4
18
CSOP
EAI
5
17
CSON
FBO
6
16
NC
CE
7
15
VFB
8
9
10
11
12
13
14
NC
bq24745
28 LD QFN
TOP VIEW
ACOK
•
•
•
28
GND
•
The bq24745 is a high-efficiency, synchronous
battery charger with an integrated input-current
comparator, offering low component count for
space-constrained, multi-chemistry battery-charging
applications. SMBus input-current, charge-current,
and charge-voltage DACs allow very high regulation
accuracies that can be easily programmed by the
system power-management microcontroller using the
SMBus. The bq24745 charges two, three, or four
series Li+ cells, and is available in a 28-pin, 5x5 mm2
thin QFN package.
BOOT
•
DESCRIPTION
VDDSMB
•
•
•
Notebook and Ultra-Mobile Computers
Portable Data-Capture Terminals
Portable Printers
Medical Diagnostics Equipment
Battery Bay Chargers
Battery Back-up Systems
ICOUT
•
•
•
•
•
•
•
SCL
•
APPLICATIONS
CSSN
•
•
SDA
•
NMOS-NMOS Synchronous Buck Converter
with 300 kHz Frequency and >95% Efficiency
30-ns Minimum Driver Dead-time and 99.5%
Maximum Effective Duty Cycle
High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
– ±2% Input Current Sense Amp Accuracy
Integration
– Input Current Comparator, With Adjustable
Threshold and Hysteresis
– Internal Soft-Start
Safety
– Input Overvoltage Protection (OVP)
– Dynamic Power Management (DPM)
Up to 19.2 V Battery Voltage
6 V–24 V AC/DC-Adapter Operating Range
Simplified SMBus Control
– Charge Voltage DAC (1.024 V–19.2 V)
– Charge Current DAC (128 mA–8.064 A)
– Adapter Current Limit DPM DAC (256
mA–11.004 A)
Status and Monitoring Outputs
– AC/DC Adapter Present with Adjustable
Voltage Threshold
– Input Current Comparator, With Adjustable
Threshold and Hysteresis
– Current Sense Amplifier for Current Drawn
From Input Source
Charge Any Battery Chemistry: Li+, NiCd,
NiMH, Lead Acid, etc.
Cells Pin Supports Two to Four Li-Ion Cells
Charge Enable Pin
< 10-µBattery Current with Adapter Removed
< 1 mA Input DCIN Current with Adapter
Present and Charge Disabled
28-pin, 5x5-mm2 QFN Package
CSSP
•
•
VICM
FEATURES
1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
bq24745
www.ti.com
SLUS761 – DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The bq24745 features Dynamic Power Management (DPM) and input power limiting. These features reduce
battery-charge current when the input power limit is reached to avoid overloading the AC adaptor when supplying
the load and the battery charger simultaneously. A highly accurate current-sense amplifier enables precise
measurement of input current from the AC adapter, allowing monitoring the overall system power. If the adapter
current is above the programmed low-power threshold, a signal is sent to host so that the system optimizes its
performance to the power available from the adapter. An integrated comparator monitors the input current
through the current-sense amplifier, and indicates when the input current exceeds a programmable threshold
limit.
TYPICAL APPLICATIONS
VIN = 20 V, VBAT = 4-cell Li-Ion, ICHARGE = 4.5 A, VICMer_limit = 6 A
ADAPTER +
CHRG_IN
R10
4
C1
1uF
Controlled by
HOST
C5 0.1uF
Q5
(BATFET)
SI4835BDY
17 CSSN
18 CSSP
P
309k
1%
P
22 DCIN
2
R2
49.9k
1%
ACIN
bq24745
+3.3V_ALWAYS
OR
+5V_ALWAYS
11 VDDSMB
C6
1uF
PHASE 23
BOOT
25
R3
10k
3
R4
10k
R5
10k
C7
VREF
1uF
BAT54
C11
1uF
L1
RSR
0.010
PACK+
5.6uH
PACK-
LGATE
20
PGND
19
CSOP
28
CSON
27
C14
3x10uF
C12
0.1uF
Q4
FDS6680A
C13
0.1uF
26 ICOUT
R6
10k
VFB 15
Dig I/O
HOST
(EC)
D1
C10
0.1uF
VDDP 21
13 ACOK
DISCRETE
LOGIC
Q3
FDS6680A
UGATE 24
12 GND
N
R1
P
Q2 (DFET)
Q1 (ACFET)
SI4835BDY
SI4835BDY
Controlled by
HOST
C4
0.1uF
C3
0.1uF
C9
2x10uF
N
ADAPTER -
RAC
0.010
7
CE
9
SDA
C15
0.1u
ICREF 1
SMBus
10 SCL
8
DISCRETE
LOGIC
C8
100pF
14 NC
16 NC
R8
4.7k
R7
7.5k
VICM
EAO
4
EAI
5
FBO
6
C16
51pF
C18
130pF
C17
2000pF
R9
200k
Pull-up rail could be either VREF or other system rail.
Figure 1. Typical System Schematic: Using External Input Current Comparator (discrete logic) Instead of
Internal Comparator
VIN = 20 V, VBAT = 4-cell Li-Ion, ICHARGE = 4.5 A, VICMer_limit = 6 A
2
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SLUS761 – DECEMBER 2007
VIN = 20 V, VBAT = 4-cell Li-Ion, ICHARGE = 4.5 A, VICMer_limit = 6 A
ADAPTER +
CHRG_IN
R10
4
P
P
Q1 (ACFET)
Q2 (DFET)
SI4835BDY
SI4835BDY
Controlled by
HOST
C4
0.1uF
C3
0.1uF
C1
1uF
R1
Controlled by
HOST
C5 0.1uF
Q5
(BATFET)
SI4835BDY
17 CSSN
18 CSSP
P
309k
1%
C9
2x10uF
22 DCIN
2
ACIN
bq24745
+3.3V_ALWAYS
OR
+5V_ALWAYS
PHASE 23
BOOT
11 VDDSMB
C6
1uF
25
13 ACOK
3
R14
10k
R4
10k
R5
10k
C7
VREF
1uF
BAT54
C11
1uF
R6
10k
7
LGATE
20
PGND
19
CSOP
28
CSON
27
VREF
1
SDA
8
100pF
C14
3x10uF
C13
R12
17.4k
1% R7
7.5k
10 SCL
C8
PACK-
C15
0.1u
R11
51.1k
1%
CE
ICREF
9
SMBus
DISCRETE
LOGIC
PACK+
5.6uH
C12
0.1uF
Q4
FDS6680A
VFB 15
Dig I/O
RSR
0.010
0.1uF
26 ICOUT
HOST
(EC)
D1
L1
C10
0.1uF
VDDP 21
R3
10k
DISCRETE
LOGIC
Q3
FDS6680A
UGATE 24
12 GND
N
R2
49.9k
1%
N
ADAPTER -
RAC
0.010
VICM
14 NC
EAO
4
EAI
5
FBO
6
R8
4.7k
C16
51pF
16 NC
C18
130pF
C17
2000pF
R13
R9
200k
1400K
Pull-up rail could be either VREF or other system rail.
Figure 2. Typical System Schematic, Using Internal Input Current Comparator
ORDERING INFORMATION
PART NUMBER
PACKAGE
bq24745
28-PIN 5 x 5 mm2 QFN
ORDERING NUMBER
(Tape and Reel)
QUANTITY
bq24745RHDR
3000
bq24745RHDT
250
PACKAGE THERMAL DATA
(1)
PACKAGE
θJA
TA = 70°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
QFN – RHD (1)
39°C/W
2.36 W
0.028 W/°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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SLUS761 – DECEMBER 2007
Table 1. TERMINAL FUNCTIONS – 28-PIN QFN
TERMINAL
FUNCTION
NO.
4
1
ICREF
Low-power voltage set input. Connect a resistor-divider from VREF to ICREF, and GND to program the reference for
the LOPWR comparator. The ICREF pin voltage is compared to the VICM pin voltage and the logic output is given on
the ICOUT open-drain pin. Connecting a positive feedback resistor from the ICREF pin to the ICOUT pin programs the
hysteresis.
2
ACIN
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter
input to ACIN pin to GND pin. Adapter voltage is detected if ACIN pin voltage is greater than 2.4 V. VICM current
sense amplifier is active when ACIN pin voltage is greater than 0.6 V.
3
VREF
3.3 V regulated voltage output. Place a 1 µF ceramic capacitor from VREF to GND pin close to the IC. This voltage
could be used for ratiometric programming of voltage and current regulation and for programming the ICREF
threshold.
4
EAO
Error Amplifier Output for compensation. Connect the feedback-compensation components from EAO to EAI.
Typically, a capacitor in parallel with a series resistor and capacitor. This node is internally compared to the PWM
saw-tooth oscillator signal.
5
EAI
Error Amplifier Input for compensation. Connect the feedback compensation components from EAI to EAO. Connect
the input compensation from FBO to EAI.
6
FBO
Feedback Output for compensation. Connect the input compensation from FBO to EAI. Typically, a resistor in parallel
with a series resistor and capacitor.
7
CE
Charge enable active-high logic input. HI enables charge. LO disables charge.
8
VICM
Adapter current sense amplifier output. VICM voltage is 20 times the differential voltage across CSSP-CSSN. Place a
100pF (max) or less ceramic decoupling capacitor from VICM to GND.
9
SDA
SMBus Data input. Connect to SMBus data line from the host controller. A 10-kΩ pull-up resistor to the host controller
power rail is needed.
10
SCL
SMBus Clock input. Connect to SMBus clock line from the host controller. A 10-kΩ pull-up resistor to the host
controller power rail is needed.
11
VDDSMB
Input voltage for SMBus logic. Connect a 3.3 V always supply rail, or 5 V always rail to VDDSMB pin. Connect a 0.1µF
ceramic capacitor from VDDSMB to GND for decoupling.
12
GND
Analog Ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the
power-pad underneath the IC.
13
ACOK
Valid adapter active-high detect logic open-drain output. Pulled HI when Input voltage is above ACIN programmed
threshold. Connect a 10-kΩ pull-up resistor from ACOK pin to pull-up supply rail.
14
NC
No Connect. Pin floating internally.
15
VFB
Battery-voltage remote sense. Directly connect a Kelvin sense trace from the battery-pack positive terminal to the VFB
pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from VFB to GND close to the IC to filter
high-frequency noise.
16
NC
No Connect. Pin floating internally.
17
CSON
Charge-current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from CSON pin to GND
for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from CSON to CSOP to provide
differential-mode filtering.
18
CSOP
Charge-current sense resistor, positive input. An optional 0.1-µF ceramic capacitor is placed from CSOP pin to GND
for common mode filtering. An optional 0.1-µF ceramic capacitor is placed from CSON to CSOP to provide
differential-mode filtering.
19
PGND
Power ground. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input
and output capacitors of the charger. Only connect to GND through the power-pad underneath the IC.
20
LGATE
PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
21
VDDP
PWM low-side driver positive 6-V supply output. Connect a 1-µF ceramic capacitor from VDDP to PGND pin, close to
the IC. Use for high-side driver bootstrap voltage by connecting a small signal Schottky diode from VDDP to BOOT.
22
DCIN
IC-power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET
and source of reverse blocking power P-channel MOSFET. Place a 1µF ceramic capacitor from DCIN to PGND pin
close to the IC.
23
PHASE
PWM high-side driver negative supply. Connect to the phase switching node (junction of the low-side power MOSFET
drain, high-side power MOSFET source, and output inductor). Connect the 0.1µF bootstrap capacitor from PHASE to
BOOT.
24
UGATE
PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
25
BOOT
PWM high-side driver positive supply. Connect a 0.1µF bootstrap ceramic capacitor from BOOT to PHASE. Connect a
small bootstrap Schottky diode from VDDP to BOOT.
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SLUS761 – DECEMBER 2007
Table 1. TERMINAL FUNCTIONS – 28-PIN QFN (continued)
TERMINAL
FUNCTION
NO.
26
ICOUT
Low power mode detect active-high open-drain logic output. Place a 10 kΩ pull-up resistor from ICOUT pin to the
pull-up voltage rail. Place a positive feedback resistor from ICOUT pin to ICREF pin for programming hysteresis. The
output is HI when VICM pin voltage is lower than ICREF pin voltage. The output is LO when VICM pin voltage is
higher than ICREF pin voltage.
27
CSSN
Adapter current-sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from CSSN pin to GND
for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from CSSN to CSSP to provide
differential-mode filtering.
28
CSSP
Adapter current-sense resistor, positive input. An optional 0.1-µF ceramic capacitor is placed from CSSP pin to GND
for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from CSSN to CSSP to provide
differential-mode filtering.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
VALUE
DCIN, CSOP, CSON, CSSP, CSSN, VFB
Voltage range
UNIT
–0.3 to 30
PHASE
–1 to 30
EAI, EAO, FBO, VDDP, LGATE, ACIN, VICM, ICOUT, ICREF, CE, ACOK
–0.3 to 7
VDDSMB
–0.3 to 7
VREF
–0.3 to 3.6
BOOT, UGATE with respect to GND and PGND
–0.3 to 36
GND, PGND
–1 to 1
Maximum difference voltage: CSOP–CSON, CSSP–CSSN
–0.5 to 0.5
Junction temperature range
–40 to 155
Storage temperature range
–55 to 155
(1)
(2)
V
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, and negative out of the specified terminal. Consult
Packaging Section of the data book for thermal limitations and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
PHASE
Voltage range
–1
NOM
MAX
24
DCIN, CSOP, CSON, CSSP, CSSN, VFB
0
24
VDDP, LGATE
0
6.5
VREF
3.3
EAI, EAO, FBO, ACIN, VICM, ICOUT, ICREF, CE, ACOK, VDDSMB
0
5.5
BOOT, UGATE with respect to GND and PGND
0
30
–0.3
0.3
GND, PGND
Maximum difference voltage: CSOP–CSON, CSSP–CSSN
–0.3
0.3
Junction temperature range
–40
125
Storage temperature range
–55
150
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UNIT
V
°C
5
bq24745
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SLUS761 – DECEMBER 2007
ELECTRICAL CHARACTERISTICS
7.0 V ≤ V(DCIN) ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VDCIN_OP
DCIN input voltage operating range
5
24
V
DCIN
V
16.884
V
CHARGE VOLTAGE REGULATION
VVFB_OP
VFB input voltage range
0
16.716
ChargeVoltage() = 0x41A0
–0.5%
12.592
ChargeVoltage() = 0x3130
VVFB_REG
_ACC
VFB charge voltage regulation accuracy
8.350
4.154
TJ = 0 to 125°C, 1.024 V–19.2 V, Max DAC
value is 19.2 V
Charge voltage regulation range
12.529
12.655
V
0.5%
8.4
–0.6%
ChargeVoltage() = 0x1060
RNG
0.5%
–0.5%
ChargeVoltage() = 0x20D0
VVFB_REG_
16.8
8.450
V
0.6%
4.192
4.230
V
–0.9%
0.9%
1.024
19.2
V
0
80.64
mV
CHARGE CURRENT REGULATION
VIREG_CHG_RNG
Charge current regulation differential voltage
range
VIREG_CHG = VCSOP – VCSON, Max DAC value
is 80.64 mV
3968
ChargeCurrent() = 0x0F80
–3%
2048
ChargeCurrent() = 0x0800
ICHRG_REG_ACC
mA
3%
–5%
Charge current regulation accuracy
mA
5%
512
ChargeCurrent() = 0x0200
–25%
mA
25%
128
ChargeCurrent() = 0x0080
mA
–33%
33%
0
110.1
INPUT CURRENT REGULATION
VIREG_DPM_RNG
Adapter current regulation differential voltage
range
VIREG_DPM = VCSSP – VCSSN, Max DAC value
is 110.084 mV
InputCurrent() ≥ 0x0800
InputCurrent() = 0x0400
IINPUT_REG_ACC
Input current regulation accuracy
InputCurrent() = 0x0100
InputCurrent() = 0x0080
4096
–3%
mV
mA
3%
2048
–5%
mA
5%
512
–25%
mA
25%
256
–33%
mA
33%
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VACIN > 0.6 V, 0 - 30 mA
IVREF_LIM
VREF current limit
VVREF = 0 V, VACIN > 0.6 V
3.267
35
VACIN > 0.6 V, 0 - 50 mA
5.7
VVDDP = 0 V, VACIN > 0.6 V
90
VVDDP = 5 V, VACIN > 0.6 V
80
3.3
3.333
V
80
mA
6.3
V
VDDP REGULATOR
VVDDP_REG
VDDP regulator voltage
IVDDP_LIM
VDDP current limit
6
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6.0
135
mA
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SLUS761 – DECEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ V(DCIN) ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADAPTER CURRENT SENSE AMPLIFIER
VCSSP/N_OP
Input common mode range
VVICM
VICM output voltage range
IVICM
VICM output current
AVICM
Current sense amplifier voltage gain
Voltage on CSSP/CSSN
0
24
V
0
2.25
V
0
AVICM = VVICM/ VIREG_DPM
Adapter current sense accuracy
1
20
VIREG_DPM = V(CSSP–CSSN) ≥ 40 mV
–2%
VIREG_DPM = V(CSSP–CSSN) =20 mV
–3%
3%
VIREG_DPM = V(CSSP–CSSN) =5 mV
–25%
25%
VIREG_DPM = V(CSSP–CSSN) =1.5 mV
–33%
33%
IVICM_LIM
Output current limit
VVICM = 0 V
CVICM_MAX
Maximum output load capacitance
For stability with 0 mA to 1 mA load
mA
V/V
2%
1
mA
100
pF
24
V
ACIN COMPARATOR INPUT UNDERVOLTAGE)
VDCIN_VFB_OP
Differential voltage from DCIN to VFB
VACIN_CHG
ACIN rising threshold
Min voltage to enable charging, VACIN rising
VACIN_CHG_HYS
ACIN falling hysteresis
VACIN falling
ACIN rising deglitch (1)
VACIN rising
ACIN falling deglitch
VACIN falling
VACIN_BIAS
Adapter present rising threshold
Min voltage to enable all bias, VACIN rising
VACIN_BIAS_HYS
Adapter present falling hysteresis
VACIN falling
20
VACIN rising
200
VACIN falling
1
ACIN rising deglitch
–20
(1)
ACIN falling deglitch
2.376
2.40
2.424
40
50
100
150
0.62
µs
µs
1
0.56
V
mV
0.68
V
mV
µs
DCIN / VFB COMPARATOR (REVERSE DISCHARGING PROTECTION)
VDCIN-VFB_FALL
DCIN to VFB falling threshold
VDCIN-VFB__HYS
DCIN to VFB hysteresis
VDCIN – VVFB to turn off ACFET
140
185
240
mV
50
mV
DCIN to VFB rising deglitch
VDCIN – VVFB > VDCIN-VFB_RISE
1
ms
DCIN to VFB falling deglitch
VDCIN – VVFB < VDCIN-VFB_FALL
3.3
µs
VFB SHORT (UNDERVOLTAGE and TRICKLE CHARGE) COMPARATOR
VVFB_SHORT_RISE VFB short rising threshold
VVFB_SHORT_HYS
2.6
VFB short rising hysteresis
VFB short rising deglitch
VVFB > VVFB_SHORT+VVFB_SHORT_HYS Detection
delay
VFB short falling deglitch
VVFB < VVFB_SHORT
ITRKL_REG_ACC
Trickle Charge current regulation accuracy in
BATSHORT
VVFB < VVFB_SHORT
ILOW_MAX_REG
Maximum Charge current regulation at Low
Voltage (<4V)
VVFB_SHORT < VVFB < 4
2.7
2.9
mV
1.5
µs
µs
3.3
60
V
215
200
300
3
mA
A
CHARGE OVERCURRENT COMPARATOR
VOC
Charge overcurrent falling threshold
As percentage of IREG_CHG
145%
Minimum Current Limit (CSOP–CSON)
Internal Filter Pole Frequency
50
mV
160
kHz
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV
AC overvoltage rising threshold on ACIN
VACOV_HYS
AC overvoltage rising deglitch
Measure on ACIN pin
3.007
3.1
1.3
3.193
ms
V
AC overvoltage falling deglitch
1.3
ms
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)
UVLO
AC undervoltage rising threshold
VUVLO_HYS
AC undervoltage hysteresis, falling
Measure on DCIN pin
3.5
4
4.5
260
V
mV
INPUT CURRENT COMPARATOR
VICCOMP_OFFSET
(1)
AC Low power mode comparator offset
voltage
-6.8
0.12
6.8
mV
Verified by design.
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ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ V(DCIN) ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
TSHUT_HYS
Thermal shutdown hysteresis, falling
Temperature Increasing
162
°C
20
PWM HIGH SIDE DRIVER (UGATE)
RDS_HI_ON
High side driver (HSD) turn-on resistance
VBOOT – VPHASE = 5.5 V
6
Ω
RDS_HI_OFF
High side driver turn-off resistance
VBOOT – VPHASE = 5.5 V
1
Ω
VBOOT_REFRESH
Bootstrap refresh comparator threshold
voltage
VBOOT – VPHASE when low side refresh pulse
is requested
IBOOT_LEAK
BOOT leakage current when charge enabled
High Side is on; Charge enabled
4
V
200
µA
PWM LOW SIDE DRIVER (LGATE)
RDS_LO_ON
Low side driver (LSD) turn-on resistance
6
Ω
RDS_LO_OFF
Low side driver turn-off resistance
1
Ω
PWM DRIVERS TIMING
Dead time when switching between LGATE
and UGATE , no load at LGATE and UGATE
Driver Dead Time
30
ns
PWM OSCILLATOR
FSW
PWM switching frequency
VRAMP_HEIGHT
PWM ramp height
240
As percentage of DCIN
360
6.67
kHz
%DCIN
QUIESCENT CURRENT
IOFF_STATE
Total off-state battery current from CSOP,
CSON, VFB, DCIN, BOOT, PHASE, etc
VVFB = 16.8 V, VACIN < 0.6 V,
VDCIN > 5 V, TJ = 85°C
IBAT_ON
Battery on-state quiescent current
IBAT_LOAD_CD
7
10
µA
VVFB = 16.8 V, 0.6V < VACIN < 2.4 V,
VDCIN > 5 V
0.7
1
mA
Internal battery load current, charge disabled
Charge is disabled: VVFB = 16.8 V,
VACIN > 2.4 V, VDCIN > 5 V
0.7
1
mA
IBAT_LOAD_CE
Internal battery load current, charge enabled
Charge is enabled: VVFB = 16.8 V,
VACIN > 2.4 V, VDCIN > 5 V
10
12
mA
IAC
Adapter quiescent current
Charge disabled, VDCIN = 20 V
0.7
1
mA
Adapter switching quiescent current
Charge enabled, VDCIN = 20 V, converter
running
25
mA
IAC_SWITCH
6
INTERNAL SOFT START (8 steps to regulation current ICHG)
Soft start steps
Soft start step time
8
step
1.5
ms
1.5
ms
CHARGER SECTION POWER-UP SEQUENCING
Charge-Enable Delay after Power-up
Delay from when adapter is detected to when
the charger is allowed to turn on
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE SYNCHRONOUS TO NON-SYNCHRONOUS)
VUCP
Cycle-by-cycle Synchronous to
Non-Synchronous Transition Threshold
Cycle-by-cycle, (CSSOP-CSSON) voltage,
falling, LGATE turns-off and latches off until
next cycle
Blankout Time after LGATE turns-on
Blankout comparator after LGATE turns-on
5
10
15
100
mV
ns
LOGIC INPUT PIN CHARACTERISTICS (CE) (2) Pull-up CE with ≥2.2 kΩ resistor or directly to VREF.
VIN_LO
Input low threshold voltage
VIN_HI
Input high threshold voltage
VBIAS
Input bias current
0.8
V
1
µA
0.5
V
5.5
V
2.1
V = 0 TO VVDDP
OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (ACOK, ICOUT)
VOUT_LO
Output low saturation voltage
Sink Current = 5 mA
VDDSMB INPUT SUPPLY FOR SMBus
VVDDSMB_RANGE
VDDSMB input voltage range
VVDDSMB_UVLO_
VDDSMB undervoltage lockout threshold
voltage, rising
VVDDSMB Rising
2.4
2.5
2.6
V
VDDSMB undervoltage lockout hysteresis
voltage, falling
VVDDSMB Falling
100
150
200
V
Threshold_Rising
VVDDSMB_UVLO_
Hyst_Rising
(2)
8
2.7
Pull up CE with ≥ 2 kΩ resistor, or connect directly to VREF.
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ELECTRICAL CHARACTERISTICS (continued)
7.0 V ≤ V(DCIN) ≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER
IVDDSMB_Iq
VDDSMB quiescent current
TEST CONDITIONS
MIN
VVDDSMB = SCL = SDA = 5.5 V
TYP
MAX
20
27
UNIT
µA
ELECTRICAL CHARACTERISTICS
7 Vdc ≤ V(VCC) ≤ 24 Vdc, –20°C<TJ <125°C, ref = AGND (unless otherwise noted) (1)
PARAMETER
[SMB TIMING SPECIFICATION (VDD = 2.7 V to 5.5 V) (see Figures 4 and 5)]
MIN
TYP MAX
UNIT
SMBus TIMING CHARACTERISTICS
1
µs
300
ns
50
µs
tR
SCLK/SDATA rise time
tF
SCLK/SDATA fall time
tW(H)
SCLK pulse width high
4
tW(L)
SCLK Pulse Width Low
4.7
µs
tSU(STA)
Setup time for START condition
4.7
µs
tH(STA)
START condition hold time after which first clock pulse is generated
4
µs
tSU(DAT)
Data setup time
250
ns
tH(DAT)
Data hold time
300
ns
tSU(STOP)
Setup time for STOP condition
4
µs
t(BUF)
Bus free time between START and STOP condition
4.7
FS(CL)
Clock Frequency
10
µs
100
kHz
25
35
ms
170
210
s
0.4
V
HOST COMMUNICATION FAILURE
ttimeout
SMBus bus release timeout
22
tBOOT
Deglitch for watchdog reset signal
10
tWDI
Watchdog timeout period
140
ms
OUTPUT BUFFER CHARACTERISTICS
V(SDAL)
(1)
Output LO voltage at SDA, I(SDA) = 3 mA
Devices participating in a transfer will timeout when any clock low exceeds the 25 ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a
slave (25 ms).
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Figure 3. SMBus Communication Timing Waveforms
TYPICAL CHARACTERISTICS
VREF LOAD AND LINE REGULATION
vs
LOAD CURRENT
VDDP LOAD AND LINE REGULATION
vs
LOAD CURRENT
0
0.40
0.20
VDDP - Error - %
VREF - Error - %
0
-0.20
DCIN = 20 V
-0.40
DCIN = 10 V
-1
DCIN = 10 V
-2
-0.60
DCIN = 20 V
-0.80
-1
0
5
10
15
20
25
30
35
40
-3
0
IL - Load Current - mA
Figure 4.
10
20
40
60
IL - Load Current - mA
80
100
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
VFB (BATTERY) VOLTAGE REGULATION ACCURACY
vs
CHARGE CURRENT
VFB (BATTERY) VOLTAGE REGULATION ACCURACY
vs
DAC VBAT SETPOINT
1
1.2
DCIN = 20 V
Battery Voltage Regulation Accuracy - %
Battery Voltage Accuracy - %
3 CELL @ 12.592 V,
ICHG @ 8.064 A,
DCIN = 20 V
0
-1
-2
-3
0
1
2
3
4
5
6
Battery Charge Current - A
7
8
0.8
0.6
0.4
0.2
0
-0.2
0
9
2000
4000 6000 8000 10000 12000 14000 16000 18000 20000
VFB programmed Setpoint - mV
Figure 6.
Figure 7.
CHARGE CURRENT REGULATION ACCURACY
vs
DAC ICHRG SETPOINT
CHARGE CURRENT REGULATION ACCURACY
vs
VFB (BATTERY) VOLTAGE
4.5
0
4
Battery Charge Current - A
-2
Charge Current Accuracy - %
1
-4
-6
-8
-10
-12
DCIN = 20 V,
VFB = 9 V
-14
1000
2000
3000
4000
5000
6000
7000
8000
3
2.5
2
1.5
1
3 CELL @ 12.592 V,
ICHG @ 4.096 A,
DCIN = 20 V
0.5
-16
0
3.5
9000
0
0
ICHG DAC Programmed Setpoint - mA
Figure 8.
2
4
6
8
Battery Voltage - V
10
12
14
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
INPUT CURRENT REGULATION (DPM) ACCURACY
vs
DAC IDPM SETPOINT
VICM INPUT CURRENT SENSE AMPLIFIER ACCURACY
INPUT CHARGE CURRENT
0
0
DCIN = 20 V,
VFB = 9 V
-0.2
Input Current Regulation Accuracy - %
-0.5
-0.4
VICM Accuracy - %
-0.6
-1
-1.5
-2
VFB = 9 V,
DCIN = 20 V
-0.8
-1
-1.2
-1.4
-1.6
-2.5
-1.8
-2
0
-3
2000
4000
6000
8000
10000
12000
2000
DPM Programmed Setpoint - mA
INPUT CURRENT REGULATION (DPM)
AND CHARGE CURRENT
vs
SYSTEM CURRENT
INPUT CURRENT REGULATION (DPM) TRANSIENT
SYSTEM LOAD RESPONSE
CCM TO CCM
Ch1
2 A/div
5
4.5
3
3.5
2
Charge Current
Ch2
2 A/div
4
Ch3
2 A/div
Input Current
4
I(DCIN)
ILOAD
Input Current - A
Charge Current - A
5
I(SYS)
VICM
3
1
2.5
1
1.5
2
2.5
System Current - A
3
3.5
t − Time = 1 ms/div
4
Figure 12.
12
12000
Figure 11.
DCIN = 20 V
0.5
10000
Figure 10.
6
0
0
4000
6000
8000
DPM Program Value - mA
Ch4
500 mV/div
0
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
INPUT CURRENT REGULATION (DPM) TRANSIENT
SYSTEM LOAD RESPONSE
CCM TO DCM
CHARGE CURRENT REGULATION ACCURACY
VFB (BATTERY) VOLTAGE
Ch1
2 A/div
0.5
I(DCIN)
Ch3
2 A/div
ILOAD
Ch4
500 mV/div
I(SYS)
VICM
Battery Charge Current Accuracy - %
Ch2
5 A/div
0
t − Time = 1 ms/div
-0.5
-1
-1.5
-2
-2.5
3-Cell at 12.592 V,
ICHG at 4.096A
with DCIN = 20 V
-3
4
5
6
7
9
8
10
11
12
13
Battery Voltage - V
Figure 14.
Figure 15.
EFFICIENCY
BATTERY CHARGE CURRENT
BATTERY REMOVAL (From Constant Current Mode)
Ch4
2 V/div
98
4-Cell
96
VFB
94
Ch2
10 V/div
3-Cell
Efficiency - %
92
2-Cell
90
PH
1-Cell
88
Ch1
2 A/div
86
1 - 4 Cell
ICHG at 8.064A
with DCIN = 20 V
84
I(IND)
82
t − Time = 4 ms/div
80
0
1
2
3
4
5
6
7
8
9
Battery Charge Current - A
CHARGER WHEN ADAPTER REMOVED
ADAPTER REMOVED WHILE CHARGING
Ch1
5 V/div
Figure 17.
Ch1
5 V/div
Figure 16.
DCIN
VREF
ACOK
VREF
ACOK
Ch4
2 V/div
Ch3
2 V/div
ACIN
Ch4
2 V/div
Ch2
Ch3
2 V/div 2 V/div
DCIN
Ch2
10 V/div
PH
t − Time = 4 ms/div
t − Time = 4 ms/div
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
SOFT-START, INDUCTOR CURRENT
AND CHARGE CURRENT
Ch4
1 A/div
Ch3
1 V/div
CE
I(IND)
Ch1
1 A/div
ILOAD
Ch4
5 V/div
PH
VDDP
t − Time = 1 ms/div
Figure 20.
Figure 21.
CHARGE ENABLED by SMBSus
CHARGE DISABLED by SMBSus
Ch1
2 V/div
Ch4
5 V/div
PH
VDDP
VDDP
t − Time = 10 ms/div
Figure 22.
Figure 23.
DEAD-TIME BETWEEN
UGATE OFF AND LGATE ON
DEAD-TIME BETWEEN
LGATE OFF AND UGATE ON
Ch1
2 A/div
I(IND)
PH
UGATE-PH
Ch4
10 V/div
Ch2
10 V/div
UGATE
Math1
5 V/div
Ch3
5 V/div
LGATE
Ch3
Ch2
5 V/div 10 V/div
Ch1
2 A/div
t − Time = 10 ms/div
I(IND)
UGATE
PH
UGATE-PH
LGATE
t − Time = 40 ns/div
t − Time = 40 ns/div
Figure 24.
14
Ch3
1 V/div
ACGOOD
Ch2
10 V/div
ACGOOD
Ch2
10 V/div
SDA
Ch3
1 V/div
SDA
Ch4
5 V/div
Ch1
2 V/div
t − Time = 10 ms/div
Ch4
10 V/div
Ch2
10 V/div
ACGOOD
Math1
5 V/div
Ch1
2 V/div
CHARGE ENABLE/DISABLE
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
BATTERY SHORTED CHARGER RESPONSE,
OVERCURRENT PROTECTION (OCP) AND
CHARGE CURRENT REGULATION
UGATE
Ch3
2 A/div
PHASE
Ch2
10 V/div
Ch2
10 V/div
Ch1
10 V/div
NEAR 100% DUTY CYCLE BOOTSTRAP RECHARGE
PULSE
Ch3
2 A/div
Ch4
5 V/div
I(IND)
VFB
I(IND)
LGATE
t − Time = 400 ms/div
Figure 27.
CONTINUOUS CONDUCTION MODE (CCM)
SWITCHING WAVEFORMS, ICHARGE = 3986 mA
DISCONTINUOUS CONDUCTION MODE (DCM)
SWITCHING WAVEFORMS, ICHARGE = 256 mA
I(IND)
UGATE
Ch2
10 V/div
PH
PH
LGATE
Math1
5 V/div
Ch3
5 V/div
UGATE-PH
LGATE
Math1
5 V/div
UGATE-PH
t − Time = 1 ms/div
t − Time = 1 ms/div
Figure 28.
Figure 29.
OFF-STATE BATTERY CURRENT (LOW Iq)
vs
VFB (BATTERY) VOLTAGE
OFF-STATE DCIN CURRENT (LOW Iq)
vs
DCIN INPUT VOLTAGE (With Adapter Connected)
7
700
6
600
Standby DCIN Current − mA
I(DCIN) − Off-State Current − mA
Ch2
Ch3
5 V/div 10 V/div
UGATE
Ch4
10 V/div
I(IND)
Ch1
500 mA/div
Figure 26.
Ch4
10 V/div
Ch1
2 A/div
t − Time = 400 ms/div
5
4
3
Including current from:
DCIN, CSSP/N, VFB,
CSOP/N, BOOT, PHASE
2
1
500
400
300
200
Adapter Connected
ACIN > 2.4 V,
Charge Disabled by CE pin
CE = Low
100
0
0
-100
0
5
10
15
VFB - Voltage - V
20
25
0
Figure 30.
5
10
15
DCIN - Voltage - V
20
25
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
Ch2
5 V/div
PROGRAMMABLE REFERENCE AND
HYSTERESIS INPUT CURRENT COMPARATOR (With
Pulsed Current)
ICOUT
Ch3
100 mV/div
Ch4
1 V/div
ICREF
IIN
VICM
t − Time = 4 ms/div
Figure 32.
16
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FUNCTIONAL BLOCK DIAGRAM
ENA_BIAS
-
0.6V
ACIN
ACOK
ACOK
+
2.4V
+
ENA
DCIN_UVLO
3.3V
LDO
DCIN
DCIN
VREF
VREF
DCIN_UVLO
(DCIN-VFB)_CMP
ENA
CE
CHRG_ENA
FBO
CSSP
+
-
-
IIN_REG
FBO
EAI
V(CSSP-CSSN)
EAI
IIN_ER
COMP
ERROR
AMPLIFIER
+
CSSN
EAO
EAO
CHRG_ENA
1V
VFB
VBAT_REG
10mA
BOOT
+
BAT_ER
+
20uA
CHRG_ENA
LEVEL
SHIFTER
UGATE
CSOP
+
20X
-
EN
V(CSOP-CSON)
IBAT _ REG
CSON
V(CSOP-CSON)
+
ICH_ER
SYNCH
+
20uA
DC-DC
CONVERTER
PWM LOGIC
PHASE
BAT_SHORT
DCIN
SYNCH
VDDP
6V LDO
10mV +-
V(BTST-PHASE)
-
REFRESH
C BTST
ENA_BIAS
+
VFB
VDDSMB
-
LGATE
+
4V _
BAT_SHORT
+
2.9V +-
IC Tj
+
145degC
-
TSHUT
PGND
SMBus_Bias
SDA
SMBus
Logic
SCL
CHRG_V
(11 bit DAC)
CHRG_I
(6 bit DAC)
INPUT_I
(6 bit DAC)
V(DCIN-VFB)
-
185mV
+
VBAT_REG 145% X IBAT_REG
-
V(CSOP-CSON)
+
ACIN
+
EN
IBAT_REG
(DCIN-VFB)_CMP
CSSP
CSSN
+
VICM
20x
ENA
VICM
ENA_BIAS
CHG_OCP
GND
IIN_REG
ACOV
3.1V
VICM
ICREF
+
-
+
-
NC
DCIN
-
DCIN_UVLO
+
4V +-
NC
VDDSMB
ICOUT
+
2.5V +-
VDDSMB_UVLO
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DETAILED DESCRIPTION
BATTERY VOLTAGE REGULATION
The bq24745 uses a high-accuracy voltage regulator to supply charging voltage. The battery voltage regulation
setting is programmed by the host microcontroller (µC), through the SMBus interface that sets an 11-bit DAC.
The input voltage range of VFB is between 1.024 V and 19.2 V. The per-cell battery termination voltage is a
function of the battery chemistry. (Consult the battery manufacturer to determine this voltage.) The programmed
value should be the per-cell voltage times the number of series cells.
The VFB pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from VFB to GND is
recommended to be as close to the VFB pin as possible to decouple high frequency noise.
BATTERY CURRENT REGULATION
The ChargeCurrent() SMBus 6-bit DAC register sets the maximum charging current. Battery current is sensed by
resistor RSR connected between the CSOP and CSON pins. The maximum full-scale differential voltage between
CSOP and CSON is 80.64 mV. Thus, for a 0.010-Ω sense resistor, the maximum charging current is 8.064 A.
The CSOP and CSON pins are used to measure the voltage across RSR, which has a default value of 10 mΩ.
However, resistors of other values can also be used. A larger sense resistor gives a larger sense voltage and
higher regulation accuracy, but at the expense of higher conduction loss.
INPUT ADAPTER CURRENT REGULATION
The total input current from an AC adapter or other DC source is a function of the system supply current and the
battery charging current. System current normally fluctuates as portions of the systems are powered up or down.
Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current
and the maximum charger input current simultaneously. By using DPM, the input current regulator reduces the
charging current when the input current exceeds the limit set by the InputCurrent() SMBus 6 bit DAC register.
With the high-accuracy limiting, the current capability of the AC adaptor can be lowered, reducing system cost.
In a manner similar to battery-current regulation, adaptor current is sensed by resistor RAC connected between
the CSSP and CSSN pins. The maximum full-scale differential voltage between CSSP and CSSN is 110.04 mV.
Thus, for a 0.010Ω sense resistor, the maximum input current is 11.004 A.
The CSSP and CSSN pins are used to sense RAC with default value of 10 mΩ. However, resistors of other
values can also be used. A larger sense resistor gives a larger sense voltage and a higher regulation accuracy,
but at the expense of higher conduction loss.
ADAPTER DETECT AND POWER UP
An external resistor voltage divider attenuates the adapter voltage before it goes to ACIN. The adapter-detect
threshold should typically be programmed to a value greater than the maximum battery voltage and lower than
the minimum allowed adapter voltage.
If DCIN is below 4 V, the charger is disabled and ACOK goes low.
If ACIN is below 0.6 V but DCIN is above 4 V, part of the bias is enabled, including a crude bandgap reference,
ACFET drive and BATFET drive. VICM is disabled and pulled down to GND. The total quiescent current is less
than 10µA.
When ACIN rises above 0.6 V and DCIN is above 4 V, all the bias circuits are enabled, the VDDP output goes to
6 V, and VREF goes to 3.3 V. VICM becomes valid to proportionally reflect the adapter current.
When ACIN keeps rising and passes 2.4 V, it indicates that a valid AC adapter is present. 200µs later, and the
following occurs:
• ACOKis pulled high through an external pull-up resistor to the host digital voltage rail;
• The charger turns on if all the conditions are satisfied after an additional 2-ms deglitch time. (refer to Enable
and Disable Charging)
18
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ENABLE AND DISABLE CHARGING
The following conditions must be valid before charging is enabled:
• CE is HIGH;
• Adapter is detected (ACIN > 2.4 V);
• Adapter is higher than the DCIN-VFB threshold;
• 200µs delay is complete after adapter detected;
• VDDP and VREF are valid;
• Thermal Shutdown (TSHUT) is not active;
Any of the following conditions stop the charge cycle:
• CE is LOW;
• Adapter is removed;
• Adapter voltage is less than 250 mV above the battery;
• Adapter is over voltage;
• Charge output current is over programmed current;
• TSHUT IC temperature threshold is reached (145°C on rising-edge with 15°C hysteresis).
AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT
The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure
that there is no overshoot or stress on the output capacitors or the power converter. The soft-start function steps
up the charge current into 8 evenly-divided steps, gradually building up to the full programmed charge current.
Each step lasts approximately 1 ms, for a typical rise time of 8 ms. No external components are needed for this
function.
CONVERTER OPERATION
The synchronous-buck PWM converter operates at a fixed frequency (300 kHz) in voltage mode with a
feed-forward control scheme. A type-III compensation network allows the use of ceramic capacitors at the output
of the converter. The input compensation stage is connected between the feedback output (FBO) and the error
amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and
error amplifier output (EAO). The LC output filter has a characteristic resonant frequency that ensures sufficient
phase margin for the target bandwidth.
fo +
The resonant frequency, fo, is given by:
1
2p ǸLoC o
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the converter duty cycle.
The ramp height is 1/15 of the input adapter voltage, always keeping it directly proportional to the input adapter
voltage. This cancels out any loop-gain variation due to an input voltage change, simplifying loop-compensation
design. The ramp is offset by 250 mV in order to allow a 0% duty cycle when the EAO signal is below the ramp.
The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to respond to a 100% duty-cycle
PWM request. The internal gate-drive logic allows a 99.98% duty cycle while ensuring that the N-channel upper
device always has enough voltage to stay fully on. If the BOOT-pin-to-PHASE-pin voltage falls below 4.5 V for
more than 3 cycles, the high-side n-channel power MOSFET is turned off and the low-side n-channel power
MOSFET is turned on to pull the PHASE node down and recharge the BOOT capacitor. Then the high-side
driver returns to 100% duty-cycle operation until the (BOOT-PHASE) voltage is again detected falling low due to
leakage current discharging the BOOT capacitor below 4 V, and the reset pulse is reissued.
The 300-kHz fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature, simplifying output-filter design and keeping it out of the
audible-noise region. The charge-current sense resistor (RSR) should be positioned with half or more of the total
output capacitance placed before RSR, contacting both RSR and the output inductor; and the remaining
capacitance placed after RSR. The output capacitance should be divided and placed on either side of RSR. A ratio
of 50:50% gives the best performance, but the node in which the output inductor and RSR connect should have a
minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching
noise and give better accuracy. The type-III compensation provides phase boost near the crossover frequency to
provide sufficient phase margin.
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SYNCHRONOUS AND NON-SYNCHRONOUS OPERATION
The charger operates in non-synchronous mode when the sensed charge current is below the internal ISYNSET
value of 13 mV (1.3 A) falling, and 0.8 mV (800 mA) rising (with built-in hysteresis). Otherwise, the charger
operates in synchronous mode.
In synchronous mode, the low-side n-channel power MOSFET is on, and the high-side n-channel power
MOSFET is off. The internal gate-drive logic enforces break-before-make switching to prevent shoot-through
currents. During the 30-ns dead time when both FETs are off, the back diode of the low-side power MOSFET
conducts the inductor current. Having the low-side FET turned on keeps the power dissipation low, and safely
allows high-current charging. In synchronous mode, the inductor current is always flowing and operates in
Continuous Conduction Mode (CCM), creating a fixed two-pole system.
In non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the
break-before-make dead-time, the low-side n-channel power MOSFET turns on for approximately 80 ns, then the
low-side power MOSFET turns off and stays off until the beginning of the next cycle, when the high-side power
MOSFET is turned on again. The 80-ns low-side MOSFET on-time is required to ensure that the bootstrap
capacitor is always charged and able to keep the high-side power MOSFET turned on during the next cycle. This
is important for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a
voltage, and can both source and sink current. The 80-ns low-side pulse pulls the PHASE node (connection
between high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the VDDP LDO
value. After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from flowing. The
inductor current is blocked by the off-state low-side MOSFET, and the inductor current becomes discontinuous.
This mode is called Discontinuous Conduction Mode (DCM).
In DCM operation, the loop response automatically changes, and acts as a single-pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. At very low currents, the loop response is slower, because there is less sinking current available to
discharge the output voltage. At very low currents during non-synchronous operation, there may be a small
amount of negative inductor current during the 80-ns recharge pulse. This should be low enough to be absorbed
by the input capacitance.
When the converter goes into 0% duty cycle, neither MOSFET turns on (no 80-ns recharge pulse), and there is
no discharge from the battery.
ISYNSET CONTROL (CHARGE UNDERCURRENT)
In bq24745, ISYN is the internally-set ISYNSET value as the charge-current threshold at which the charger
switches from non-synchronous operation to synchronous operation. The low-side driver turns on for only 80 ns
to charge the boost capacitor. This is important to prevent negative inductor current, which may cause a boost
effect in which the input voltage increases as power is transferred from the battery to the input capacitors. This
can lead to an overvoltage condition on the DCIN node, and potentially can damage the system. This
programmable value allows setting the current threshold for any inductor ripple current to avoid negative inductor
current. The minimum synchronous threshold should be set from 50%-100% of the inductor ripple current, where
the inductor ripple current is calculated using Equation 1.
I RIPPLE_MAX
v I SYN v I RIPPLE_MAX
2
ǒVIN_MAX * VBAT_MINǓ
and
I RIPPLE_MAX +
ǒ
Ǔ ǒǓ
VBAT_MIN
VIN_MAX
1
fs
LMIN
(1)
where
VIN_MAX: maximum adapter voltage
VBAT_MIN: minimum BAT voltage
fS: switching frequency
LMIN: minimum output inductor
The ISYNSET comparator, or charge undercurrent comparator, compares the voltage between CSOP-CSON and
the 13-mV internal threshold. The threshold is set internally to 13 mV on the falling edge and 8 mV on the rising
edge (with built-in hysteresis) with 10% variation.
20
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HIGH ACCURACY VICM USING CURRENT SENSE AMPLIFIER (CSA)
An industry-standard, high-accuracy current-sense amplifier (CSA) provides an analog output voltage at the
VICM pin that can be used by a host system to monitor the input current. The CSA amplifies the input sensed
voltage of CSSP-CSSN by 20× through the VICM pin. The VICM output is a voltage source 20× the input
differential voltage. When DCIN is above 4 V and ACIN is above 0.6 V, VICM no longer stays at ground, but
becomes active. A lower voltage can be used by connecting a resistor divider from VICM to GND, while still
achieving good accuracy over temperature if the resistors are matched by their thermal coefficients.
A 0.1µF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional
RC filter is optional, after the 0.1µF capacitor, if additional filtering is desired. Note that adding filtering also adds
additional response delay.
VDDSMB INPUT SUPPLY
The VDDSMB input provides bias power to the SMBus interface logic. Connect VDDSMB to an external 3.3 V or
5 V supply rail to keep the SMBus interface active while the supply to DCIN is removed. When VDDSMB is
biased, the internal registers are maintained, and SMBus communication can occur between the host and the
charger. Bypass VDDSMB to GND with a 0.1-µF or greater ceramic capacitor. The VDDSMB UVLO threshold is
2.7 V rising and 250 mV falling (with hysteresis). The SMBus is always active and can be written to or read from
whenever VDDSMB is above the VDDSMB UVLO threshold.
INPUT UNDER VOLTAGE LOCK OUT (UVLO)
The system must have a minimum 4 V DCIN voltage from the input adapter to allow proper charger operation.
When the DCIN voltage is below 4 V, the bias circuits VDDP and VREF stay inactive, even with ACIN above
0.6 V.
BATTERY OVERVOLTAGE PROTECTION
The converter will not allow the high-side FET to turn-on when the battery voltage at VFB exceeds 104% of the
regulation voltage set-point, until the VFB voltage returns below 101% of the regulation voltage. This allows quick
response to an overvoltage condition – such as occurs when the load is removed or the battery is disconnected.
A 10-mA current sink from VFB to PGND is on only during charge and allows discharging the stored output
inductor energy that is transferred to the output capacitors.
BATTERY SHORTED (Battery Undervoltage) PROTECTION AND BATTERY TRICKLE CHARGING
The bq24745 has a VFB SHORT comparator monitoring the output battery VFB voltage. If the voltage falls below
2.5 V (absolute, fixed), a battery-short status is detected. The charger continues charging at the value
programmed on the ChargeCurrent(0x14) register down to 2.5 V falling, and 2.7 V rising on the VFB pin.
The bq24745 automatically reduces the charge current limit to a fixed 128 mA to trickle charge the battery, when
the voltage on the VFB pin falls below 2.5 V. The charge current returns to the value programmed on the
ChargeCurrent(0x14) register, when the VFB pin voltage rises above 2.7 V.
This function provides short circuit protection from the battery node, and it also provides a safe trickle charge to
close deeply discharged open packs.
INPUT CURRENT COMPARATOR TRIP DETECTION
To optimize system performance, the host monitors the adapter current. When the adapter current is above a
threshold set via ICREF, the ICOUT pin asserts low to act as an alarm signal to the host, indicating that input
power has exceeded the programmed limit, allowing the host to throttle back system power by reducing clock
frequency, lowering rail voltages, or disabling parts of the system. The ICOUT pin is an open-drain output, and
must have a pull-up resistor connected. The output is logic HI when the VICM output voltage [VICM = 20 ×
V(CSSP-CSSN)] is lower than the ICREF input voltage. The ICREF threshold is set by an external resistor
divider using VREF. A hysteresis can be programmed by connecting a positive feedback resistor from the ICOUT
pin to the ICREF pin.
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ACOK
Comparator
ACIN
ENABLE VICM
Comparator
0.6V
+
-
+
2.4V
t_dg
rising
100us
ACOK
ACOK
ACOK_DG
ENA_BIAS & ENA_VICM
CHARGE_DISABLE
CSSP
1k
VICM
Current Sense
Amplifier
+
-
CSSN
VICM
Error
Amplifier
Disable
20k
VICM
+
VICM
Disable
Program Hysteresis of
comparator
by putting a resistor in feedback
from ICOUT pin to ICREF pin.
Input Current
Comparator
ICOUT
+
-
Figure 33. ACOK, ICREF, and ICOUT Logic
CHARGE OVERCURRENT PROTECTION
The charger has a secondary overcurrent monitor that prevents the charge current from exceeding 145% of the
programmed charge current. The high-side gate drive turns off when the overcurrent is detected, and
automatically resumes when the current falls below the overcurrent threshold.
THERMAL SHUTDOWN PROTECTION
The QFN package has low thermal impedance, providing good thermal conduction from the silicon to the
ambient air, to keep junction temperatures low. As an added level of protection, the charger converter turns off
and self-protects whenever the junction temperature exceeds the TSHUT threshold of 155°C. The charger stays
off until the junction temperature falls below 135°C.
OPEN-DRAIN STATUS OUTPUTS (ACOK, ICOUT)
Two status outputs are available; both require external pull up resistors to pull the pins to the system digital rail
for a high level.
The ACOK open-drain output goes high when ACIN is above 2.4 V. It indicates that a functional adapter is
providing a valid input voltage.
The ICOUT open-drain output goes low when the input current is higher than the threshold programmed via the
ICREF pin. Hysteresis can be programmed by adding a resistor from the ICREF pin to the ICOUT pin.
SMBus INTERFACE
The bq24745 operates as a slave, receiving control inputs from the host through the SMBus interface.
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BATTERY-CHARGER COMMANDS
The bq24745 supports four battery-charger commands that use either Write-Word or Read-Word protocols, as
summarized in Table 2. ManufacturerID() and DeviceID() can be used to identify the bq24745. On the bq24745,
the ManufacturerID() command always returns 0x0040 and the DeviceID() command always returns 0x0006.
Table 2. Battery Charger SMBus Registers
REGISTER ADDRESS
REGISTER NAME
READ/WRITE
DESCRIPTION
POR STATE
0x14
ChargeCurrent()
Read or Write
6-Bit Charge Current Setting
0x0000
0x15
ChargeVoltage()
Read or Write
11-Bit Charge Voltage Setting
0x0000
0x3F
InputCurrent()
Read or Write
6-Bit Input Current Setting
0x0080
0xFE
ManufacturerID()
Read Only
Manufacturer ID
0x0040
0xFF
DeviceID()
Read Only
Device ID
0x0006
SMBus Interface
The bq24745 receives commands from the SMBus interface. The bq24745 uses a simplified subset of the
commands documented in the System Management Bus Specification V1.1, which can be downloaded from
www.smbus.org. The bq24745 uses the SMBus Read-Word and Write-Word protocols (see Figure 34) to
communicate with the smart battery. The bq24745 performs only as an SMBus slave device with address
0b0001001_ (0x12), and does not initiate communication on the bus. In addition, the bq24745 has two
identification (ID) registers (0xFE): a 16-bit device ID register and a 16-bit manufacturer ID register (0xFF).
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition; a high-to-low transition on SDA while SCL is
high. When the master has finished communicating, the master issues a STOP condition, which is a low-to-high
transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 35 and Figure 36
show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes
are transmitted between the START and STOP conditions. The SDA state changes only while SCL is low, except
for the START and STOP conditions. Data is transmitted in 8-bit bytes, sampled on the rising edge of SCL. Nine
clock cycles are required to transfer each byte to or from the bq24745 because either the master or the slave
acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24745 supports the charger
commands as described in Table 5.
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a) Write-Word Format
S
SLAVE
ADDRESS
W
ACK
COMMAND
BYTE
ACK
7 BITS
1b
MSB LSB
0
1b
8 BITS
1b
8 BITS
0
MSB LSB
0
MSB LSB
Preset to 0b0001001
LOW DATA
BYTE
ChargeCurrent() = 0x14 D7
ChargeVoltage() = 0x15
InputCurrent() = 0x3F
HIGH DATA
BYTE
ACK
1b
8 BITS
1b
0
MSB L SB
0
ACK
D0
D15
P
D8
b) Read-Word Format
S
SLAVE
ADDRESS
W
ACK
COMMAND
BYTE
ACK
7 BITS
1b
1b
8 BITS
1b
MSB LSB
0
0
MSB LSB
0
Preset to 0b0001001
S
SLAVE
ADDRESS
R
ACK
LOW DATA
BYTE
ACK
HIGH DATA
BYTE
NACK
7 BITS
1b
1b
8 BITS
1b
8 BITS
1b
1
0
MSB
ChargeSpecInfo() = 0x11
ChargerStatus() = 0x13
ChargeMode() = 0x14
ChargeMode() = 0x15
ChargeMode() = 0x3F
LSB
Preset to
0b0001001
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
MSB
D7
LSB
0
D0
MSB
D15
LSB
P
1
D8
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 34. SMBus Write-Word and Read-Word Protocols
Figure 35. SMBus Write Timing
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A
tLOW tHIGH
B
C
D
E
F
G
H
I
J
K
SMBCLK
SMBDATA
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS C LOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW I = ACKNOWLEDGE CLOCK PULSE
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER J = STOP CONDITION
G = MSB OF DATA CLOCKED INTO MASTER K = NEW START CONDITION
H = LSB OF DATA CLOCKED INTO MASTER
Figure 36. SMBus Read Timing
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SETTING THE CHARGE VOLTAGE
To program the output charge voltage regulation setpoint, use the SMBus to write a 16-bit ChargeVoltage()
command using the data format listed in Table 3. The ChargeVoltage() command uses the Write-Word protocol
(see Figure 34). The command code for ChargeVoltage() is 0x15 (0b00010101). The bq24745 provides a
charge-voltage range of 1.024 V to 19.200 V, with 16 mV resolution. Set ChargeVoltage() below 1.024 V to
terminate charging. Upon reset, the ChargeVoltage() and ChargeCurrent() values are cleared and the charger
remains off until both the ChargeVoltage() and the ChargeCurrent() command are sent. Both UGATE and
LGATE pins remain low until the charger is restarted.
Table 3. Charge Voltage Register (0x15)
26
BIT
BIT NAME
0
–
Not used.
DESCRIPTION
1
–
Not used.
2
–
Not used.
3
–
Not used.
4
Charge Voltage, DACV 0
0 = Adds 0 mV of charger voltage, 1024 mV min.
1 = Adds 16 mV of charger voltage
5
Charge Voltage, DACV 1
0 = Adds 0 mV of charger voltage, 1024 mV min.
1 = Adds 32 mV of charger voltage
6
Charge Voltage, DACV 2
0 = Adds 0 mV of charger voltage, 1024 mV min.
1 = Adds 64 mV of charger voltage.
7
Charge Voltage, DACV 3
0 = Adds 0 mV of charger voltage, 1024 mV min.
1 = Adds 128 mV of charger voltage.
8
Charge Voltage, DACV 4
0 = Adds 0 mV of charger voltage, 1024 mV min.
1 = Adds 256 mV of charger voltage.
9
Charge Voltage, DACV 5
0 = Adds 0 mV of charger voltage, 1024 mV min.
1 = Adds 512 mV of charger voltage
10
Charge Voltage, DACV 6
0 = Adds 0 mV of charger voltage.
1 = Adds 1024 mV of charger voltage.
11
Charge Voltage, DACV 7
0 = Adds 0 mV of charger voltage.
1 = Adds 2048 mV of charger voltage.
12
Charge Voltage, DACV 8
0 = Adds 0 mV of charger voltage.
1 = Adds 4096 mV of charger voltage.
13
Charge Voltage, DACV 9
0 = Adds 0 mV of charger voltage.
1 = Adds 8192 mV of charger voltage.
14
Charge Voltage, DACV 10
0 = Adds 0 mV of charger voltage.
1 = Adds 16384 mV of charger voltage.
15
–
Not used.
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SETTING THE CHARGE CURRENT
To set the charge current, use the SMBus to write a 16bit ChargeCurrent() command using the data format listed
in Table 4. The ChargeCurrent() command uses the Write-Word protocol (see Figure 34). The command code for
ChargeCurrent() is 0x14 (0b00010100). When using a 10-mΩ sense resistor, the bq24745 provides a
charge-current range of 128 mA to 8.064 A, with 128 mA resolution. Set ChargeCurrent() to 0 to terminate
charging. Upon reset, the ChargeVoltage() and ChargeCurrent() values are cleared and the charger remains off
until both the ChargeVoltage() and the ChargeCurrent() commands are received. Both UGATE and LGATE pins
remain low until the charger is restarted.
The bq24745 includes a foldback current limit when the battery voltage is low. If the battery voltage is less than
2.5 V, the charge current is temporarily set to 128 mA. The ChargeCurrent() register value is preserved, and
becomes active again when the battery voltage is higher than 2.7 V. This function effectively provides a fold-back
current limit, protecting the charger during short circuit and overload.
Table 4. Charge Current Register (0x14), Using 10mΩ Sense Resistor
BIT
BIT NAME
DESCRIPTION
0
–
Not used.
1
–
Not used.
2
–
Not used.
3
–
Not used.
4
–
Not used.
5
–
Not used.
6
–
Not used.
7
Charge Current, DACI 0
0 = Adds 0 mA of charger current
1 = Adds 128 mA of charger current.
8
Charge Current, DACI 1
0 = Adds 0 mA of charger current
1 = Adds 256 mA of charger current.
9
Charge Current, DACI 2
0 = Adds 0 mA of charger current
1 = Adds 512 mA of charger current
10
Charge Current, DACI 3
0 = Adds 0 mA of charger current.
1 = Adds 1024 mA of charger current.
11
Charge Current, DACI 4
0 = Adds 0 mA of charger current.
1 = Adds 2048 mA of charger current.
12
Charge Current, DACI 5
0 = Adds 0 mA of charger current.
1 = Adds 4096 mA of charger current, 8064 mA.
13
–
Not used.
14
–
Not used.
15
–
Not used.
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SETTING THE CHARGE CURRENT
System current normally fluctuates as portions of the system are powered up or down, or enter low-power mode.
By using the input-current limit circuit, the output-current requirement of the AC wall adapter can be lowered,
reducing system cost.
The total input current, from a power-line wall adapter or other DC source, is the sum of the system supply
current and the current required by the charger. When the input current exceeds the programmed input current
limit, the bq24745 decreases the charge current to provide priority to the system load current. As the system
supply current rises, the available charge current drops linearly to zero. Thereafter, the total input current can
increase without limit.
The internal amplifier compares the differential voltage between CSSP and CSSN to a scaled voltage set by the
InputCurrent() command (see Table 5). The total input current is the sum of the device supply current, the
charger input current, and the system load current. The total input current can be estimated as follows:
Table 5. Input Current Register (0x3F), Using 10mΩ Sense Resistor
BIT
BIT NAME
0
–
Not used.
1
–
Not used.
2
–
Not used.
3
–
Not used.
4
–
Not used.
5
–
Not used.
6
–
Not used.
7
Charge Current, DACS 0
0 = Adds 0 mA of charger current
1 = Adds 256 mA of charger current.
8
Charge Current, DACS 1
0 = Adds 0 mA of charger current
1 = Adds 512 mA of charger current
9
Charge Current, DACS 2
0 = Adds 0 mA of charger current.
1 = Adds 1024 mA of charger current.
10
Charge Current, DACS 3
0 = Adds 0 mA of charger current.
1 = Adds 2048 mA of charger current.
11
Charge Current, DACS 4
0 = Adds 0 mA of charger current.
1 = Adds 4096 mA of charger current
12
Charge Current, DACS 5
0 = Adds 0 mA of charger current.
1 = Adds 8192 mA of charger current, 11004 mA max.
13
–
Not used.
14
–
Not used.
15
–
Not used.
I INPUT + I LOAD )
ƪ
I LOAD
DESCRIPTION
ƫ
VBATTERY
VIN
h
) I BIAS
(2)
where η is the efficiency of the DC-DC converter (typically 85% to 95%).
To set the input current limit, write a 16-bit InputCurrent() command using the data format listed in Table 5. The
InputCurrent() command uses the Write-Word protocol (see Figure 34). The command code for InputCurrent() is
0x3F (0b00111111). When using a 10-mΩ sense resistor, the bq24745 provides an input-current limit range of
256 mA to 11.004 A, with 256 mA resolution. InputCurrent() settings from 1 mA to 256 mA result in a current limit
of 256 mA. Upon reset the input current limit is 256 mA.
CHARGER TIMEOUT
The bq24745 includes a timer to terminate charging if the charger does not receive a ChargeVoltage() or
ChargeCurrent() command within 175 s. If a timeout occurs, both ChargeVoltage() and ChargeCurrent()
commands must be resent to re-enable charging.
28
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REMOTE SENSE
The bq24745 has a dedicated remote sense pin, VFB, which allows the rejection of board resistance and
selector resistance. To fully utilize remote sensing, connect VFB directly to the battery interface through an
unshared battery-sense Kelvin trace, and place a 0.1-µF ceramic capacitor near the VFB pin to GND (see
Figure 1).
Remote Kelvin Sensing provides higher regulation accuracy, by eliminating parasitic voltage drops. Remote
sensing cancels the effect of impedance in series with the battery. This impedance normally causes the battery
charger to prematurely enter constant-voltage mode with reducing charge current.
INPUT CURRENT MEASUREMENT
Use VICM to monitor the system-input current sensed across CSSP and CSSN. The voltage at VICM is
proportional to the input current by the equation:
VICM = 20 × V(CSSP-CSSN) = 20 × (Iin × Rsense)
where Iin is the input DC current supplied by the AC adapter, 20 is the gain, and Rsense is the input sense resistor.
VICM has a 0 to (VREF–100 mV) output voltage range. Leave VICM open if not used. Use a 100 pF (maximum)
ceramic capacitor.
VDDP GATE DRIVE REGULATOR
An integrated low-dropout (LDO) linear regulator provides a 6-V supply derived from DCIN, for high efficiency,
and delivers over 75 mA of load current. The LDO powers the gate drivers of the n-channel MOSFETs. VDDP
has a minimum current limit of 90 mA. This allows the bq24745 to work with high gate charge (both high-side
and low-side) MOSFETs. Bypass VDDP to PGND with a 1-µF or greater ceramic capacitor.
AC ADAPTER DETECTION
The bq24745 includes a hysteretic comparator that detects the presence of an AC power adapter. When ACIN is
greater than 2.4 V, the open-drain ACOK output becomes high impedance. Connect a 10-kΩ pullup resistor
between the pull-up rail and ACOK. Use a resistive voltage-divider from the adapter’s output to the ACIN pin to
set the appropriate detection threshold. Select the resistive voltage-divider not to exceed the 7 V absolute
maximum rating of ACIN.
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bq24745
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SLUS761 – DECEMBER 2007
VDDSMB SUPPLY
The VDDSMB input provides power to the SMBus interface. Connect VDDSMB to VREF, or apply an external
supply to VDD to keep the SMBus interface active while the supply to DCIN is removed. When VDDSMBus is
biased, the internal register contents are maintained. Bypass VDDSMB to GND with a 0.1µF or greater ceramic
capacitor.
OPERATING CONDITIONS
The bq24745 has the following operating states:
• Adapter Present: When DCIN is greater than 4 V and ACIN is greater than 2.4 V, the adapter is considered
to be present. In this condition, both the VDDP and VREF function properly and battery charging is allowed:
– Charging: The total bq24745 quiescent current when charging is 1 mA (max) plus the current required to
drive the MOSFETs.
– Not Charging: To disable charging, set either ChargeCurrent() or ChargeVoltage() to zero. When the
adapter is present and charging is disabled, the total adapter quiescent current is less than 1.5 mA and
the total battery quiescent current is less than 200 µA.
• Adapter Absent (Power Fail): When VCSSP is less than VCSON + 150 mV, the bq24745 is in the power-fail
state, since the DC-DC converter is in dropout. The charger does not attempt to charge in the power-fail
state. Typically, this occurs when the adapter is absent. When the adapter is absent, the total bq24745
quiescent battery current is less than 1µA (max).
• VDDSMBus Undervoltage (POR): When VDD is less than 2.5 V, the VDD supply is in an undervoltage state
and the internal registers are in their power-on-reset (POR) state. The SMBus interface does not respond to
commands. When VDD rises above 2.7 V, the bq24745 is in a power-on-reset state. Charging does not occur
until the ChargeVoltage() and ChargeCurrent() commands are sent. When VDD is greater than 2.5 V, SMBus
register contents are preserved.
The bq24745 allows charging under the following conditions:
1. DCIN > 4 V, VDDP > 4 V, VREF > 3.1 V
2. VCSSP > VCSON + 250 mV (15 mV falling threshold)
3. VDDSMBus > 2.5 V
Charge Termination for Li-Ion or Li-Polymer
The primary termination method for Li-Ion and Li-Polymer is minimum current. Secondary temperature
termination also provides additional safety. The host controls the charge initiation and the termination. A battery
pack gas gauge assists the hosts on setting the voltages and determining when to terminate based on the
battery pack state of charge.
30
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Product Folder Link(s) :bq24745
bq24745
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SLUS761 – DECEMBER 2007
Component List for Typical System Circuit of Figure 2
PART DESIGNATOR
QTY
DESCRIPTION
Q1, Q2, Q3
3
P-channel MOSFET, –30V, –6A, SO-8, Vishay-Siliconix, Si4435
Q4, Q2
2
N-channel MOSFET, 30V, 12.5A, SO-8, Fairchild, FDS6680A
D1
1
Diode, Dual Schottky, 30V, 200mA, SOT23, Fairchild, BAT54C
RAC, RSR
2
Sense Resistor, 10 m W, 2010, Vishay-Dale, WSL2010R0100F
L1
1
Inductor, 10µH, 7A, 31m Vishay-Dale, IHLP5050FD-01
C1, C6, C7, C11, C12
5
Capacitor, Ceramic, 10µF, 35V, 20%, X5R, 1206, Panasonic, ECJ-3YB1E106M
C4, C8, C10
3
Capacitor, Ceramic, 1µF, 25V, 10%, X7R, 2012, TDK, C2012X7R1E105K
C2, C3, C9, C13–C15
6
Capacitor, Ceramic, 0.1µF, 50V, 10%, X7R, 0805, Kemet, C0805C104K5RACTU
C5
1
Capacitor, Ceramic, 100pF, 25V, 10%, X7R, 0805, Kemet
R3, R4, R5
3
Resistor, Chip, 10kΩ, 1/16W, 5%, 0402
R1
1
Resistor, Chip, 432kΩ, 1/16W, 1%, 0402
R2
1
Resistor, Chip, 66.5kΩ, 1/16W, 1%, 0402
R6
1
Resistor, Chip, 33kΩ, 1/16W, 5%, 0402
R7
1
Resistor, Chip, 200kΩ, 1/16W, 1%, 0402
R8
1
Resistor, Chip, 24.9kΩ, 1/16W, 1%, 0402
R9
1
Resistor, Chip, 1.8MΩ, 1/16W, 1%, 0402
GLOSSARY
VICM output Voltage of Input Current Monitor
ICREF Input Current Reference - sets the threshold for the ??? input current ?? limit ??
DPM Dynamic Power Management
CSOP, CSON Current Sense Output of battery (??) positive and negative
These pins are used with an external low-value series resistor to monitor the current to and
from the battery pack.
CSSP, CSSN Current Sense Supply (??) positive and negative
These pins are used with an external low-value series resistor to monitor the current from
the adapter supply.
POR Power on reset
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31
PACKAGE OPTION ADDENDUM
www.ti.com
31-Dec-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24745RHDR
ACTIVE
QFN
RHD
28
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24745RHDT
ACTIVE
QFN
RHD
28
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24745RHDR
RHD
28
SITE 41
330
12
5.3
5.3
1.5
8
12
Q2
BQ24745RHDT
RHD
28
SITE 41
180
12
5.3
5.3
1.5
8
12
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2008
Device
Package
Pins
Site
Length (mm)
Width (mm)
BQ24745RHDR
RHD
28
SITE 41
346.0
346.0
29.0
BQ24745RHDT
RHD
28
SITE 41
190.0
212.7
31.75
Pack Materials-Page 2
Height (mm)
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