Cypress CYM1441PZ-35C 256k x 8 static ram module Datasheet

41
CYM1441
256K x 8 Static RAM Module
Features
Functional Description
• High-density 2-megabit SRAM module
• High-speed CMOS SRAMs
— Access time of 20 ns
• Low active power
— 5.3W (max.)
• SMD technology
• Separate data I/O
• 60-pin ZIP package
• TTL-compatible inputs and outputs
• Low profile
— Max. height of 0.5 in.
• Small PCB footprint
— 1.14 sq. in.
The CYM1441 is a very high performance 2-megabit static
RAM module organized as 256K words by 8 bits. The module
is constructed using eight 256K x 1 static RAMs in SOJ packages mounted onto an epoxy laminate substrate with pins. Two
chip selects (CSL and CSU) are used to independently enable
the upper and lower 4 bits of the data word. Writing to the
memory module is accomplished when the chip select (CS)
and write enable (WE) inputs are both LOW. Data on the eight
input pins (DI0 through DI7) is written into the memory location
specified on the address pins (A0 through A17). Reading the
device is accomplished by taking chip select (CS) LOW while
write enable (WE) remains inactive or HIGH. Under these conditions, the contents of the memory location specified on the
address pins will appear on the appropriate data output pins
(DO0 through DO7). The data output pins remain in a highimpedance state unless the module is selected and write enable (WE) is HIGH.Two pins (PD0 and PD1) are used to identify
module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged.
Logic Block Diagram
Pin Configuration
ZIP
TopView
A0 - A17
WE
CSU
256K x 1
SRAM
256K x 1
SRAM
256K x 1
SRAM
DI4 - DI7
CSL
256K x 1
SRAM
256K x 1
SRAM
256K x 1
SRAM
(OPEN)PD 0
NC
VCC
DI0
DO0
A0
A2
A4
256K x 1
A6
SRAM
GND
DI1
DO1
WE
DO4 - DO7
A9
CSL
256K x 1
SRAM
DO0 - DO3
DI0 - DI3
Cypress Semiconductor Corporation
Document #: 38-05271 Rev. **
•
3901 North First Street
•
San Jose
•
NC
NC
VCC
DI2
DO2
A10
A12
A14
A16
NC
DI3
DO3
NC
NC
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
GND
PD1 (GND)
NC
DI4
DO4
NC
A1
A3
A5
A7
DI5
DO5
VCC
A8
NC
CSU
NC
NC
DI6
DO6
GND
A11
A13
A15
A17
DI7
DO7
VCC
NC
NC
CA 95134 • 408-943-2600
Revised March 15, 2002
CYM1441
Selection Guide
1441-20
1441-25
1441-35
1441-45
Maximum Access Time (ns)
20
25
35
45
Maximum Operating Current (mA)
960
960
960
960
Maximum Standby Current (mA)
320
320
320
320
Shaded area contains preliminary information.
Maximum Ratings
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
(Above which the useful life may be impaired.)
DC Input Voltage ............................................–0.5V to +7.0V
Storage Temperature ................................. –55°C to +125°C
Ambient Temperature with
Power Applied............................................... –10°C to +85°C
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 12.0 mA
VIH
Input HIGH Voltage
Min.
Max.
Unit
2.4
[1]
V
0.4
V
2.2
VCC
V
−0.5
0.8
V
VIL
Input LOW Voltage
IIX
Input Load Current
GND < VI < VCC
–80
+80
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–50
+50
µA
ICC
VCC Operating Supply Current
VCC = Max., IOUT = 0 mA, CS < VIL
960
mA
ISB1
Automatic CS
Power-Down Current
Max. VCC, CS > VIH,
Min. Duty Cycle = 100%
320
mA
ISB2
Automatic CS
Power-Down Current
Max. VCC, CS > VCC - 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V
160
mA
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
60
pF
15
pF
AC Test Loads and Waveforms
R1329 Ω
R1329 Ω
5V
5V
OUTPUT
OUTPUT
R2
202Ω
30 pF
INCLUDING
JIG AND
SCOPE
90%
R2
202Ω
5 pF
Equivalent to:
OUTPUT
GND
< 5 ns
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
3.0V
10%
90%
10%
< 5 ns
(b)
THÉVENIN EQUIVALENT
125Ω
1.9V
Notes:
1. VIN (min.) = –3.0V for pulse widths less than 20 ns.
2. Tested on a sample basis.
Document #: 38-05271 Rev. **
Page 2 of 6
CYM1441
Switching Characteristics Over the Operating Range[3]
1441-20
Parameter
Description
Min.
1441-25
Max.
Min.
Max.
1441-35
Min.
Max.
1441-45
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACS
CS LOW to Data Valid
tLZCS
CS LOW to Low Z
25
20
25
3
3
20
tHZCS
CS HIGH to High Z
tPU
CS LOW to Power-Up
tPD
CS HIGH to Power-Down
3
12
35
0
20
45
35
45
25
ns
ns
30
0
35
ns
ns
3
0
25
ns
3
3
15
0
45
3
25
3
[4]
35
ns
ns
45
ns
WRITE CYCLE[5]
tWC
Write Cycle Time
20
25
35
45
ns
tSCS
CS LOW to Write End
15
20
30
35
ns
tAW
Address Set-Up to Write End
15
20
30
35
ns
tHA
Address Hold from Write End
2
2
2
2
ns
tSA
Address Set-Up to Write Start
0
0
0
2
ns
tPWE
WE Pulse Width
15
20
25
30
ns
tSD
Data Set-Up to Write End
13
15
20
20
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tLZWE
WE HIGH to Low Z
3
tHZWE
WE LOW to High Z[4]
0
3
13
0
3
15
0
3
20
0
ns
25
ns
Shaded area contains preliminary information.
Switching Waveforms
[6,7]
Read Cycle No. 1
tRC
ADDRESS
tAA
tOHA
DATAOUT
PREVIOUS DATA VALID
DATA VALID
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady state voltage.
5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
6. WE is HIGH for read cycle.
7. Device is continuously selected, CS = VIL.
Document #: 38-05271 Rev. **
Page 3 of 6
CYM1441
Switching Waveforms (continued)
Read Cycle No. 2
[6,8]
tRC
CS
tACS
tHZCS
tLZCS
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATAOUT
tPD
tPU
ICC
VCC
SUPPLY
CURRENT
50%
50%
ISB
Write Cycle No. 1 (WE Controlled) [5]
tWC
ADDRESS
tSCS
CS
tAW
tSA
tHA
tPWE
WE
tSD
DATAIN
tHD
DATA VALID
tHZWE
DATAOUT
tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
Write Cycle No. 2 (CS Controlled)
[5,9]
tWC
ADDRESS
tSCS
tSA
CS
tAW
tHA
tPWE
WE
tSD
DATAIN
tHD
DATA VALID
tHZWE
DATAOUT
HIGH IMPEDANCE
DATA UNDEFINED
Notes:
8. Address valid prior to or coincident with CS transition LOW.
9. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05271 Rev. **
Page 4 of 6
CYM1441
Truth Table
CS
WE
Input/Output
Mode
H
X
High Z
Deselect/Power-Down
L
H
Data Out
Read
L
L
Data In
Write
Ordering Information
Speed
Ordering Code
Package
Name
Package Type
Operating
Range
20
CYM1441PZ-20C
PZ04
60-Pin ZIP Module
Commercial
25
CYM1441PZ-25C
PZ04
60-Pin ZIP Module
Commercial
35
CYM1441PZ-35C
PZ04
60-Pin ZIP Module
Commercial
45
CYM1441PZ-45C
PZ04
60-Pin ZIP Module
Commercial
Shaded area contains preliminary information.
Package Diagrams
60-Pin ZIP Module PZ04
BottomView
0.330
MAX
3.440
3.460
0.050
0.050
0.500
MAX
0.120
0.150
0.008
0.014
0.135
0.165
0.015
0.025
0.250
TYP
0.100
TYP
0.050
TYP
0.100
TYP
Pin 1
DIMENSIONS IN INCHES
MIN.
MAX.
Document #: 38-05271 Rev. **
Page 5 of 6
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYM1441
Document Title: CYM1441 256K x 8 Static RAM Module
Document Number: 38-05271
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
114172
3/19/02
DSG
Document #: 38-05271 Rev. **
Description of Change
Change from Spec number: 38-M-00020 to 38-05271
Page 6 of 6
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