Cypress CY62147EV18LL-55BVXI 4-mbit (256k x 16) static ram Datasheet

CY62147EV18 MoBL2™
4-Mbit (256K x 16) Static RAM
Features
■
Very high speed: 55 ns
■
Wide voltage range: 1.65V–2.25V
■
Pin compatible with CY62147DV18
■
Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 7 µA
■
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH or both BLE and BHE are
HIGH). The input and output pins (IO0 through IO15) are placed
in a high impedance state when:
Ultra low active power
❐ Typical active current: 2 mA @ f = 1 MHz
■
Ultra low standby power
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Available in a Pb-free 48-Ball VFBGA package
■
Deselected (CE HIGH)
■
Outputs are disabled (OE HIGH)
■
Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■
When a write operation is active (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW then data
from IO pins (IO0 through IO7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 9 for a
complete description of read and write modes.
Functional Description
The CY62147EV18 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SENSE AMPS
DATA IN DRIVERS
256K x 16
RAM Array
IO0–IO7
IO8–IO15
COLUMN DECODER
Cypress Semiconductor Corporation
Document #: 38-05441 Rev. *F
•
A17
A15
198 Champion Court
A16
A13
A14
BLE
A11
BHE
A12
CE
POWER DOWN
CIRCUIT
•
BHE
WE
CE
OE
BLE
San Jose, CA 95134-1709
•
408-943-2600
Revised August 01, 2007
[+] Feedback
CY62147EV18 MoBL2™
Product Portfolio
Power Dissipation
Product
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1MHz
CY62147EV18LL
Min
Typ [1]
Max
1.65
1.8
2.25
Standby ISB2 (µA)
f = fmax
Typ [1]
Max
Typ [1]
Max
Typ [1]
Max
2
2.5
15
20
1
7
55
Pin Configuration
Figure 1. 48-Ball VFBGA Pinout [2, 3]
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
IO8
BHE
A3
A4
CE
IO0
B
IO9
IO10
A5
A6
IO1
IO2
C
VSS
IO11
A17
A7
IO3
VCC
D
VCC
IO12
NC
A16
IO4
VSS
E
IO14
IO13
A14
A15
IO5
IO6
F
IO15
NC
A12
A13
WE
IO7
G
NC
A8
A9
A10
A11
NC
H
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
2. NC pins are not connected on the die.
3. Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb and 32 Mb, respectively.
Document #: 38-05441 Rev. *F
Page 2 of 12
[+] Feedback
CY62147EV18 MoBL2™
Maximum Ratings
DC Input Voltage[4, 5] ........... –0.2V to 2.45V (VCCmax + 0.2V)
Exceeding the maximum ratings may shorten the battery life of
the device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Output Current into Outputs (LOW) ............................ 20 mA
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Latch up Current .................................................... > 200 mA
Supply Voltage to Ground
Potential ........................... –0.2V to + 2.45V (VCCmax + 0.2V)
Operating Range
Static Discharge Voltage ......................................... > 2001V
(MIL-STD-883, Method 3015)
Device
DC Voltage Applied to Outputs
in High Z State[4, 5] ............... –0.2V to 2.45V (VCCmax + 0.2V)
Range
Ambient
Temperature
VCC[6]
CY62147EV18LL Industrial –40°C to +85°C 1.65V to 2.25V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
IOH = –0.1 mA
VOL
Output LOW Voltage
IOL = 0.1 mA
VIH
Input HIGH Voltage
VCC =1.65V to 2.25V
VIL
Input LOW Voltage
VCC =1.65V to 2.25V
IIX
Input Leakage Current
IOZ
ICC
55 ns
Min
Typ[1]
Unit
Max
1.4
V
0.2
V
1.4
VCC+ 0.2
V
–0.2
0.4
V
GND < VI < VCC
–1
+1
µA
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
+1
µA
VCC Operating Supply
Current
f = fmax = 1/tRC
VCC(max)=2.25V
IOUT = 0 mA
CMOS levels
15
20
mA
f = 1 MHz
VCC(max)=2.25V
2
2.5
mA
ISB1
Automatic CE Power Down CE > VCC – 0.2V,
VCC(max)=2.25V
Current–CMOS Inputs
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, WE, BHE, and BLE)
1
7
µA
ISB2[7]
Automatic CE Power Down CE > VCC – 0.2V,
Current–CMOS Inputs
VIN > VCC – 0.2V or VIN < 0.2V,
f=0
VCC(max)=2.25V
1
7
µA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max)=VCC+0.5V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 38-05441 Rev. *F
Page 3 of 12
[+] Feedback
CY62147EV18 MoBL2™
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
VFBGA
Package
Unit
75
°C/W
10
°C/W
Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
VCC
OUTPUT
VCC
30 pF
10%
GND
Rise Time = 1 V/ns
R2
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
1.80V
Unit
R1
13500
Ω
R2
10800
Ω
RTH
6000
Ω
VTH
0.80
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR[7]
Data Retention Current
tCDR[8]
Chip Deselect to Data Retention Time
tR
[9]
Min
Typ[1]
Max
1.0
VCC= 1.0V, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Operation Recovery Time
Unit
V
0.5
5
µA
0
ns
tRC
ns
Data Retention Waveform
Figure 3. Data Retention Waveform[10]
DATA RETENTION MODE
VCC
CE or
VCC(min)
tCDR
VDR > 1.0V
VCC(min)
tR
BHE.BLE
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document #: 38-05441 Rev. *F
Page 4 of 12
[+] Feedback
CY62147EV18 MoBL2™
Switching Characteristics
Over the Operating Range [11, 12]
Parameter
Description
55 ns
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
ns
tDOE
OE LOW to Data Valid
25
ns
tLZOE
OE LOW to Low
55
55
Z[13]
10
tLZCE
CE LOW to Low
Z[13]
ns
18
OE HIGH to High Z
10
Z[13, 14]
ns
ns
5
[13, 14]
tHZOE
ns
ns
ns
tHZCE
CE HIGH to High
tPU
CE LOW to Power Up
tPD
CE HIGH to Power Down
55
ns
tDBE
BLE/BHE LOW to Data Valid
55
ns
tLZBE
BLE/BHE LOW to Low
tHZBE
Write
18
0
Z[13]
BLE/BHE HIGH to High
ns
10
Z[13, 14]
ns
ns
18
ns
Cycle[15]
tWC
Write Cycle Time
45
ns
tSCE
CE LOW to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tBW
BLE/BHE LOW to Write End
35
ns
tSD
Data Setup to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
tLZWE
WE LOW to High
Z[13, 14]
WE HIGH to Low
Z[13]
18
10
ns
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels
of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4 section.
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedence state
15. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05441 Rev. *F
Page 5 of 12
[+] Feedback
CY62147EV18 MoBL2™
Switching Waveforms
Figure 4 shows the Read Cycle No.1 that is address transition controlled. [16, 17]
Figure 4. Read Cycle No. 1
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5 shows the Read Cycle No.2 that is OE controlled. [17, 18]
Figure 5. Read Cycle No. 2
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGHIMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes:
16. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL.
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 38-05441 Rev. *F
Page 6 of 12
[+] Feedback
CY62147EV18 MoBL2™
Switching Waveforms (continued)
Figure 6 shows the Write Cycle No.1 that is WE Controlled. [15, 19, 20]
Figure 6. Write Cycle No. 1
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA IO
tSD
NOTE 21
tHD
DATAIN
tHZOE
Figure 7 shows the Write Cycle No.2 that is CE Controlled. [15, 19, 20]
Figure 7. Write Cycle No. 2
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA IO
tHD
DATAIN
NOTE 21
tHZOE
Notes:
19. Data IO is high impedance if OE = VIH.
20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
21. During this period, the IOs are in output state. Do not apply input signals.
Document #: 38-05441 Rev. *F
Page 7 of 12
[+] Feedback
CY62147EV18 MoBL2™
Switching Waveforms (continued)
Figure 8 shows the Write Cycle No. 3 that is WE Controlled and OE LOW. [20]
Figure 8. Write Cycle No. 3
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
WE
tPWE
tSD
DATA IO
NOTE 21
tHD
DATAIN
tLZWE
tHZWE
Figure 9 shows Write Cycle No. 4 that is BHE/BLE Controlled and OE LOW. [20]
Figure 9. Write Cycle No. 4
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA IO
NOTE 21
tSD
tHD
DATAIN
tLZWE
Document #: 38-05441 Rev. *F
Page 8 of 12
[+] Feedback
CY62147EV18 MoBL2™
Truth Table
CE
WE
OE
BHE BLE
Inputs or Outputs
Mode
Power
H
X
X
X
X
High Z
Deselect or Power Down
Standby (ISB)
L
X
X
H
H
High Z
Deselect or Power Down
Standby (ISB)
L
H
L
L
L
Data Out (IO0–IO15)
Read
Active (ICC)
L
H
L
H
L
Data Out (IO0–IO7);
IO8–IO15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (IO8–IO15);
IO0–IO7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
L
X
L
L
Data In (IO0–IO15)
Write
Active (ICC)
L
L
X
H
L
Data In (IO0–IO7);
IO8–IO15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (IO8–IO15);
IO0–IO7 in High-Z
Write
Active (ICC)
Ordering Information
Speed
(ns)
55
Ordering Code
CY62147EV18LL-55BVXI
Package
Diagram
Package Type
51-85150 48-Ball VFBGA (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of other parts.
Document #: 38-05441 Rev. *F
Page 9 of 12
[+] Feedback
CY62147EV18 MoBL2™
Package Diagram
Figure 10. 48-Ball VFBGA (6 x 8 x 1 mm), 51- 85150
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.15(4X)
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
Document #: 38-05441 Rev. *F
1.00 MAX
0.26 MAX.
SEATING PLANE
C
51-85150-*D
Page 10 of 12
[+] Feedback
CY62147EV18 MoBL2™
Document History Page
Document Title: CY62147EV18 MoBL2™ 4-Mbit (256K x 16) Static RAM
Document Number: 38-05441
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
201580
01/08/04
AJU
New Datasheet
*A
247009
See ECN
SYT
Changed from Advance Information to Preliminary
Moved Product Portfolio to Page 2
Changed VCCMax from 2.20 to 2.25 V
Changed VCC stabilization time in footnote #8 from 100 µs to 200 µs
Removed Footnote #15 (tLZBE) from Previous Revision
Changed ICCDR from 2.0 µA to 2.5 µA
Changed typo in Data Retention Characteristics (tR) from 100 µs to tRC ns
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for
45 ns Speed Bin
Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns
Speed Bin
Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin
Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
45 ns Speed Bin
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed Ordering Information to include Pb-Free Packages
*B
414820
See ECN
ZSD
Changed from Preliminary to Final
Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901
North First Street” to “198 Champion Court”
Removed 35 ns Speed Bin
Removed “L” version of CY62147EV18
Changed ball E3 from DNU to NC
Changed ICC(typ) value from 1.5 mA to 2 mA at f = 1 MHz
Changed ICC(max) value from 2 mA to 2.5 mA at f = 1 MHz
Changed ICC(typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ values from 0.7 µA to 1 µA and Max values from 2.5 µA to
7 µA
Extended undershoot limit to –2V in footnote #5
Changed ICCDR Max from 2.5 µA to 3 µA
Added ICCDR typical value
Changed tLZOE from 3 ns to 5 ns
Changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns
Changed tHZCE from 22 ns to 18 ns
Changed tPWE from 30 ns to 35 ns
Changed tSD from 22 ns to 25 ns
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering information table and replaced Package Name Column with
Package Diagram
*C
571786
See ECN
VKN
Replaced 45ns speed bin with 55 ns
*D
908120
See ECN
VKN
Added footnote #8 related to ISB2 and ICCDR
Added footnote #13 related AC timing parameters
Changed tWC specification from 45 ns to 55 ns
Changed tSCE, tAW, tPWE, tBW spec from 35 ns to 40 ns
Changed tHZWE specification from 18 ns to 20 ns
Document #: 38-05441 Rev. *F
Page 11 of 12
[+] Feedback
CY62147EV18 MoBL2™
Document Title: CY62147EV18 MoBL2™ 4-Mbit (256K x 16) Static RAM
Document Number: 38-05441
REV.
ECN NO.
Issue
Date
Orig. of
Change
VKN
Description of Change
Changed ICCDR specification from 3 µA to 5 µA
*E
1045701 See ECN
*F
1274728 See ECN VKN/AESA Changed tWC specification from 55 ns to 45 ns
Changed tSCE, tAW, tPWE, tBW specification from 40 ns to 35 ns
Changed tHZWE specification from 20 ns to 18 ns
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05441 Rev. *F
Revised August 01, 2007
Page 12 of 12
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective
holders.
[+] Feedback
Similar pages