CYPRESS CY7C199N_10

CY7C199N
32 K × 8 Static RAM
Features
■
Functional Description
High speed
The CY7C199N is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199NN is in
the standard 300-mil-wide DIP, SOJ, and LCC packages.
— 15 ns
■
Fast tDOE
■
CMOS for optimum speed/power
■
Low active power
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
— 550 mW (max, 15 ns “L” version)
■
Low standby power
— 0.275 mW (max, “L” version)
■
2V data retention (“L” version only)
■
Easy memory expansion with CE and OE features
■
TTL-compatible inputs and outputs
■
Automatic power-down when deselected
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Logic Block Diagram
I/O0
INPUT BUFFER
I/O1
ROW DECODER
I/O2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1024 x 32 x 8
ARRAY
I/O3
I/O4
I/O5
CE
WE
I/O6
POWER
DOWN
COLUMN
DECODER
I/O7
Cypress Semiconductor Corporation
Document #: 001-06493 Rev. *B
•
A 14
A 12
A 13
A 11
A 10
OE
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 13, 2010
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CY7C199N
Pin Configurations
OE
A1
A2
A3
A4
WE
V CC
A5
A6
A7
A8
A9
A 10
A 11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TSOP I
Top View
(not to scale)
A0
CE
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
GND
I/O 2
I/O 1
I/O 0
A 14
A 13
A 12
Selection Guide
Description
-15
Maximum Access Time
Unit
15
ns
Maximum Operating Current
L
100
mA
Maximum CMOS Standby Current
L
0.05
mA
Document #: 001-06493 Rev. *B
Page 2 of 11
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CY7C199N
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65C to +150C
Ambient Temperature with
Power Applied ............................................ –55C to +125C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)............................................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[1] .................................... –0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Ambient Temperature[2]
VCC
0C to +70C
5V  10%
Electrical Characteristics Over the Operating Range
Parameter
Description
-15
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VCC = Min., IOL = 8.0 mA
Min.
Max.
2.4
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Load Current
GND < VI < VCC
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply Current VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-down Current— TTL
Inputs
ISB2
Max. VCC,
Automatic CE
Power-down Current— CMOS CE > VCC – 0.3V
Inputs
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
L
Max. VCC, CE > VIH, VIN > VIH L
or VIN < VIL, f = fMAX
L
Unit
V
0.4
V
2.2
VCC + 0.3V
V
–0.5
0.8
V
–5
+5
A
–5
+5
A
100
mA
5
mA
0.05
mA
Notes
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
Document #: 001-06493 Rev. *B
Page 3 of 11
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CY7C199N
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
TA = 25C, f = 1 MHz,
VCC = 5.0V
Unit
8
pF
8
pF
AC Test Loads and Waveforms[4]
R1 481
5V
R1 481
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
255 
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
3.0V
INCLUDING
JIG AND
SCOPE
(a)
R2
255
5 pF
GND
10%
90%
10%
90%
tr
tr
(b)
THÉVENIN EQUIVALENT
167 
OUTPUT
1.73V
Data Retention Characteristics Over the Operating Range (L-version only)
Parameter
VDR
Conditions[5]
VCC for Data Retention
ICCDR
tCDR[3]
tR
Description
[4]
Min.
Max.
Unit
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
Data Retention Current
L
VIN > VCC – 0.3V or
Chip Deselect to Data Retention Time VIN < 0.3V
2.0
V
0
ns
Operation Recovery Time
200
s
10
A
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
VDR > 2V
tCDR
3.0V
tR
CE
Note
3. Tested initially and after any design or process changes that may affect these parameters.
4. tR< 3 ns for -15 speed.
5. No input may exceed VCC + 0.5V.
Document #: 001-06493 Rev. *B
Page 4 of 11
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CY7C199N
Switching Characteristics Over the Operating Range
Parameter
Description
[6]
7C199-15
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
15
ns
tDOE
OE LOW to Data Valid
7
ns
tLZOE
OE LOW to
15
Low-Z[7]
3
[7]
CE LOW to Low-Z
tHZCE
CE HIGH to High-Z[7,8]
tPU
CE LOW to Power-up
tPD
ns
7
3
ns
ns
7
0
CE HIGH to Power-down
ns
ns
0
OE HIGH to High-Z
tLZCE
Write
15
[7, 8]
tHZOE
ns
ns
ns
15
ns
Cycle[9, 10]
tWC
Write Cycle Time
15
ns
tSCE
CE LOW to Write End
10
ns
tAW
Address Set-up to Write End
10
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
9
ns
tSD
Data Set-up to Write End
9
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[8]
tLZWE
Low-Z[7]
WE HIGH to
ns
7
3
ns
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less for -15 speed, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of
the specified IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06493 Rev. *B
Page 5 of 11
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CY7C199N
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [12, 13]
tRC
CE
tACE
OE
DATA OUT
tDOE
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZOE
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
ICC
50%
50%
ISB
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06493 Rev. *B
Page 6 of 11
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CY7C199N
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[9, 14, 15]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
tHD
DATAIN VALID
DATA I/O
tHZOE
Write Cycle No. 2 (CE Controlled)[8, 14, 15]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATA IN VALID
Write Cycle No. 3 (WE Controlled OE LOW)[10, 15]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
tHD
DATAIN VALID
tHZWE
tLZWE
Notes:
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 001-06493 Rev. *B
Page 7 of 11
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CY7C199N
NORMALIZED ICC, ISB
1.2
ICC
0.8
0.6
VIN = 5.0V
TA = 25°C
0.4
0.2
0.0
4.0
1.0
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
0.2
ISB
4.5
5.0
5.5
ISB
0.0
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
TA = 25°C
1.0
1.2
1.0
VCC = 5.0V
0.8
0.9
0.8
4.0
4.5
5.0
5.5
0.6
–55
6.0
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
100
80
VCC = 5.0V
60
TA = 25°C
40
20
0
0.0
25
2.5
25.0
DELTA t AA (ns)
30.0
2.0
1.5
1.0
0.5
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
140
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
VCC = 5.0V
TA = 25°C
40
20
0
0.0
125
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
0.0
0.0
120
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
NORMALIZED IPO
125
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE (C)
SUPPLY VOLTAGE (V)
1.1
25
OUTPUT SINK CURRENT (mA)
1.0
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.4
ICC
1.2
NORMALIZED ICC vs. CYCLE TIME
1.25
20.0
15.0
VCC = 4.5V
TA = 25°C
10.0
NORMALIZED ICC
NORMALIZED ICC, ISB
1.4
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
1.00
VCC = 5.0V
TA = 25°C
VIN = 0.5V
0.75
5.0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 001-06493 Rev. *B
5.0
0.0
0
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 8 of 11
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CY7C199N
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High Z
Deselect/Power-down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Output disabled
Active (ICC)
Ordering Information
Speed
(ns)
15
Package
Diagram
51-85071
Ordering Code
CY7C199NL-15ZXC
Package Type
28-lead TSOP 1 (Pb-free)
Operating
Range
Commercial
Ordering Code Definitions
CY 7 C 1 99 NL - 15
ZX C
Temperature Range:
C = Commercial
Package Type:
ZX = 28-lead TSOP 1 (Pb-free)
Speed: 15 ns
NL = low power
99 = 256 K bit density with datawidth × 8 bits
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Contact your Local Cypress sales representative for availability of these parts
Document #: 001-06493 Rev. *B
Page 9 of 11
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CY7C199N
Package Diagrams
Figure 1. 28-pin TSOP 1 (8 x 13.4 mm), 51-85071
51-85071 *H
Document #: 001-06493 Rev. *B
Page 10 of 11
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CY7C199N
Document History Page
Document Title: CY7C199N 32 K × 8 Static RAM
Document Number: 001-06493
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
423877
See ECN
NXR
New Data Sheet
*A
2892510
03/18/2010
VKN
Removed speed bins from the data sheet: 12ns, 20ns, 25ns, 35ns, and 55ns.
Removed Industrial and Military product information
Removed 28-pin (300-Mil) PDIP package
Updated Ordering Information table
Updated Package Diagram
*B
3109199
12/13/2010
AJU
Added Ordering Code Definitions.
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© Cypress Semiconductor Corporation, 2006-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-06493 Rev. *B
Revised December 13, 2010
Page 11 of 11
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