Revised March 2005
74AC374 • 74ACT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
The AC/ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to
all flip-flops.
■ ICC and IOZ reduced by 50%
■ Buffered positive edge-triggered clock
■ 3-STATE outputs for bus-oriented applications
■ Outputs source/sink 24 mA
■ See 273 for reset version
■ See 377 for clock enable version
■ See 373 for transparent latch version
■ See 574 for broadside pinout version
■ See 564 for broadside pinout version with inverted
outputs
■ ACT374 has TTL-compatible inputs
Ordering Code:
Order Number
Package
Package Description
Number
74AC374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC374SCX_NL
(Note 1)
M20B
Pb-Free 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC374SJ
74AC374MTC
M20D
MTC20
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC374PC
N20A
74ACT374SC
M20B
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT374SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT374MSA
MSA20
74ACT374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT374MTCX_NL
(Note 1)
MTC20
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT374PC
N20A
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009959
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74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
November 1988
74AC374 • 74ACT374
Connection Diagram
Pin Descriptions
Pin Names
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Outputs
Truth Table
Inputs
Logic Symbols
Dn
H
L
X
CP
Outputs
OE
On
L
H
L
L
X
H
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
LOW-to-HIGH Transition
IEEE/IEC
Functional Description
The AC/ACT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
DC Input Voltage (VI)
Supply Voltage (VCC)
20 mA
20 mA
0.5V to VCC 0.5V
DC Output Diode Current (IOK)
VO
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
20 mA
20 mA
0.5V to VCC 0.5V
per Output Pin (ICC or IGND)
0V to VCC
Output Voltage (VO)
0V to VCC
40qC to 85qC
AC Devices
VIN from 30% to 70% of VCC
r 50 mA
VCC @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate ('V/'t)
r 50 mA
65qC to 150qC
ACT Devices
VIN from 0.8V to 2.0V
Junction Temperature (TJ)
VCC @ 4.5V, 5.5V
140qC
(PDIP)
4.5V to 5.5V
Input Voltage (VI)
Operating Temperature (TA)
DC VCC or Ground Current
Storage Temperature (TSTG)
2.0V to 6.0V
ACT
Minimum Input Edge Rate ('V/'t)
DC Output Source
or Sink Current (IO)
AC
125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
VOL
Parameter
VCC
TA
25qC
TA
40qC to 85qC
(V)
Typ
Guaranteed Limits
Minimum HIGH Level
3.0
1.5
2.1
2.1
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
Units
Conditions
VOUT
or VCC 0.1V
V
or VCC 0.1V
V
IOUT
50 PA
VOUT
V
VIN
VIL or VIH
12 mA
IOH
24 mA
IOH
24 mA (Note 3)
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r0.1
r1.0
PA
VI
5.5
r0.25
r2.5
PA
VI
Maximum Input Leakage Current
IOZ
Maximum 3-STATE Current
V
V
0.1V
IOH
Maximum LOW Level
IIN (Note 5)
0.1V
V
50 PA
IOUT
VIN
VIL or VIH
IOL
12 mA
IOL
24 mA
IOL
24 mA (Note 3)
VCC, GND
VI (OE)
VO
VCC, GND
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 4)
5.5
75
mA
VOHD
ICC (Note 5) Maximum Quiescent Supply Current
5.5
40.0
PA
VIN
4.0
VIL, VIH
VCC, GND
1.65V Max
3.85V Min
VCC or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
3
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74AC374 • 74ACT374
Absolute Maximum Ratings(Note 2)
74AC374 • 74ACT374
DC Electrical Characteristics for ACT
Symbol
VIH
VIL
VOH
Parameter
VCC
TA
25qC
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
3.86
3.76
5.5
IIN
40qC to 85qC
Typ
4.5
VOL
TA
(V)
Units
V
V
V
V
Conditions
VOUT
0.1V
or VCC 0.1V
VOUT
0.1V
or VCC 0.1V
50 PA
IOUT
VIN
VIL or VIH
IOH
24 mA
IOH 24 mA (Note 6)
4.86
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r0.1
r1.0
PA
VI
VCC, GND
5.5
r0.25
r2.5
PA
VI
VIL, VIH
Maximum Input
V
V
50 PA
IOUT
VIN
VIL or VIH
IOL
24 mA
IOL
24 mA (Note 6)
Leakage Current
Maximum
IOZ
3-STATE Current
ICCT
Maximum
5.5
0.6
1.5
mA
VO
VCC, GND
VI
VCC 2.1V
ICC/Input
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 7)
5.5
75
mA
VOHD
ICC
Maximum Quiescent
5.5
40.0
PA
VIN
4.0
Supply Current
1.65V Max
3.85V Min
VCC
or GND
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 8)
fMAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Min
Typ
40qC to 85q
TA
CCL
Max
Min
50 pF
Maximum Clock
3.3
60
110
60
Frequency
5.0
100
155
100
Propagation Delay
3.3
3.0
11.0
13.5
1.5
15.5
CP to On
5.0
2.5
8.0
9.5
1.5
10.5
Propagation Delay
3.3
2.5
10.0
12.5
2.0
14.0
CP to On
5.0
2.0
7.0
9.0
1.5
10.0
Output Enable Time
3.3
3.0
9.5
11.5
1.5
13.0
5.0
2.0
7.0
8.5
1.0
9.5
3.3
2.5
9.0
11.5
1.5
13.0
5.0
2.0
6.5
8.5
1.0
9.5
3.3
3.0
10.5
12.5
2.0
14.5
5.0
2.0
8.0
11.0
2.0
12.5
3.3
2.0
8.0
11.5
1.0
12.5
5.0
1.5
6.5
8.5
1.0
10.0
Output Enable Time
Output Disable Time
Output Disable Time
Note 8: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
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4
Units
Max
MHz
ns
ns
ns
ns
ns
ns
Symbol
tS
tH
tW
VCC
TA
25qC
(V)
CL
50 pF
Parameter
40qC to 85qC
TA
CL
50 pF
(Note 9)
Typ
Setup Time, HIGH or LOW
3.3
2.0
5.5
6.0
Dn to CP
5.0
1.0
4.0
4.5
Units
Guaranteed Minimum
Hold Time, HIGH or LOW
3.3
1.0
1.0
1.0
Dn to CP
5.0
0
1.5
1.5
CP Pulse Width,
3.3
4.0
5.5
6.0
HIGH or LOW
5.0
2.5
4.0
4.5
ns
ns
ns
Note 9: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
AC Electrical Characteristics
Symbol
fMAX
Parameter
Maximum Clock
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
Max
50 pF
Min
Units
(Note 10)
Min
Typ
Max
5.0
100
160
5.0
2.0
8.5
10.0
2.0
11.5
ns
5.0
2.0
8.0
9.5
1.5
11.0
ns
90
MHz
Frequency
tPLH
Propagation Delay
CP to On
tPHL
Propagation Delay
CP to On
tPZH
Output Enable Time
5.0
2.0
8.0
9.5
1.5
10.5
ns
tPZL
Output Enable Time
5.0
1.5
8.0
9.0
1.5
10.5
ns
tPHZ
Output Disable Time
5.0
1.5
8.5
11.5
1.0
12.5
ns
tPLZ
Output Disable Time
5.0
1.5
7.0
8.5
1.0
10.0
ns
Note 10: Voltage Range 5.0 is 5.0V r 0.5V
AC Operating Requirements
Symbol
tS
Parameter
Setup Time, HIGH or LOW
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
50 pF
Units
(Note 11)
Typ
Guaranteed Minimum
5.0
1.0
5.5
5.5
ns
5.0
0
1.5
1.5
ns
5.0
2.5
5.0
5.0
ns
Dn to CP
Hold Time, HIGH or LOW
tH
Dn to CP
tW
CP Pulse Width,
HIGH or LOW
Note 11: Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Symbol
CIN
Parameter
Input Capacitance
Typ
Units
4.5
pF
5
Conditions
VCC OPEN
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74AC374 • 74ACT374
AC Operating Requirements
74AC374 • 74ACT374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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74AC374 • 74ACT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
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74AC374 • 74ACT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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74AC374 • 74ACT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
9
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74AC374 • 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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