Cypress CY7C199BL-15PC 32k x 8 static ram Datasheet

CY7C199B
PRELIMINARY
32K x 8 Static RAM
Features
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199B is in
the standard 300-mil-wide DIP, SOJ, and LCC packages.
• High speed
— 10 ns
• Fast tDOE
• CMOS for optimum speed/power
• Low active power
— 495 mW (max, 10 ns “L” version)
• Low standby power
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O7) is written into the memory location addressed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
Functional Description
The CY7C199B is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configurations
DIP / SOJ / SOIC
Top View
I/O0
INPUT BUFFER
I/O1
ROW DECODER
I/O2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1024 x 32 x 8
ARRAY
I/O6
I/O7
C199B–1
A 14
A 12
A 13
A 11
A 10
OE
A7
A6
A5
VCC
WE
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3 2 1 28 27
4
26 A4
5
25 A3
6
24 A2
7
23 A1
8
22 OE
9
21 A0
10
20 CE
11
19 I/O7
12
18 I/O6
1314151617
C199–3
C199B–2
OE
A1
A2
A3
A4
WE
V CC
A5
A6
A7
A8
A9
A 10
A 11
I/O4
POWER
DOWN
COLUMN
DECODER
VCC
WE
A4
A3
A2
A1
I/O3
I/O5
CE
WE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
I/O2
GND
I/O3
I/O4
I/O5
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
LCC
Top View
22
23
21
24
25
26
27
28
1
2
3
4
5
6
7
20
19
18
17
16
15
14
13
12
11
10
9
8
TSOP I
Top View
(not to scale)
A0
CE
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
GND
I/O 2
I/O 1
I/O 0
A 14
A 13
A 12
C199–4
Selection Guide
199B-8
199B-10
199B-12
199B-15
199B-20
199B-25
199B-35
199B-45
Maximum Access Time (ns)
Maximum Operating
Current (mA)
L
8
120
0.5
12
160
90
10
0.05
15
155
90
10
0.05
20
150
90
10
0.05
25
150
80
10
0.05
35
140
70
10
0.05
45
140
Maximum CMOS
Standby Current (mA)
10
110
90
0.5
0.05
L
10
Shaded area contains advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 13, 2000
PRELIMINARY
CY7C199B
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Voltage Applied to Outputs
in High Z State[1] ................................... –0.5V to VCC + 0.5V
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Storage Temperature ................................. –65°C to +150°C
Output Current into Outputs (LOW)............................. 20 mA
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
Latch-Up Current .................................................... >200 mA
Maximum Ratings
Operating Range
Range
Commercial
Industrial
Military
Ambient Temperature[2]
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
–55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[3]
7C199B-8
Parameter
Description
Test Conditions
Min.
Max.
7C199B-10
Min.
Max.
7C199B-12
Min.
Max.
VOH
Output HIGH
Voltage
VCC = Min., IOH=–4.0 mA
VOL
Output LOW
Voltage
VCC = Min., IOL=8.0 mA
VIH
Input HIGH
Voltage
2.2
VCC
+0.3V
2.2
VCC
+0.3V
2.2
VCC
+0.3V
VIL
Input LOW
Voltage
–0.5
0.8
–0.5
0.8
–0.5
IIX
Input Load
Current
GND < VI < VCC
–5
+5
–5
+5
IOZ
Output Leakage
Current
GND < VO < V CC,
Output Disabled
–5
+5
–5
+5
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Automatic CE
Power-Down
Current— TTL
Inputs
Max. V CC,
Com’l
CE > VIH,
L
V IN > VIH or
V IN < VIL, f = fMAX
5
Automatic CE
Power-Down
Current— CMOS
Inputs
Max. V CC,
Com’l
CE > VCC – 0.3V L
V IN > VCC – 0.3V
or V IN < 0.3V, f = 0 Mil
ISB1
ISB2
2.4
2.4
0.4
Com’l
120
2.4
0.4
Max.
2.4
0.4
Unit
V
0.4
V
2.2
VCC
+0.3V
V
0.8
–0.5
0.8
V
–5
+5
–5
+5
µA
–5
+5
–5
+5
µA
110
160
155
mA
85
85
100
mA
180
mA
5
30
30
mA
5
5
5
mA
0.5
0.5
10
10
mA
0.05
0.05
0.05
0.05
mA
15
mA
L
Mil
Shaded area contains advance information.
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
3. See the last page of this specification for Group A subgroup testing information.
2
7C199B-15
Min.
PRELIMINARY
CY7C199B
Electrical Characteristics Over the Operating Range[3] (continued)
Parameter
Description
7C199B-20
7C199B-25
7C199B-35
7C199B-45
Test Conditions
Min.
Min.
Min.
Min.
2.4
Max.
Max.
Max.
VOH
Output HIGH
Voltage
VCC = Min., IOH=–4.0 mA
VOL
Output LOW
Voltage
VCC = Min., IOL=8.0 mA
VIH
Input HIGH
Voltage
2.2
VCC
+0.3V
2.2
VCC
+0.3V
2.2
VCC
+0.3V
VIL
Input LOW
Voltage
–0.5
0.8
-0.5
0.8
-0.5
IIX
Input Load
Current
GND < VI < VCC
–5
+5
–5
+5
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
–5
+5
–5
+5
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
ISB1
ISB2
2.4
2.4
0.4
0.4
Max.
2.4
0.4
V
0.4
V
2.2
VCC
+0.3V
V
0.8
-0.5
0.8
V
–5
+5
–5
+5
µA
–5
+5
–5
+5
µA
Com’l
150
150
140
140
mA
L
90
80
70
70
mA
Mil
170
150
150
150
mA
Automatic CE
Power-Down
Current—
TTL Inputs
Max. VCC, CE > VIH, Com’l
VIN > VIH
L
or VIN < VIL, f = fMAX
30
30
25
25
mA
5
5
5
5
mA
Automatic CE
Power-Down
Current—
CMOS Inputs
Max. V CC,
Com’l
CE > VCC – 0.3V
L
VIN > VCC – 0.3V or
VIN < 0.3V, f=0
Mil
10
10
10
10
mA
0.05
0.05
0.05
0.05
µA
15
15
15
15
mA
]
Capacitance[4]
Parameter
CIN
COUT
Unit
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
Max.
8
8
Unit
pF
pF
PRELIMINARY
CY7C199B
AC Test Loads and Waveforms
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
3.0V
R2
255 Ω
30 pF
(a)
Equivalent to:
R2
255Ω
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
GND
≤tr
≤tr
C199B–5
C199B–6
(b)
THÉVENIN EQUIVALENT
167 Ω
OUTPUT
1.73V
Data Retention Characteristics Over the Operating Range (L version only)
Parameter
Conditions[5]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Min.
Max.
2.0
tCDR[4]
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
Com’l L
VIN > VCC – 0.3V or
Chip Deselect to Data Retention Time VIN < 0.3V
tR
Operation Recovery Time
Unit
V
µA
Com’l
10
µA
0
ns
200
µs
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
VDR > 2V
3.0V
tR
tCDR
CE
C199B–7
Note:
5. No input may exceed VCC + 0.5V.
4
PRELIMINARY
CY7C199B
Switching Characteristics Over the Operating Range[3, 6]
7C199B-8
Parameter
Description
Min.
Max.
7C199B-10
Min.
Max.
7C199B-12
Min.
Max.
7C199B-15
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
8
10
8
10
12
15
CE LOW to Data Valid
8
10
12
15
ns
tDOE
OE LOW to Data Valid
4.5
5
5
7
ns
0
[7, 8]
tHZOE
OE HIGH to High Z
tLZCE
CE LOW to Low Z[7]
tHZCE
CE HIGH to High Z[7,8]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
0
5
3
0
5
3
4
0
0
5
ns
7
3
5
0
10
ns
0
3
5
8
3
ns
Data Hold from Address Change
OE LOW to Low Z
3
ns
tOHA
tLZOE
3
15
tACE
[7]
3
12
7
0
12
ns
ns
ns
ns
15
ns
WRITE CYCLE[9, 10]
tWC
Write Cycle Time
8
10
12
15
ns
tSCE
CE LOW to Write End
7
7
9
10
ns
tAW
Address Set-Up to Write End
7
7
9
10
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
7
7
8
9
ns
tSD
Data Set-Up to Write End
5
5
8
9
ns
tHD
Data Hold from Write End
0
0
0
0
ns
tHZWE
tLZWE
[8]
WE LOW to High Z
[7]
WE HIGH to Low Z
5
3
6
3
7
3
7
3
ns
ns
Shaded area contains advance information.
Notes:
6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
5
PRELIMINARY
CY7C199B
Switching Characteristics Over the Operating Range[3,6] (continued)
7C199B-20
Parameter
Description
Min.
Max.
7C199B-25
Min.
Max.
7C199B-35
Min.
Max.
7C199B-45
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address
Change
tACE
CE LOW to Data Valid
20
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z[7]
tHZOE
OE HIGH to High Z[7, 8]
tLZCE
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
WRITE CYCLE
3
20
9
3
3
3
9
3
0
20
16
0
15
15
15
20
ns
ns
ns
15
0
20
ns
ns
3
0
ns
ns
45
16
11
0
3
0
11
ns
45
35
10
0
9
45
35
25
0
CE HIGH to Power-Down
35
25
3
[7, 8]
tHZCE
tPD
20
[7]
tPU
25
ns
ns
25
ns
[9,10]
tWC
Write Cycle Time
20
25
35
45
ns
tSCE
CE LOW to Write End
15
18
22
22
ns
tAW
Address Set-Up to Write End
15
20
30
40
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
15
18
22
22
ns
tSD
Data Set-Up to Write End
10
10
15
15
ns
tHD
Data Hold from Write End
0
0
0
0
ns
[8]
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z[7]
10
11
3
3
15
3
15
3
ns
ns
Switching Waveforms
Read Cycle No. 1[11, 12]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
C199B–8
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
6
PRELIMINARY
CY7C199B
Switching Waveforms (continued)
Read Cycle No. 2 [12, 13]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
C199B–9
Write Cycle No. 1 (WE Controlled)[9, 14, 15]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tPWE
OE
tSD
tHD
DATA IN VALID
DATA I/O
tHZOE
C199B–10
Write Cycle No. 2 (CE Controlled)[9, 14, 15]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATA IN VALID
C199B–11
Notes:
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
7
PRELIMINARY
CY7C199B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled OE LOW)[10, 15]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tSD
DATA I/O
tHD
DATA IN VALID
tLZWE
tHZWE
C199B–12
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
NORMALIZED ICC,I SB
1.2
ICC
1.0
0.8
0.6
VIN =5.0V
TA =25°C
0.4
0.2
1.2
1.0
0.8
0.6
VCC =5.0V
VIN =5.0V
0.4
0.2
ISB
0.0
4.0
ICC
4.5
5.0
5.5
ISB
0.0
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.6
1.4
1.3
NORMALIZED t AA
NORMALIZED t AA
125
1.2
1.1
TA =25°C
1.0
1.4
1.2
1.0
VCC =5.0V
0.8
0.9
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
VCC =5.0V
TA =25°C
60
40
20
0
0.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.8
4.0
25
6.0
0.6
–55
25
125
AMBIENT TEMPERATURE (°C)
8
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
NORMALIZED ICC,I SB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60
VCC =5.0V
TA =25°C
40
20
0
0.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
PRELIMINARY
CY7C199B
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
2.0
1.5
1.0
20.0
15.0
VCC =4.5V
TA =25°C
10.0
1.00
VCC =5.0V
TA =25°C
VIN =0.5V
0.75
5.0
0.5
0.0
0.0
NORMALIZED I CC vs. CYCLE TIME
1.25
NORMALIZED I CC
3.0
DELTA t AA (ns)
NORMALIZED I PO
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1.0
2.0
3.0
4.0
5.0
0.0
0
200
SUPPLY VOLTAGE (V)
400
600
800 1000
0.50
10
CAPACITANCE (pF)
20
30
40
CYCLE FREQUENCY (MHz)
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Deselect, Output Disabled
Active (ICC)
Ordering Information
Speed
(ns)
8
10
12
Ordering Code
CY7C199B-8VC
CY7C199B-8ZC
CY7C199BL-8VC
CY7C199BL-8ZC
CY7C199B-10VC
CY7C199B-10ZC
CY7C199BL-10VC
CY7C199BL-10ZC
CY7C199B-10VI
CY7C199B-10ZI
CY7C199BL-10VI
CY7C199BL-10ZI
CY7C199B-12PC
CY7C199B-12VC
CY7C199B-12ZC
CY7C199BL-12PC
CY7C199BL-12VC
CY7C199BL-12ZC
CY7C199B-12VI
CY7C199B-12ZI
CY7C199BL-12VI
CY7C199BL-12ZI
Package
Name
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
V21
Z28
P21
V21
Z28
P21
V21
Z28
V21
Z28
V21
Z28
Package Type
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
Shaded area contains advance information. Contact your Cypress sales representative for availability
9
Operating
Range
Commercial
Commercial
Industrial
Commercial
Industrial
PRELIMINARY
CY7C199B
Ordering Information (continued)
Speed
(ns)
15
20
25
35
45
Ordering Code
CY7C199B-15PC
CY7C199B-15VC
CY7C199B-15ZC
CY7C199BL-15PC
CY7C199BL-15VC
CY7C199BL-15ZC
CY7C199B-15VI
CY7C199B-15ZI
CY7C199B-15DMB
CY7C199B-15LMB
CY7C199BL-15DMB
CY7C199BL-15LMB
CY7C199B-20PC
CY7C199B-20VC
CY7C199B-20ZC
CY7C199BL-20PC
CY7C199BL-20VC
CY7C199BL-20ZC
CY7C199B-20VI
CY7C199B-20ZI
CY7C199B-20DMB
CY7C199B-20LMB
CY7C199BL-20DMB
CY7C199BL-20LMB
CY7C199B-25PC
CY7C199B-25SC
CY7C199B-25VC
CY7C199B-25ZC
CY7C199BL-25ZI
CY7C199B-25DMB
CY7C199B-25LMB
CY7C199B-35PC
CY7C199B-35SC
CY7C199B-35VC
CY7C199B-35ZC
CY7C199B-35DMB
CY7C199B-35LMB
CY7C199B-45DMB
CY7C199B-45LMB
Package
Name
P21
V21
Z28
P21
V21
Z28
V21
Z28
D22
L54
D22
L54
P21
V21
Z28
P21
V21
Z28
V21
Z28
D22
L54
D22
L54
P21
S21
V21
Z28
Z28
D22
L54
P21
S21
V21
Z28
D22
L54
D22
L54
Package Type
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) Molded DIP
28-Lead Molded SOIC
28-Lead Molded SOJ
28-Lead Thin Small Outline Package
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
28-Lead (300-Mil) CerDIP
28-Pin Rectangular Leadless Chip Carrier
Shaded area contains advance information. Contact your Cypress sales representative for availability
10
Operating
Range
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Industrial
Military
Commercial
Military
Military
PRELIMINARY
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter
VOH
VOL
VIH
VIL Max.
IIX
IOZ
ICC
ISB1
ISB2
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Switching Characteristics
Parameter
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
WRITE CYCLE
tWC
tAA
tAW
tHA
tSA
tPWE
tSD
tHD
Document #: 38-00941-**
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
11
CY7C199B
PRELIMINARY
CY7C199B
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032
12
PRELIMINARY
CY7C199B
Package Diagrams (continued)
28-Pin Rectangular Leadless Chip Carrier L54
MIL-STD-1835C-11A
51-80067
28-Lead (300-Mil) Molded DIP P21
51-85014-B
13
PRELIMINARY
CY7C199B
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOIC S21
51-85026-A
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
14
PRELIMINARY
CY7C199B
Package Diagrams (continued)
28-Lead Thin Small Outline Package Z28
51-85071-F
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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