TI1 BQ76925 Host controlled analog front end for 3 to 6 series cell lithium-ion/ polymer battery Datasheet

bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
Host Controlled Analog Front End for 3 to 6 Series Cell Lithium-Ion/ Polymer Battery
Protection and Gas Gauging Applications
Check for Samples: bq76925
FEATURES
DESCRIPTION
•
The bq76925 Host controlled analog front end (AFE)
is part of a complete pack monitoring, balancing and
protection system for 3, 4, 5 or 6 series cell Lithium
batteries. The bq76925 allows a Host controller to
easily monitor individual cell voltages, pack current
and temperature. This information may be used by
the Host to determine unsafe or faulty operating
conditions such as over-voltage, under-voltage,
over-temperature and over-current, as well as cell
imbalance, state of charge and state of health
conditions.
1
•
•
•
•
•
•
•
•
•
•
Analog Interface for Host cell Measurement
– Cell Input MUX, Level Shifter and Scaler
– 1.5 / 3.0 V Low-Drift, Calibrated Reference
Allows Accurate Analog to Digital
Conversions
Analog Interface for Host Current
Measurement
– Variable Gain Current Sense Amplifier
Capable of Operation with 1 mΩ Sense
Resistor
Switchable Thermistor Bias output for Host
Temperature Measurements
Overcurrent Comparator with Dynamically
Adjustable Threshold
– Alerts Host to Potential Overcurrent Faults
– May be used to Wake up Host on Load
Connect
Integrated Cell Balancing FETs
– Individual Host Control
– 50 mA per-cell Balancing Current
Supports Cell Sense-line Open Wire Detection
Integrated 3.3 V Regulator for Powering
Micro-controller and/or LEDs
I2C Interface for Host Communications
– Optional Packet CRC for Robust Operation
Supply Voltage Range From 4.2 to 26.4 V
Low Power Consumption
– 40 µA Typical in Normal Mode
– 1.5 µA Maximum in Sleep Mode
20-pin TSSOP or 24-pin QFN Package
APPLICATIONS
•
Primary Protection in Li-Ion Battery Packs
– Cordless Power Tools
– Light Electric Vehicles (E-Bike, Scooter,
etc.)
– UPS Systems
– Medical Equipment
– Portable Test Equipment
Cell input voltages are level shifted, multiplexed,
scaled and output for measurement by a Host ADC.
A low-drift calibrated reference voltage is provided on
a dedicated pin to enable accurate measurements.
The voltage across an external sense resistor is
amplified and output to a Host ADC for both charge
and discharge current measurements. Two gain
settings enable operation with a variety of sense
resistor values over a wide range of pack currents.
To enable temperature measurements by the Host,
the AFE provides a separate output pin for biasing an
external thermistor network. This output can be
switched on and off under Host control to minimize
power consumption.
The bq76925 includes a comparator with a
dynamically selectable threshold for monitoring
current. The comparator result is driven through an
open-drain output to alert the host when the threshold
is exceeded. This feature can be used to wake up the
Host on connection of the load, or to alert the Host to
a potential fault condition.
The bq76925 integrates cell balancing FETs that are
fully controlled by the Host. The balancing current is
set by external resistors up to a maximum value of 50
mA. These same FETs may be utilized in conjunction
with cell voltage measurements to detect an open
wire on a cell sense-line.
The Host communicates with the AFE via an I2C
interface. A packet CRC may optionally be used to
ensure robust operation. The device may be put into
a low-current sleep mode via the I2C interface and
awakened by pulling up the ALERT pin.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN DIAGRAMS
20
V3P3
BAT
VC6
2
19
3
18
SCL
SDA
VC5
4
17
VC4
5
16
VC3
VC2
6
15
7
VC1
VC0
VSS
SCL
1
NC
NC
V3P3
VCTL
VCTL
RGE PACKAGE
(TOP VIEW)
BAT
PW PACKAGE
(TOP VIEW)
24
23
22
19
21
20
1
18
VREF
VC6
VC5
2
17
SDA
VREF
VTB
VC4
3
16
VTB
VC3
VC2
4
15
14
VCOUT
VIOUT
14
VCOUT
VIOUT
8
13
ALERT
VC1
6
13
ALERT
9
12
10
11
SENSEP
SENSEN
bq76925
PACKAGE PREVIEW
8
9
VSS
7
10
11
12
NC
NC
SENSEN
SENSEP
5
VC0
bq76925
PIN FUNCTIONS
PIN NO.
(1)
2
NAME
TYPE
23
VCTL
Output
3.3 V Regulator control voltage (1)
2
24
BAT
Power
Supply voltage, tied to most positive cell
3
1
VC6
Input
Sense voltage for most positive cell
4
2
VC5
Input
Sense voltage for second most positive cell
5
3
VC4
Input
Sense voltage for third most positive cell
6
4
VC3
Input
Sense voltage for fourth most positive cell
7
5
VC2
Input
Sense voltage for fifth most positive cell
8
6
VC1
Input
Sense voltage for least positive cell
9
7
VC0
Input
Sense voltage for negative end of cell stack
10
8
VSS
Power
9
NC
NA
No Connection (leave open)
10
NC
NA
No Connection (leave open)
11
11
SENSEN
Input
Negative current sense
12
12
SENSEP
Input
Positive current sense
13
13
ALERT
Output
Overcurrent alert (open drain)
14
14
VIOUT
Output
Current measurement voltage
15
15
VCOUT
Output
Cell measurement voltage
16
16
VTB
Output
Bias voltage for thermistor network
17
17
VREF
Output
Reference voltage for ADC
18
18
SDA
Input / Output
I2C Data (open drain)
19
19
SCL
Input
I2C Clock (open drain)
20
20
V3P3
Output
21
NC
NA
No Connection (leave open)
22
NC
NA
No Connection (leave open)
TSSOP
QFN
1
DESCRIPTION
Ground
3.3 V Regulator
When a bypass FET is used to supply the regulated 3.3V load current, VCTL automatically adjusts to keep V3P3 = 3.3 V. If VCTL is tied
to BAT, the load current is supplied through V3P3.
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
PACK+
Bypass FET (optional)
Hold-up
circuit
(optional)
RBAT
3.3 V
uC / LED
Supply
RVCTL
DBAT
BAT
VCTL
VREG
ZBAT
CBAT
POR
V3P3
VC6
CV3P3
RIN
+
-
CIN
Cell Select
VC5
I2C
Bal Select
SCL
RIN
+
I2C
Interface
VC4
RIN
Cell MUX
+
-
CIN
Level Shift
VC3
RIN
Balance
Control
+
-
CIN
NTC Bias Switch
Thresh Select
CIN
VCOUT Select
EE
-
SDA
REGS
Ref Select
1.5 / 3.0 V
REF
ADC
Reference
VREF
CREF
REF×0.5
REF×0.85
VC2
ADC Ch 1
Temp
VTB
RIN
RTH
RNTC
+
CTH
-
CIN
+
Amp
-
VC1
RIN
+
-
CIN
ADC Ch 2
Cell Voltage
VCOUT
COUT
Gain = 0.3, 0.6
CIN
ADC Ch 3
Pack Current
VIOUT
VC0
RIN
VSS
Shunt Select
COUT
Gain Select
+
Amp
-
SENSEN
RSENSE
RSENSEN
Wakeup
Detect
Overcurrent
Alert
ALERT
Gain = 4, 8
Output Range = 1V, 2V
CSENSE
+
Amp
-
SENSEP
RSENSEP
Gain = 1
Polarity Select
ITHRESH
25,50,75,100,…,400 mV
+
Comp
-
bq76925
PACK-
ORDERING INFORMATION (1)
TA
–25°C to 85°C
(1)
(2)
(3)
PACKAGE
PART NUMBER (2)
20-Pin PW
bq76925PW
24-Pin RGE
bq76925RGE (3)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
The PW and RGE package options are also available taped and reeled. Add an R suffix to the device type (e.g., bq76925PWR for 2000
units per reel). See applications section of data sheet for layout information.
Product Preview
Copyright © 2011, Texas Instruments Incorporated
3
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
RANGE (2)
VBAT
Supply
voltage
range
Input
voltage
range
VI
MIN
MAX
UNITS
BAT
–0.3
36
V
Cell input differential, VCn to VCn+1, n = 0 to 5
–0.3
9
Cell input, VCn, n = 1 to 6
–0.3
(6 × n)
BAT to VC6 differential
–10
10
–3
3
–3
3
VC0
(3)
SENSEP, SENSEN
Output
voltage
range
VO
SCL, SDA
–0.3
6
VCOUT, VIOUT, VREF
–0.3
3.6
VTB, V3P3
–0.3
7
ALERT
–0.3
30
VCTL
–0.3
36
V
V
ICB
Cell balancing current
70
mA
IIN
Cell input current
–25
70
mA
TSTG
Storage temperature range
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltages are relative to VSS, except “Cell input differential”.
Negative voltage swings on VC0 in the absolute maximum range can cause unwanted circuit behavior and should be avoided.
THERMAL INFORMATION
bq76925
THERMAL METRIC (1)
TSSOP
(PW PACKAGE)
QFN
(RGE PACKAGE)
PRODUCT
PREVIEW
(20) PINS
(24) PINS
θJA
Junction-to-ambient thermal resistance
97.5
θJCtop
Junction-to-case (top) thermal resistance
31.7
θJB
Junction-to-board thermal resistance
48.4
ψJT
Junction-to-top characterization parameter
1.5
ψJB
Junction-to-board characterization parameter
47.9
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
(1)
4
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS (1)
MIN
Supply voltage range
MAX
UNIT
BAT
4.2
TYP
26.4
V
Cell input differential, VCn to VCn+1, n = 0 to 5
1.4
4.4
V
4.4 × n
V
8
V
Cell input, VCn, n = 1 to 6
BAT to VC6 differential
VIN
Input voltage range
SENSEP
SCL, SDA
V3P3
Backfeeding (2)
ALERT
Wakeup function
VCOUT, VIOUT
VREF
VOUT
Output voltage range
ALERT
RBAT
BAT filter resistance
CBAT
BAT filter capacitance
RIN
External cell input resistance
CIN
External cell input capacitance
RSENSEN
RSENSEP
Current sense input filter resistance
CSENSE
Current sense input filter capacitance
RVCTL
VCTL pullup resistance
CV3P3
V3P3 output capacitance
CREF
VREF output capacitance
COUT
ADC channel output capacitance
TOPR
TFUNC
(1)
(2)
(3)
V
–125
375
mV
0
5.5
V
5.5
V
0
26.4
V
0
V3P3 +
0.2
V
REFSEL = 0
1.5
V
REFSEL = 1
3.0
V
Regulating
3.3
5.5
VCTL
Cell balancing current
0
VTB
V3P3
ICB
–8
VC0, SENSEN
Alert function
V
V
0.8
26.4
0
5.5
V
0
50
mA
100
Ω
10
µF
(3)
Ω
100
0.1
Without external bypass transistor
1
10
µF
1K
Ω
0.1
µF
0
With external bypass transistor
V
Ω
200K
Without external bypass transistor
4.7
With external bypass transistor
1.0
µF
µF
1.0
µF
VCOUT
0.1
VIOUT
470
2000
pF
Operating free-air temperature
–25
85
°C
Functional free-air temperature
–40
100
°C
All voltages are relative to VSS, except “Cell input differential”.
Internal 3.3 V regulator may be overridden (i.e. backfed) by applying an external voltage larger than the regulator voltage.
RIN,MIN = 0.5 × (VCnMAX / 50 mA) if cell balancing used so that maximum recommended cell balancing current is not exceeded
Copyright © 2011, Texas Instruments Incorporated
5
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS
BAT = 4.2 to 26.4V, VCn = 1.4 to 4.4, TA = –25°C to 85°C
Typical values stated where TA = 25°C and BAT= 21.6V (unless otherwise noted)
Supply Current
PARAMETER
TYP
MAX
Normal mode supply current
All device functions enabled
All pins unloaded
SDA and SCL high
40
48
µA
Standby mode 1 supply current
V3P3 and overcurrent monitor enabled
All pins unloaded
All other device functions disabled
SDA and SCL high
14
17
µA
Standby mode 2 supply current
V3P3 enabled
All pins unloaded
All device functions disabled
SDA and SCL high
12
14
V
Sleep mode supply current
V3P3 disabled
All pins unloaded
All device functions disabled
SDA and SCL low
1.0
1.5
µA
2.4
2.7
IVCn
Input current for selected cell
All cell voltages equal
Cell balancing disabled
Open cell detection disabled
during cell voltage monitoring
∆IVCn
Cell to cell input current difference
All cell voltages equal
Cell balancing disabled
Open cell detection disabled
IDD1
IDD2
IDD3
IDD4
TEST CONDITION
MIN
n=6
n=1–5
< 0.5
UNIT
µA
< 0.2
µA
UNIT
Internal Power Control (Startup and Shutdown)
PARAMETER
VPOR
Power on reset voltage
TEST CONDITION
Measured at BAT pin
MIN
TYP
MAX
Initial BAT < 1.4
VBAT rising (1)
4.3
4.5
4.7
V
Initial BAT > 1.4
VBAT rising (1)
6.5
7.0
7.5
V
3.6
V
VSHUT
Shutdown voltage (2)
Measured at BAT pin, BAT falling
tPOR
Time delay after POR before I2C
comms allowed
CV3P3 = 4.7 µF
VWAKE
Wakeup voltage
Measured at ALERT pin
tWAKE_PLS
Wakeup signal pulse width
tWAKE_DLY
Time delay after wakeup before
I2C comms allowed
(1)
(2)
6
CV3P3 = 4.7 µF
1
ms
0.8
2
V
1
5
μs
1
ms
Initial power up will start with BAT < 1.4 V, however if BAT falls below VSHUT after rising above VPOR, the power on threshold depends
on the minimum level reached by BAT after falling below VSHUT
Following POR, the device will operate down to this voltage.
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
3.3 V Voltage Regulator
PARAMETER
TEST CONDITION
MIN
TYP MAX
UNIT
3.3 V VOLTAGE REGULATOR
(1) (2)
VCTL
Regulator control voltage
VV3P3
Regulator output
IREG
V3P3 output current
ISC
V3P3 short circuit current limit
V3P3 = 0.0 V
VTB
Thermistor bias voltage
Measured at VTB, ITB = 0
ITB
Thermistor bias current
RTB
Thermistor bias internal resistance RDS,ON for internal FET switch, ITB = 1.0 mA
(1)
(2)
Measured at VCTL, V3P3 regulating
3.3
Measured at V3P3, IREG = 0 to 4 mA,
BAT = 4.2 to 26.4 V
3.2
3.3
10.0
26.4
V
3.4
V
4.0
mA
17.0
mA
1.0
mA
130
Ω
VV3P3
90
V
When a bypass FET is used to supply the regulated 3.3V load current, VCTL automatically adjusts to keep V3P3 = 3.3 V. Note that
VCTL,MIN and the FET VGS will determine the minimum BAT voltage at which the bypass FET will operate.
If VCTL is tied to BAT, the load current is supplied through V3P3.
Voltage Reference
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
V
VOLTAGE REFERENCE
Before gain correction, TA = 25°C
VREF
VREF_CAL
Voltage reference output
Reference calibration
voltage
After gain correction,
TA = 25°C
Measured at VCOUT
∆VREF
Voltage reference tolerance TA = 0 – 50°C
IREF
VREF output current
(1)
(1)
REF_SEL = 0
1.44
1.56
REF_SEL = 1
2.88
3.12
REF_SEL = 0
–0.1%
1.5 +0.1%
REF_SEL = 1
–0.1%
3.0 +0.1%
VCOUT_SEL = 2
–0.9%
0.5 × +0.9%
VREF
VCOUT_SEL = 3
–0.5% 0.85 × +0.5%
VREF
(0.85 × VREF) – (0.5
× VREF)
–0.3% 0.35 × +0.3%
VREF
–40
V
V
40
ppm/
°C
10
µA
Gain correction factor determined at final test and stored in non-volatile storage. Gain correction is applied by Host controller.
Cell Voltage Amplifier
PARAMETER
TEST CONDITION
GVCOUT
Cell voltage amplifier gain
Measured from VCn to VCOUT
OVCOUT
Cell voltage amplifier offset
Measured from VCn to VCOUT
VCOUT
Cell voltage amp output range
(1)
Measured at VCOUT, VCn = 5.0V
MIN
TYP
MAX
REF_SEL = 0
–1.6%
0.3
1.5%
REF_SEL = 1
–1.6%
0.6
1.5%
–16
∆VCOUT
Cell voltage amplifier accuracy
1.47
1.5
1.53
V
REF_SEL = 1
2.94
3.0
3.06
V
0.0
–3
3
TA = 0°C to 50°C
–5
5
TA = –25°C to 85°C
–8
8
VCOUT output current (5)
tVCOUT
Delay from VCn select to VCOUT Output step of 200 mV. COUT = 0.1 µF
(5)
V
TA = 25°C
IVCOUT
(1)
(2)
(3)
(4)
mV
REF_SEL = 0
Measured at VCOUT, VCn = 0.0V
VCn = 1.4 V to 4.4 V, After
correction, (2)
Measured at VCOUT (3)
REF_SEL = 1 (4)
15
UNIT
mV
10
µA
100
µs
For VCn values greater than 5.0 V, VCOUT clamps at approximately V3P3.
Correction factor determined at final test and stored in non-volatile storage. Correction is applied by Host controller.
Output referred. Input referred accuracy is calculated as ∆VCOUT / GVCOUT (e.g. 3 / 0.6 = 5).
Correction factors are calibrated for gain of 0.6. Tolerance at gain of 0.3 is approximately doubled. Contact TI for information on devices
calibrated to a gain of 0.3.
Max DC load for specified accuracy.
Copyright © 2011, Texas Instruments Incorporated
7
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
Current Sense Amplifier
PARAMETER
GVIOUT
VIIN
TEST CONDITION
Current sense amplifier gain
Measured from SENSEN,
SENSEP to VIOUT
Current sense amp input range
Measured from SENSEN,
SENSEP to VSS
Current sense amp output range
Measured at VIOUT
Zero current output
Measured at VIOUT
SENSEP = SENSEN
VIOUT
∆VIOUT
Current amplifier accuracy
IVIOUT
VIOUT output current
(1)
MIN
TYP
MAX
UNIT
–125
375
mV
REF_SEL = 0
0.25
1.25
V
REF_SEL = 1
0.5
2.5
V
I_GAIN = 0
4
I_GAIN = 1
8
REF_SEL = 0
1.0
REF_SEL = 1
2.0
V
V
–1%
1%
(1)
µA
10
Max DC load for specified accuracy
Over Current Comparator
PARAMETER
VBAT_COMP
TEST CONDITION
TYP
Comparator amplifier gain
VITRIP
Current comparator trip threshold (2)
MAX
UNIT
5
Measured from SENSEP to comparator
input
GVCOMP
V
1
25
400
mV
VITRIP = 25 mV
–6
6
mV
VITRIP > 25 mV
–10%
10%
V
0.4
V
∆VITRIP
Current comparator accuracy
VOL_ALERT
ALERT Output Low Logic
VOH_ALERT
ALERT Output High Logic
IALERT
ALERT Pulldown current
ALERT = 0.4 V, Output driving low
IALERT_LKG
ALERT Leakage current
ALERT = 5.0 V, Output high-Z
tOC
Comparator response time
(1)
(2)
(3)
MIN
Minimum VBAT for comparator operation (1)
IALERT = 1 mA
(3)
NA
NA
NA
1
mA
<1
μA
100
µs
TYP
MAX
UNIT
1.2
1.25
The Over Current Comparator is not guaranteed to work when VBAT is below this voltage.
Trip threshold selectable from 25, 50, 75, 100, 125, 150, 175, 200, 225, 250, 275, 300, 325, 350, 375 or 400 mV
This parameter NA because output is open drain.
Internal Temperature Measurement
PARAMETER
VTEMP_INT
Internal temperature voltage
∆VTEMP_INT
Internal temperature voltage sensitivity
TEST CONDITION
MIN
Measured at VCOUT, TINT = 25°C
1.15
–4.4
V
mV /
ºC
Cell Balancing and Open Cell Detection
PARAMETER
RBAL
(1)
8
Cell balancing internal resistance (1)
TEST CONDITION
MIN
TYP
MAX
RDS,ON for VC1 internal FET switch,
VCn = 3.6 V
1
3
5
RDS,ON for internal VC2 to VC6 FET switch,
VCn = 3.6 V
3
5.5
8
UNIT
Ω
Balancing current is not internally limited. The cell balancing operation is completely controlled by the Host processor, no automatic
function or time-out is included in the part. Care must be used to ensure that balancing current through the part is below the maximum
power dissipation limit. The Host algorithm is responsible for limiting thermal dissipation to package ratings.
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
I2C Compatible Interface
DC PARAMETERS
MIN
VIL
Input Low Logic Threshold
VIH
Input High Logic Threshold
VOL
Output Low Logic Drive
VOH
Output High Logic Drive (Not applicable due to open-drain outputs)
ILKG
I2C Pin Leakage
TYP
MAX
0.6
2.8
UNIT
V
V
IOL = 1 mA
0.20
IOL = 2.5 mA
V
0.40
N/A
Pin = 5.0 V, Output in high-Z
V
<1
µA
AC PARAMETERS
tr
SCL, SDA Rise Time
1000
ns
tf
SCL, SDA Fall Time
300
ns
tw(H)
SCL Pulse Width High
4.0
µs
tw(L)
SCL Pulse Width Low
4.7
µs
tsu(STA)
Setup time for START condition
4.7
µs
th(STA)
START condition hold time after which first clock pulse is generated
4.0
µs
tsu(DAT)
Data setup time
250
ns
th(DAT)
Data hold time
0 (1)
µs
tsu(STOP)
Setup time for STOP condition
4.0
µs
tsu(BUF)
Time the bus must be free before new transmission can start
4.7
tV
Clock Low to Data Out Valid
th(CH)
Data Out Hold Time After Clock Low
0
fSCL
Clock Frequency
0
tWAKE
I2C ready after transition to Wake Mode
(1)
µs
900
ns
ns
100
kHz
2.5
ms
Devices must provide internal hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.
SCL
SDA
SCL
SDA
SCL
SDA
Figure 1. I2C Timing
Copyright © 2011, Texas Instruments Incorporated
9
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
OPERATIONAL OVERVIEW
INTRODUCTION
The bq76925 Host controlled analog front end (AFE) is part of a complete pack monitoring, balancing and
protection system for 3 to 6 series cell Lithium batteries. The bq76925 allows a Host controller to easily monitor
individual cell voltages, pack current and temperature. This information can be used by the Host to detect and
act on a fault condition caused when one or more of these parameters exceed the limits of the application. In
addition, this information may be used by the Host to determine end-of-charge, end-of-discharge and other
gas-gauging and state of health conditions.
PACK+
BAT
VCTL
AVCC
V3P3
DVCC
VC6
+
VC5
SCL
SCL
VC4
SDA
SDA
P1.5
COMM
+
-
µController
+
-
VeREF+
VREF
VC3
bq76925
+
VC2
VTB
RTH
RNTC
+
-
Example:
MSP430x20x2
A0
or
equivalent
VC1
VCOUT
A1
VC0
VIOUT
A2
+
VeREFAVSS
VSS
ALERT
DVSS
NMI
SENSEP
Note: Some components
omitted for clarity.
P2.7
SENSEN
P2.6
RSENSE
FET Driver Circuits
PACK-
Example only. Not required.
Figure 2. Example of bq76925 With Host Controller
10
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
POWER MODES
Power On Reset (POR)
When initially powering up the bq76925, the voltage on the BAT pin must exceed VPOR (4.7 V max) before the
device will turn on. Following this, the device will remain operational as long as the voltage on BAT remains
above VSHUT (3.6 V max). If the BAT voltage falls below VSHUT the device will shut down. Recovery from
shutdown occurs when BAT rises back above the VPOR threshold and is equivalent to a POR. The VPOR threshold
following a shutdown depends on the minimum level reached by BAT after crossing below VSHUT. If BAT does
not fall below ~1.4 V, a higher VPOR (7.5 V max) applies. This is illustrated in Figure 3.
VBAT
VPOR
Initial BAT > 1.4 V
VPOR
Initial BAT < 1.4 V
VSHUT
1.4 V
OFF
ON
OFF
ON
Figure 3. Power On State vs VBAT
Following a power on reset, all volatile registers assume their default state. Therefore, care must be taken that
transients on the BAT pin during normal operation do not fall below VSHUT. To avoid this condition in systems
subject to extreme transients or brown-outs, a hold-up circuit such as the one shown in the functional diagram is
recommended. When a hold-up circuit is used, care must be taken to observe the BAT to VC6 maximum ratings.
Standby
Individual device functions such as cell translator, current amplifier, reference and current comparator can be
enabled and disabled under Host control by writing to the POWER_CTL register. This feature can be used to
save power by disabling functions that are unused. In the minimum power standby mode, all device functions can
be turned off leaving only the 3.3 V regulator active.
Sleep
In addition to standby, a sleep mode is provided by which the Host can order the bq76925 to shutdown all
internal circuitry including the LDO regulator. In this mode the device will consume a minimal amount of current
(< 1.5 μA) due only to leakage and powering of the wake-up detection circuitry.
Sleep mode is entered by writing a ‘1’ to the SLEEP bit in the POWER_CTL register. In sleep mode, all functions
including the LDO are disabled. Wake-up is achieved by pulling up the ALERT pin; however the wake-up circuitry
is not armed until the voltage at V3P3 drops to ~0 V. To facilitate the discharge of V3P3, an internal 3 kΩ
pull-down is connected from V3P3 to VSS during the time that sleep mode is active. Once V3P3 is discharged,
the bq76925 may be awakened by pulling the ALERT pin above VWAKE (2 V max).
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The SLEEP_DIS bit in the POWER_CTL register acts as an override to the sleep function. When SLEEP_DIS is
set to ‘1’, writing the SLEEP bit has no effect (i.e. sleep mode cannot be entered). If SLEEP_DIS is set after
sleep mode has been entered, the device will immediately exit sleep mode. This scenario can arise if
SLEEP_DIS is set after SLEEP is set, but before V3P3 has discharged below a valid operating voltage. This
scenario can also occur if the V3P3 pin is held up by external circuitry and not allowed to fully discharge.
If the over-current alert function is not used, the ALERT pin can function as a dedicated wake-up pin. Otherwise,
the ALERT pin will normally be pulled up to the LDO voltage, so care must be taken in the system design so that
the wake-up signal does not interfere with proper operation of the regulator.
Internal LDO Voltage Regulator
The bq76925 provides a regulated 3.3 V supply voltage on the V3P3 pin for operating the device’s internal logic
and interface circuitry. This regulator may also be used to directly power an external microcontroller or other
external circuitry up to a limit of 4 mA load current. In this configuration, the VCTL pin is tied directly to the BAT
pin. For applications requiring more than 4 mA, an external bypass transistor may be used to supply the load
current. In this configuration the VCTL pin is tied to the gate of the bypass FET. These two configurations are
show in Figure 4.
PACK +
PACK+
R VCTL
R BAT BAT
CBAT
3.3 V
R BAT BAT
VREG
VCTL
C BAT
VREG
V3P3
V3P3
C V3P3
bq76925
a) Regulator load supplied through bq76925
VCTL
bq76925
C V3P3
b) Regulator load supplied through external
pass device
Figure 4. LDO Regulator Configurations
For the configuration of Figure 4B), a high gain bypass device should be used to ensure stability. A bipolar PNP
or p-channel FET bypass device may be used. Contact TI for recommendations.
The LDO regulator may be overridden (i.e., back-fed) by an external supply voltage greater than the regulated
voltage on V3P3. In this configuration the bq76925 internal logic and interface circuitry will operate from the
external supply and the internal 3.3 V regulator will supply no load current.
ADC Interface
The bq76925 is designed to interface to a multi-channel analog-to-digital converter (ADC) located in an external
Host controller, such as an MSP430 Microcontroller or equivalent. Three outputs provide voltage, current and
temperature information for measurement by the Host. In addition, the bq76925 includes a low-drift calibrated 1.5
/ 3 V reference that is output on a dedicated pin for use as the reference input to the ADC.
The gain and offset characteristics of the bq76925 are measured during factory test and stored in non-volatile
memory as correction factors. The Host reads these correction factors and applies them to the ADC conversion
results in order to achieve high measurement accuracy. In addition, the precise voltage reference of the bq76925
can be used to calibrate out the gain and offset of the Host ADC.
Reference Voltage
The bq76925 outputs a stable reference voltage for use by the Host ADC. A nominal voltage of 1.5 V or 3 V is
selected via the REF_SEL bit in the CONFIG_2 register. The reference voltage is very stable across
temperature, but the initial voltage may vary by ±4%. The variation from nominal is manifested as a gain error in
the ADC conversion result. To correct for this error, offset and gain correction factors are determined at final test
and stored in the non-volatile registers VREF_CAL and VREF_CAL_EXT. The Host reads the correction factors
and applies them to the nominal reference voltage to arrive at the actual reference voltage as described under
Cell Voltage Monitoring. After gain correction, the tolerance of the reference will be within ±0.1%.
12
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
Host ADC Calibration
All analog to digital converters have inherent gain and offset errors which adversely affect measurement
accuracy. Some microcontrollers may be characterized by the manufacturer and shipped with ADC gain and
offset information stored on-chip. It is also possible for such characterization to be done by the end-user on loose
devices prior to PCB assembly, or as a part of the assembled PCB test.
For applications where such ADC characterization is not provided or is not practical, the bq76925 provides a
means for in-situ calibration of the Host ADC. Through setting of the VCOUT_SEL bits in the CELL_CTL register
two scaled versions of the reference voltage, 0.5 × VREF and 0.85 × VREF, can be selected for output on the
VCOUT pin for measurement by the Host ADC. Measuring both scaled voltages enables the Host to do a
two-point calibration of the ADC and compensate for the ADC offset and gain in all subsequent ADC
measurement results as shown in Figure 5.
Note that the calibration accuracy will be limited by the tolerance of the scaled reference voltage output so that
use of this method may not be effective. For these cases, it is recommended to use a higher accuracy source for
the two-point calibration shown in Figure 5.
VOUT
Slope =
Actual gain = G’
Actual transfer curve:
VADC,ACT = G’ × VIN + VOFFSET
Ideal transfer curve:
VADC,IDEAL = VIN
Corrected result:
VADC,COR = (VADC,ACT – VOFFSET) ÷ G’
Slope =
Ideal gain = 1
VOFFSET
VIN
VREF × 0.5
VREF × 0.85
Figure 5. Host ADC Calibration Using VREF
Cell Voltage Monitoring
The cell voltage monitoring circuits include an input level-shifter, multiplexer (MUX) and scaling amplifier. The
Host selects one VCn cell input for measurement by setting the VCOUT_SEL and CELL_SEL bits in the
CELL_CTL register. The scaling factor is set by the REF_SEL bit in the CONFIG_2 register. The selected cell
input is level shifted to VSS reference, scaled by a nominal gain GVCOUT = 0.3 (REF_SEL = 0) or 0.6 (REF_SEL
= 1) and output on the VCOUT pin for measurement by the Host ADC.
Similar to the reference voltage, gain and offset correction factors are determined at final test for each individual
cell input and stored in non-volatile registers VCn_CAL (n = 1-6) and VC_CAL_EXT_m (m = 1-2). These factors
are read by the Host and applied to the ADC voltage measurement results in order to obtain the specified
accuracy.
The cell voltage offset and gain correction factors are stored as 5-bit signed integers in 2’s complement format.
The most significant bits (VCn_OC_4, VCn_GC_4) are stored separately and must be concatenated with the
least significant bits (VCn_OFFSET_CORR, VCn_GAIN_CORR).
The reference voltage offset and gain correction factors are stored respectively as a 6-bit and 5-bit signed integer
in 2’s complement format. As with the cell voltage correction factors, the most significant bits (VREF_OC_5,
VREF_OC_4, VREF_GC_4) are stored separately and must be concatenated with the least significant bits
(VREF_OFFSET_CORR, VREF_GAIN_CORR).
Copyright © 2011, Texas Instruments Incorporated
13
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The actual cell voltage (VCn) is calculated from the measured voltage (VCOUT) as shown in the following
equations:
ADC Count
VCOUT =
× VREFNOMINAL
Full Scale Count
VCn =
VCOUT ´ GCV REF + OCVCOUT
G VCO UT
× (1 + GC VCOUT )
(1)
spacer
spacer
GCVCOUT = éë(VCn_GC_4 << 4 ) + VCn_GAIN_CORR ùû ´ 0.001,
OCVCOUT = ëé(VCn_OC_4 << 4 ) + VCn_OFFSET_CORR ûù ´ 0.001,
GCVREF = (1 + éë(VREF_GC_4 << 4 ) + VREF_GAIN_CORR ùû ´ 0.001)
é(VREF_OC_5 << 5 ) + (VREF_OC_4 << 4 ) + VREF_OFFSET_CORR ûù ´ 0.001
+ ë
VREFNOMINAL
(2)
Cell Amplifier Headroom Under Extreme Cell Imbalance
For cell voltages across (VC1 – VC0) that are less than ~2.64 V, extreme cell voltage imbalances between
(VC1 – VC0) and (VC2 – VC1) can lead to a loss of gain in the (VC2 – VC1) amplifier. The cell imbalance at
which the loss of gain occurs is determined by the following equation:
(VC2 - VC1) ´ 0.6 > (VC1 - VSS)
(3)
Assuming VC0 = VSS, it can be seen that when (VC1 – VC0) > 2.64 volts, the voltage across (VC2 – VC1) can
range up to the limit of 4.4 V without any loss of gain. At the minimum value of (VC1 – VC0) = 1.4 V, an
imbalance of more than 900 mV is tolerated before any loss of gain in the (VC2 – VC1) amplifier. For higher
values of (VC1 – VC0), increasingly large imbalances are tolerated. For example, when (VC1 – VC0) = 2.0 V, an
imbalance up to 1.33 V (i.e. (VC2 – VC1) = 3.33 V) results in no degradation of amplifier performance.
Normally, cell imbalances greater than 900 mV will signal a faulty condition of the battery pack and its use should
be discontinued. The loss of gain on the second cell input does not affect the ability of the system to detect this
condition. The gain fall-off is gradual so that the measured imbalance will never be less than the critical
imbalance set by Equation 3.
Therefore if the measured (VC2 – VC1) is greater than (VC1 – VSS) / 0.6, a severe imbalance is detected and
the pack should enter a fault state which prevents further use. In this severe cell imbalance condition
comparisons of the measured (VC2 – VC1) to any over-voltage limits will be optimistic due to the reduced gain in
the amplifier, further emphasizing the need to enter a fault state.
Cell Amplifier Headroom Under BAT Voltage Drop
Voltage differences between BAT and the top cell potential come from two sources as shown in Figure 6: V3P3
regulator current that flows through the RBAT filter resistor, and the voltage drop in the series diode DBAT of the
hold-up circuit. These effects cause BAT to be less than the top cell voltage measured by the cell amplifier.
14
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
PACK+
RBAT DBAT
Z BAT
BAT
VCTL
VREG
CBAT
V3P3
CV3P3
VC6
+
-
bq76925
Figure 6. Sources of Voltage Drop Affecting the BAT Pin
The top cell amplifier (VC6 – VC5) is designed to measure an input voltage down to 1.4 V with a difference
between the BAT and VC6 pin up to 1.2 V (i.e. BAT can be 1.2 V lower than VC6). However, in applications with
fewer than 6 cells, the upper cell inputs are typically shorted to the top cell input. For example, in a 5-cell
application VC6 and VC5 would be shorted together and the (VC5 – VC4) amplifier would measure the top cell
voltage. The case is similar for 4- and 3-cell applications.
For these cases when using the (VC5 – VC4), (VC4 –VC3) or (VC3 – VC2) amplifier to measure the top cell, the
difference between BAT and the top cell amplifier must be less than 240 mV in order to measure cell voltages
down to 1.4 V. Note that at higher cell input voltages the top amplifier tolerates a greater difference. For example,
in a 5-cell configuration (VC6 and VC5 tied together) the (VC5 – VC4) amplifier is able to measure down to a 1.7
V input with a 600 mV difference between VC5 and BAT.
Accordingly, in systems with fewer than 6 cells it is important in system design to minimize RBAT and to use a
Schottky type diode for DBAT with a low forward voltage. If it is not possible to reduce the drop at BAT to an
acceptable level, then for 4 and 5 cell configurations the (VC6 – VC5) amplifier may be used as the top cell
amplifier as show in Table 1, which allows up to a 1.2 V difference between BAT and top cell.
Table 1. Alternate Connections for 4 and 5 Cells
Configuration
Cell 5
Cell 4
Cell 3
Cell 2
Cell 1
5-cell
VC6 – VC5
VC4 – VC3
VC3 – VC2
VC2 – VC1
VC1 – VC0
Short VC5 to VC4
VC6 – VC5
VC3 – VC2
VC2 – VC1
VC1 – VC0
Short VC5 to VC4 to VC3
4-cell
Unused Cell Inputs
Current Monitoring
Current is measured by converting current to voltage via a sense resistor connected between SENSEN and
SENSEP. A positive voltage at SENSEP with respect to SENSEN indicates a discharge current is flowing, and a
negative voltage indicates a charge current. The small voltage developed across the sense resistor is amplified
by gain GVIOUT and output on the VIOUT pin for conversion by the Host ADC. The voltage on VIOUT is always
positive and for zero current is set to 3/4 of the output range. The current sense amplifier is inverting; discharge
current causes VIOUT to decrease and charge current causes VIOUT to increase. Therefore, the measurement
range for discharge currents is 3 times the measurement range for charge currents.
The current sense amplifier is preceded by a multiplexer that allows measurement of either the SENSEN or
SENSEP input with respect to VSS. The Host selects the pin for measurement by writing the I_AMP_CAL bit in
the CONFIG_1 register. The Host then calculates the voltage across the sense resistor by subtracting the
measured voltage at SENSEN from the measured voltage at SENSEP. If the SENSEN and VSS connections are
such that charge and discharge currents do not flow through the connection between them, i.e. there is no
voltage drop between SENSEN and VSS due to the current being measured, then the measurement of the
SENSEN voltage can be regarded as a calibration step and stored by the Host for use as a pseudo-constant in
the VSENSE calculation. The SENSEN voltage measurement would then only need updating when changing
environmental conditions warrant.
Copyright © 2011, Texas Instruments Incorporated
15
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
The Host sets GVIOUT by writing the I_GAIN bit in the CONFIG_1 register. The available gains of 4 and 8 enable
operation with a variety of sense resistor values over a broad range of pack currents. The gain may be changed
at any time allowing for dynamic range and resolution adjustment. The input and output ranges of the amplifier
are determined by the value of the REF_SEL bit in the CONFIG_2 register. These values are shown in Table 2.
Because the current amplifier is inverting, the Min column under Output Range corresponds to the Max column
under Input Range. Likewise, the Max column under Output Range corresponds to the Min column under Input
Range.
The actual current is calculated from the measured voltage (VIOUT) as follows. Note that VSENSE is positive when
discharge current is flowing. In keeping with battery pack conventions, the sign of ISENSE is inverted so that
discharge current is negative.
-(VIOUT(SENSEP) - VIOUT(SENSEN))
VSENSE =
GVIOUT
ISENSE = -
VSENSE
RSENSE
(4)
Table 2. Current Amplifier Configurations
Input Range (1) (mV)
REF_SEL
I_GAIN
Gain
VIOUT (V) at
ISENSE = 0
(typical)
0
0
4
1.0
0
1
8
1.0
1
0
4
2.0
1
1
8
2.0
–62.5
(1)
(2)
(3)
Output Range (V) (2)
ISENSE
Resolution
(mA)w/10-bit
ADC (3)
Min
Max
Min
Max
ISENSE Range (A)
at RSENSE = 1
mΩ
–62.5
187.5
0.25
1.25
–62.5 – 187.5
366
–14
91
0.27
1.11
–14 – 91
183
–125
375
0.5
2.5
–125 – 375
732
187.5
0.5
2.5
–62.5 – 187.5
366
SENSEN or SENSEP measured with respect to VSS.
Output range assumes typical value of VIOUT at ISENSE = 0. For non-typical values, the output range will shift accordingly.
Assumes 1 mΩ RSENSE and ADC reference voltage of 1.5 V and 3.0 V when REF_SEL = 0 and 1, respectively.
Over Current Monitoring
The bq76925 also includes a comparator for monitoring the current sense resistor and alerting the Host when the
voltage across the sense resistor exceeds a selected threshold. The available thresholds range from 25 mV to
400 mV and are set by writing the I_THRESH bits in the CONFIG_1 register. Positive (discharge) or negative
(charge) current may be monitored by setting the I_COMP_POL bit in the CONFIG_1 register. By the choice of
sense resistor and threshold a variety of trip points are possible to support a wide range of applications.
The comparator result is driven through the open-drain ALERT output to signal the host when the threshold is
exceeded. This feature can be used to wake up the Host on connection of a load, or to alert the Host to a
potential fault condition. The ALERT pin state is also available by reading the ALERT bit in the STATUS register.
Temperature Monitoring
To enable temperature measurements by the Host, the bq76925 provides the LDO regulator voltage on a
separate output pin (VTB) for biasing an external thermistor network. In order to minimize power consumption,
the Host may switch the VTB output on and off by writing to the VTB_EN bit in the POWER_CTL register. Note
that if the LDO is back-fed by an external source, the VTB bias will be switched to the external source.
In a typical application, the thermistor network will consist of a resistor in series with an NTC thermistor, forming
a resistor divider where the output is proportional to temperature. This output may be measured by the Host ADC
to determine temperature.
Internal Temperature Monitoring
The internal temperature (TINT) of the bq76925 can be measured by setting VCOUT_SEL = ‘01’ and CELL_SEL
= ‘110’ in the CELL_CTL register. In this configuration, a voltage proportional to temperature (VTEMP_INT) is output
on the VCOUT pin. This voltage is related to the internal temperature as follows:
VTEMP_INT(mV) = VTEMP_INT(TINT = 25°C) – TINT(°C) × ΔVTEMP_INT
16
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Cell Balancing and Open Cell Detection
The bq76925 integrates cell balancing FETs that are individually controlled by the Host. The balancing method is
resistive bleed balancing, where the balancing current is set by the external cell input resistors. The maximum
allowed balancing current is 50 mA per cell.
The Host may activate one or more cell balancing FETs by writing the BAL_n bits in the BAL_CTL register. To
allow the greatest flexibility, the Host has complete control over the balancing FETs. However, in order to avoid
exceeding the maximum cell input voltage, the bq76925 will prevent two adjacent balancing FETs from being
turned on simultaneously. If two adjacent bits in the balance control register are set to 1, neither balancing
transistor will be turned on. The Host based balancing algorithm must also limit the power dissipation to the
maximum ratings of the device.
In a normal system, closing a cell balancing FET will cause 2 cell voltages to appear across one cell input. This
fact can be utilized to detect a cell sense-line open condition, i.e. a broken wire from the cell sense point to the
bq76925 VCn input. Table 3 shows how this can be accomplished. Note that the normal cell voltage
measurements may represent a saturated or full scale reading. However, these will normally be distinguishable
from the open cell measurement.
Table 3. Open Cell Detection Method
Method 1
Kelvin
input to
test
Turn On
VC0
BAL_1
VC1
VC2
Method 2
Result
Result
Measure
Turn On
Normal
Open
CELL2
CELL2 + 0.5 × CELL1
CELL2
BAL_2
CELL3
CELL3 + 0.5 × CELL2
CELL3
BAL_3
CELL4
CELL4 + 0.5 × CELL3
CELL4
BAL_2
VC3
BAL_4
CELL5
CELL5 + 0.5 × CELL4
CELL5
BAL_3
VC4
BAL_5
CELL6
CELL6 + 0.5 × CELL5
CELL6
Measure
Normal
Open
CELL1
CELL1 + 0.5 × CELL2
CELL1
CELL2
CELL2 + 0.5 × CELL3
CELL2
BAL_4
CELL3
CELL3 + 0.5 × CELL4
CELL3
VC5
BAL_5
CELL4
CELL4 + 0.5 × CELL5
CELL4
VC6
BAL_6
CELL5
CELL5 + 0.5 × CELL6
CELL5
It should be noted that the cell amplifier headroom limits discussed above apply to the open cell detection
method because by virtue of closing a switch between 2 cell inputs, internally to the device this appears as an
extreme cell imbalance. Therefore, when testing for an open on CELL2 by closing the CELL1 balancing FET, the
CELL2 measurement will be less than the expected normal result due to gain loss caused by the imbalance.
However, the CELL2 measurement will still increase under this condition so that a difference between open (no
change) and normal (measured voltage increases) can be detected.
Host Interface
The Host communicates with the AFE via an I2C interface. A CRC byte may optionally be used to ensure robust
operation. The CRC is calculated over all bytes in the message according to the polynomial x8 + x2 + x + 1.
I2C Addressing
In order to reduce communications overhead, the addressing scheme for the I2C interface combines the slave
device address and device register addresses into a single 7-bit address as shown below.
ADDRESS[6:0] = (I2C_GROUP_ADDR[3:0] << 3) + REG_ADDR[4:0]
The I2C_GROUP_ADDR is a 4-bit value stored in the EEPROM. REG_ADDR is the 5-bit register address being
accessed, and can range from 0x00 – 0x1F. The factory programmed value of the group address is ‘0100’.
Contact TI if an alternative group address is required.
For the default I2C_GROUP_ADDR, the combined address can be formed as shown in Table 4.
Table 4. Combined I2C Address for Default Group
Address
ADDRESS[6:0]
Copyright © 2011, Texas Instruments Incorporated
6
5
4:0
0
1
Register address
17
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
Bus Write Command to bq76925
The Host writes to the registers of the bq76925 as shown in Figure 7. The bq76925 acknowledges each received
byte by pulling the SDA line low during the acknowledge period.
The Host may optionally send a CRC after the Data byte as shown. The CRC for write commands is enabled by
writing the CRC_EN bit in the CONFIG_2 register. If the CRC is not used, then the Host generates the Stop
condition immediately after the bq76925 acknowledges receipt of the Data byte.
When the CRC is disabled, the bq76925 will act on the command on the first rising edge of SCL following the
ACK of the Data byte. This occurs as part of the normal bus setup prior to a Stop. If a CRC byte is sent while the
CRC is disabled, the first rising edge of the SCL following the ACK will be the clocking of the first bit of the CRC.
The bq76925 does not distinguish these two cases. In both cases, the command will complete normally, and in
the latter case the CRC will be ignored.
SCL
A6
SDA
Start
A5 ... A0 R/W ACK
Address
D7 D6 ... D0 ACK
C7 C6 ... C0 ACK
Data
CRC
(optional)
Stop
Figure 7. I2C Write Command
Bus Read Command from bq76925
The Host reads from the registers of the bq76925 as shown in Figure 8. This protocol is similar to the write
protocol, except that the slave now drives data back to the Host. The bq76925 acknowledges each received byte
by pulling the SDA line low during the acknowledge period. When the bq76925 sends data back to the Host, the
Host drives the acknowledge.
The Host may optionally request a CRC byte following the Data byte as shown. The CRC for read commands is
always enabled, but not required. If the CRC is not used, then the Host simply NACK’s the Data byte and then
generates the Stop condition.
SCL
A6
SDA
Start
A5 ... A0 R/W ACK
Address
D7 D6 ... D0 ACK
Slave
Drives Data
C7 C6 ... C0 NACK
Slave
Drives CRC
(optional)
Stop
Master
Drives NACK
Figure 8. I2C Read Command
18
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bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
Register Map
Address
Name
Access
0x00
STATUS
R/W
D7
D6
0x01
CELL_CTL
R/W
0x02
BAL_CTL
R/W
0x03
CONFIG_1
R/W
0x04
CONFIG_2
R/W
CRC_EN
0x05
POWER_CTL
R/W
SLEEP
0x06
Reserved
R/W
D5
D4
D3
D2
D1
D0
ALERT
CRC_ERR
POR
VCOUT_SEL
BAL_6
CELL_SEL
BAL_5
I_THRESH
BAL_4
BAL_3
I_COMP_POL
I_AMP_CAL
I_AMP_EN
VC_AMP_EN
BAL_2
BAL_1
I_GAIN
REF_SEL
SLEEP_DIS
I_COMP_EN
VTB_EN
0x07
CHIP_ID
RO
0x08 – 0x0F
Reserved
R/W
0x10
VREF_CAL
EEPROM
VREF_OFFSET_CORR
VREF_GAIN_CORR
0x11
VC1_CAL
EEPROM
VC1_OFFSET_CORR
VC1_GAIN_CORR
0x12
VC2_CAL
EEPROM
VC2_OFFSET_CORR
VC2_GAIN_CORR
0x13
VC3_CAL
EEPROM
VC3_OFFSET_CORR
VC3_GAIN_CORR
0x14
VC4_CAL
EEPROM
VC4_OFFSET_CORR
VC4_GAIN_CORR
0x15
VC5_CAL
EEPROM
VC5_OFFSET_CORR
VC5_GAIN_CORR
0x16
VC6_CAL
EEPROM
VC6_OFFSET_CORR
0x17
VC_CAL_EXT_1
EEPROM
VC1_OC_4
VC1_GC_4
VC2_OC_4
VC2_GC_4
VC3_OC_4
VC3_GC_4
VC4_OC_4
VC4_GC_4
REF_EN
CHIP_ID
0x18
VC_CAL_EXT_2
EEPROM
0x10 – 0x1A
Reserved
EEPROM
0x1B
VREF_CAL_EXT
EEPROM
0x1C – 0x1F
Reserved
EEPROM
VC6_GAIN_CORR
VC5_OC_4
VC5_GC_4
VC6_OC_4
VC6_GC_4
1
VREF_OC_5
VREF_OC_4
VREF_GC_4
Register Descriptions
STATUS
Address
Name
Type
0x00
STATUS
R/W
D7
Defaults:
0
D6
D5
0
D4
0
0
D3
0
D2
D1
D0
ALERT
CRC_ERR
POR
0
0
1
ALERT : Over-current alert. Reflects state of the over-current comparator. ‘1’ = over-current.
CRC_ERR : CRC error status. Updated on every I2C write packet when CRC_EN = ‘1’. ‘1’ = CRC error.
POR : Power on reset flag. Set on each power-up and wake-up from sleep. May be cleared by writing with ‘0’.
CELL_CTL
Address
Name
Type
0x01
CELL_CTL
R/W
D7 (1)
D5
D4
D3
VCOUT_SEL
Defaults:
(1)
D6
0
0
D2
D1
D0
CELL_SEL
0
0
0
This bit must be kept = 0
VCOUT_SEL : VCOUT MUX select. Selects the VCOUT pin function as follows.
VCOUT_SEL
VCOUT
00
VSS
01
VCn (n determined by CELL_SEL)
10
VREF × 0.5
11
VREF × 0.85
CELL_SEL : Cell select. Selects the VCn input for output on VCOUT when VCOUT_SEL = ‘01’.
VCOUT_SEL
CELL_SEL
VCOUT
01
000
VC1
01
001
VC2
Copyright © 2011, Texas Instruments Incorporated
19
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
VCOUT_SEL
CELL_SEL
VCOUT
01
010
VC3
01
011
VC4
01
100
VC5
01
101
VC6
01
110
VTEMP,INT
01
111
Hi-Z
BAL_CTL
Address
Name
Type
0x02
BAL_CTL
R/W
Defaults:
D7
D6
0
0
D5
D4
D3
D2
D1
D0
BAL_6
BAL_5
BAL_4
BAL_3
BAL_2
BAL_1
0
0
0
0
0
0
BAL_n : Balance control for cell n. When set, turns on balancing transistor for cell n. Setting of two adjacent
balance controls is not permitted. If two adjacent balance controls are set, neither cell balancing transistor will be
turned on. However, the BAL_n bits will retain their values.
CONFIG_1
Address
Name
Type
0x03
CONFIG_1
R/W
D7
D6
D3
D2
I_THRESH
D5
I_COMP_POL
I_AMP_CAL
0
0
0
Defaults:
D4
D1
D0
I_GAIN
0
0
I_THRESH : Current comparator threshold. Sets the threshold of the current comparator as follows:
I_THRESH
Comparator threshold
0x0
25 mV
0x1
50 mV
0x2
75 mV
0x3
100 mV
0x4
125 mV
0x5
150 mV
0x6
175 mV
0x7
200 mV
0x8
225 mV
0x9
250 mV
0xA
275 mV
0xB
300 mV
0xC
325 mV
0xD
350 mV
0xE
375 mV
0xF
400 mV
I_COMP_POL : Current comparator polarity select. When ‘0’, trips on discharge current (SENSEP > SENSEN).
When ‘1’, trips on charge current (SENSEP < SENSEN).
I_AMP_CAL : Current amplifier calibration. When ‘0’, current amplifier reports SENSEN with respect to VSS.
When ‘1’, current amplifier reports SENSEP with respect to VSS. This bit can be used for offset cancellation as
described under OPERATIONAL OVERVIEW.
20
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
I_GAIN : Current amplifier gain. Sets the nominal gain of the current amplifier as follows.
I_GAIN
Current amp gain
0
4
1
8
CONFIG_2
Address
Name
Type
D7
0x04
CONFIG_2
R/W
CRC_EN
Defaults:
D6
D5
D4
D3
D2
D1
D0
REF_SEL
0
0
0
0
0
0
0
0
CRC_EN : CRC enable. Enables CRC comparison on write. When ‘1’, CRC is enabled. CRC on read is always
enabled but is optional for Host.
REF_SEL : Reference voltage selection. Sets reference voltage output on VREF pin, cell voltage amplifier gain
and VIOUT output range.
REF_SEL
VREF (V)
VCOUT Gain
VIOUT Output Range (V)
0
1.5
0.3
0.25 – 1.25
1
3.0
0.6
0.5 – 2.5
POWER_CTL
Address
Name
Type
D7
D6
0x05
POWER_CTL
R/W
SLEEP
SLEEP_DIS
0
0
Defaults:
D5
0
D4
D3
D2
D1
D0
I_COMP_EN
I_AMP_EN
VC_AMP_EN
VTB_EN
REF_EN
0
0
0
0
0
SLEEP : Sleep control. Set to ‘1’ to put device to sleep
SLEEP_DIS : Sleep mode disable. When ‘1’, disables the sleep mode.
I_COMP_EN : Current comparator enable. When ‘1’, comparator is enabled. Disable to save power.
I_AMP_EN : Current amplifier enable. When ‘1’, current amplifier is enabled. Disable to save power.
VC_AMP_EN : Cell amplifier enable. When ‘1’, cell amplifier is enabled. Disable to save power.
VTB_EN : Thermistor bias enable. When ‘1’, the VTB pin is internally switched to the V3P3 voltage.
REF_EN : Voltage reference enable. When ‘1’, the 1.5 / 3.0 V reference is enabled. Disable to save power
CHIP_ID
Address
Name
Type
0x07
CHIP_ID
RO
D7
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
CHIP_ID
Defaults:
0x10
CHIP_ID : Silicon version identifier.
VREF_CAL
Address
Name
Type
0x10
VREF_CAL
EEPROM
D7
D6
D5
VREF_OFFSET_CORR
D4
D3
VREF_GAIN_CORR
VREF_OFFSET_CORR : Lower 4 bits of offset correction factor for reference output. The complete offset
correction factor is obtained by concatenating this value with the the two most significant bits VREF_OC_5 and
VREF_OC_4, which are stored in the VREF_CAL_EXT register. The final value is a 6-bit signed 2’s complement
number in the range -32 to +31 with a value of 1 mV per lsb. See description of usage in OPERATIONAL
OVERVIEW.
Copyright © 2011, Texas Instruments Incorporated
21
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
VREF_GAIN_CORR : Lower 4 bits of gain correction factor for reference output. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VREF_GC_4, which is stored in the
VREF_CAL_EXT register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a
value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC1_CAL
Address
Name
Type
0x11
VC1_CAL
EEPROM
D7
D6
D5
D4
D3
VC1_OFFSET_CORR
D2
D1
D0
VC1_GAIN_CORR
VC1_OFFSET_CORR : Lower 4 bits of offset correction factor for cell 1 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC1_OC_4, which is stored
in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15
with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC1_GAIN_CORR : Lower 4 bits of gain correction factor for cell 1 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC1_GC_4, which is stored in the
VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a
value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC2_CAL
Address
Name
Type
0x12
VC2_CAL
EEPROM
D7
D6
D5
D4
D3
VC2_OFFSET_CORR
D2
D1
D0
VC2_GAIN_CORR
VC2_OFFSET_CORR : Lower 4 bits of offset correction factor for cell 2 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC2_OC_4, which is stored
in the VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15
with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC2_GAIN_CORR : Lower 4 bits of gain correction factor for cell 2 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC2_GC_4, which is stored in the
VC_CAL_EXT_1 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a
value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC3_CAL
Address
Name
Type
0x13
VC3_CAL
EEPROM
D7
D6
D5
VC3_OFFSET_CORR
D4
D3
D2
D1
D0
VC3_GAIN_CORR
VC3_OFFSET_CORR : Lower 4 bits of offset correction factor for cell 3 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC3_OC_4, which is stored
in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15
with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC3_GAIN_CORR : Lower 4 bits of gain correction factor for cell 3 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC3_GC_4, which is stored in the
VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a
value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.
22
Copyright © 2011, Texas Instruments Incorporated
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
VC4_CAL
Address
Name
Type
0x14
VC4_CAL
EEPROM
D7
D6
D5
D4
D3
D2
VC4_OFFSET_CORR
D1
D0
VC4_GAIN_CORR
VC4_OFFSET_CORR : Lower 4 bits of offset correction factor for cell 4 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC4_OC_4, which is stored
in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15
with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC4_GAIN_CORR : Lower 4 bits of gain correction factor for cell 4 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC4_GC_4, which is stored in the
VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a
value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC5_CAL
Address
Name
Type
0x15
VC5_CAL
EEPROM
D7
D6
D5
D4
D3
D2
VC5_OFFSET_CORR
D1
D0
VC5_GAIN_CORR
VC5_OFFSET_CORR : Lower 4 bits of offset correction factor for cell 5 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC5_OC_4, which is stored
in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15
with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC5_GAIN_CORR : Lower 4 bits of gain correction factor for cell 5 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC5_GC_4, which is stored in the
VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a
value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC6_CAL
Address
Name
Type
0x16
VC6_CAL
EEPROM
D7
D6
D5
D4
D3
D2
VC6_OFFSET_CORR
D1
D0
VC6_GAIN_CORR
VC6_OFFSET_CORR : Lower 4 bits of offset correction factor for cell 6 translation. The complete offset
correction factor is obtained by concatenating this value with the most significant bit VC6_OC_4, which is stored
in the VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15
with a value of 1 mV per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC6_GAIN_CORR : Lower 4 bits of gain correction factor for cell 6 translation. The complete gain correction
factor is obtained by concatenating this value with the most significant bit VC6_GC_4, which is stored in the
VC_CAL_EXT_2 register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a
value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.
VC_CAL_EXT_1
Address
Name
Type
D7
D6
D5
D4
0x17
VC_CAL_EXT_1
EEPROM
VC1_OC_4
VC1_GC_4
VC2_OC_4
VC2_GC_4
D3
D2
D1
D0
VC1_OC_4 : Most significant bit of offset correction factor for cell 1 translation. See VC1_CAL register
description for details.
VC1_GC_4 : Most significant bit of gain correction factor for cell 1 translation. See VC1_CAL register description
for details.
VC2_OC_4 : Most significant bit of offset correction factor for cell 2 translation. See VC2_CAL register
description for details.
VC2_GC_4 : Most significant bit of gain correction factor for cell 2 translation. See VC2_CAL register description
for details.
Copyright © 2011, Texas Instruments Incorporated
23
bq76925
SLUSAM9A – JULY 2011 – REVISED JULY 2011
www.ti.com
VC_CAL_EXT_2
Address
Name
Type
D7
D6
D5
D4
D3
D2
D1
D0
0x18
VC_CAL_EXT_2
EEPROM
VC3_OC_4
VC3_GC_4
VC4_OC_4
VC4_GC_4
VC5_OC_4
VC5_GC_4
VC6_OC_4
VC6_GC4
VC3_OC_4 : Most significant bit of offset correction factor for cell 3 translation. See VC3_CAL register
description for details.
VC3_GC_4 : Most significant bit of gain correction factor for cell 3 translation. See VC3_CAL register description
for details.
VC4_OC_4 : Most significant bit of offset correction factor for cell 4 translation. See VC4_CAL register
description for details.
VC4_GC_4 : Most significant bit of gain correction factor for cell 4 translation. See VC4_CAL register description
for details.
VC5_OC_4 : Most significant bit of offset correction factor for cell 5 translation. See VC5_CAL register
description for details.
VC5_GC_4 : Most significant bit of gain correction factor for cell 5 translation. See VC5_CAL register description
for details.
VC6_OC_4 : Most significant bit of offset correction factor for cell 6 translation. See VC6_CAL register
description for details.
VC6_GC_4 : Most significant bit of gain correction factor for cell 6 translation. See VC6_CAL register description
for details.
VREF_CAL_EXT
Address
Name
Type
0x1B
VREF_CAL_EXT
EEPROM
D7
D6
D5
D4
D3
D2
D1
D0
1
VREF_OC_5
VCREF_OC_4
VREF_GC4
VREF_OC_5 : Most significant bit of offset correction factor for reference output. See VREF_CAL register
description for details.
VREF_OC_4 : Next most significant bit of offset correction factor for reference output. See VREF_CAL register
description for details.
VREF_GC_4 : Most significant bit of gain correction factor for reference output. See VREF_CAL register
description for details.
24
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
BQ76925PW
ACTIVE
TSSOP
PW
20
1050
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ76925PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ76925PWR
Package Package Pins
Type Drawing
TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ76925PWR
TSSOP
PW
20
2000
346.0
346.0
33.0
Pack Materials-Page 2
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Wireless
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions
www.ti.com/lprf
TI E2E Community Home Page
e2e.ti.com
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