4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A SST31LF041 / 041A4Mb Flash (x8) + 1Mb SRAM (x8) Monolithic ComboMemory Preliminary Specifications FEATURES: • Monolithic Flash + SRAM ComboMemory – SST31LF041/041A: 512K x8 Flash + 128K x8 SRAM • Single 3.0-3.6V Read and Write Operations • Concurrent Operation – Read from or Write to SRAM while Erase/Program Flash • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 10 mA (typical) for Flash and 20 mA (typical) for SRAM Read – Standby Current: 10 µA (typical) • Flash Sector-Erase Capability – Uniform 4 KByte sectors • Latched Address and Data for Flash • Fast Read Access Times: – SST31LF041/041A Flash: 70 ns SRAM: 70 ns – SST31LF041A Flash: 300 ns SRAM: 300 ns • Flash Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Bank-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Bank Rewrite Time: 8 seconds (typical) • Flash Automatic Erase and Program Timing – Internal VPP Generation • Flash End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Packages Available – 32-lead TSOP (8mm x 14mm) SST31LF041A – 40-lead TSOP (10mm x 14mm) SST31LF041 PRODUCT DESCRIPTION The SST31LF041/041A devices are a 512K x8 CMOS flash memory bank combined with a 128K x8 CMOS SRAM memory bank manufactured with SST’s proprietary, high performance SuperFlash technology. The SST31LF041/041A devices write (SRAM or flash) with a 3.0-3.6V power supply. The monolithic SST31LF041/041A devices conform to Software Data Protect (SDP) commands for x8 EEPROMs. The SRAM bank enable signal, BES# selects the SRAM bank and the flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. Featuring high performance Byte-Program, the flash memory bank provides a maximum Byte-Program time of 20 µsec. The entire flash memory bank can be erased and programmed byte-by-byte in typically 8 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST31LF041/041A devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST31LF041/041A devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST31LF041/041A provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Byte-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. The SST31LF041/041A operate as two independent memory banks with respective bank enable signals. The SRAM and flash memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SST31LF041/041A devices are suited for applications that use both nonvolatile flash memory and volatile SRAM memory to store code or data. For all system applications, the SST31LF041/041A devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The ©2003 Silicon Storage Technology, Inc. S71107-05-000 12/03 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications SRAM Operation SST31LF041/041A inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The monolithic ComboMemory eliminates redundant functions when using two separate memories of similar architecture; therefore, reducing the total power consumption. With BES# low and BEF# high, the SST31LF041/041A operate as a 128K x8 CMOS SRAM with fully static operation requiring no external clocks or timing strobes. The SRAM is mapped into the first 128 KByte address space of the device for 041/041A. Read and Write cycle times are equal. SRAM Read The SRAM Read operation of the SST31LF041/041A are controlled by OE# and BES#, both have to be low with WE# high, for the system to obtain data from the outputs. BES# is used for SRAM bank selection. When BES# and BEF# are high, both memory banks are deselected. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 3 for the Read cycle timing diagram. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST31LF041/041A devices also improve flexibility by using a single package and a common set of signals to perform functions previously requiring two separate devices. To meet high density, surface mount requirements, the SST31LF041 device is offered in 40-lead TSOP package and the SST31LF041A device is offered in 32-lead TSOP package. See Figures 1 and 2 for the pinouts. SRAM Write The SRAM Write operation of the SST31LF041/041A is controlled by WE# and BES#; both have to be low for the system to write to the SRAM. BES# is used for SRAM bank selection. During the Byte-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The Write time is measured from the last falling edge to the first rising edge of BES# and WE#. OE# can be VIL or VIH, but no other value, for SRAM Write operations. See Figure 4 for the SRAM Write cycle timing diagram. Device Operation The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. Bus contention is eliminated as the monolithic device will not recognize both bank enables as being simultaneously active. If both bank enables are asserted (i.e., BEF# and BES# are both low), the BEF# will dominate while the BES# is ignored and the appropriate operation will be executed in the flash memory bank. SST does not recommend that both bank enables be simultaneously asserted. All other address, data, and control lines are shared which minimizes power consumption and area. The device goes into standby when both bank enables are raised to VIHC. See Table 3 for SRAM operation mode selection. Flash Operation With BEF# active, the SST31LF041/041A operate as a 512K x8 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and internally timed Erase and Program operations. See Table 3 for flash operation mode selection. For SST31LF041A only: BES# and OE# share pin 32. During SRAM operation, pin 32 will function as BES#. During flash operation, pin 32 will function as OE#. When pin 32 (OE#/BES#) is high, the data bus is in high impedance state. ©2003 Silicon Storage Technology, Inc. S71107-05-000 2 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications Flash Read sector address (SA) in the last bus cycle. The address lines A18-A12 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 10 for timing waveforms. Any SDP commands loaded during the Sector-Erase operation will be ignored. The Read operation of the SST31LF041/041A devices are controlled by BEF# and OE#; both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. See Figure 5 for the Read cycle timing diagram. Flash Bank-Erase Operation Flash Erase/Program Operation The SST31LF041/041A flash memory bank provides a Bank-Erase operation, which allows the user to erase the entire flash memory bank array to the ‘1’s state. This is useful when the entire bank must be quickly erased. The BankErase operation is initiated by executing a six-byte Software Data Protection command sequence with Bank-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or BEF# pulse, whichever occurs first. During the internal Erase operation, the only valid Flash Read operations are Toggle Bit and Data# Polling. See Table 4 for the command sequence, Figure 11 for timing diagram, and Figure 20 for the flowchart. Any SDP commands loaded during the Bank-Erase operation will be ignored. SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST31LF041/041A. SDP commands are loaded to the flash memory bank using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first. Flash Byte-Program Operation The flash memory bank of the SST31LF041/041A devices are programmed on a byte-by-byte basis. Before the Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid Flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Write Operation Status Detection The SST31LF041/041A flash memory bank provides two software means to detect the completion of a flash memory bank Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Sector-Erase Operation The Sector-Erase operation allows the system to erase the flash memory bank on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and ©2003 Silicon Storage Technology, Inc. S71107-05-000 3 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications Flash Data# Polling (DQ7) Flash Software Data Protection (SDP) When the SST31LF041/041A flash memory bank is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector or Bank-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart. The SST31LF041/041A provide the JEDEC approved Software Data Protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST31LF041/041A devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP commands will abort the device to the Read mode, within TRC. Concurrent Read and Write Operations The SST31LF041/041A provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. The device will ignore all SDP commands when an Erase or Program operation is in progress. This allows data alteration code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. SST does not recommend that both bank enables, BEF# and BES#, be simultaneously asserted. Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BE#) pulse for Program operation. For Sector or Bank-Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 18 for a flowchart. CONCURRENT READ/WRITE STATE TABLE Flash Memory Data Protection Flash SRAM Program/Erase Read Program/Erase Write Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. The SST31LF041/041A flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down. ©2003 Silicon Storage Technology, Inc. S71107-05-000 4 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications Product Identification Product Identification Mode Exit/Reset The Product Identification mode identifies the devices as either SST31LF041 or SST31LF041A and the manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware device ID Read operation is typically used by a programmer to identify the correct algorithm for the SST31LF041/041A flash memory banks. Users may wish to use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 12 for the software ID entry and read timing diagram and Figure 19 for the ID entry command sequence flowchart. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure 19 for a flowchart. Design Considerations SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. TABLE 1: PRODUCT IDENTIFICATION Address Data 0000H BFH SST31LF041 0001H 17H SST31LF041A 0001H 16H Manufacturer’s ID Device ID T1.2 1107 FUNCTIONAL BLOCK DIAGRAM Address Buffers AMS - A0 BES# BEF# OE# WE# SRAM Address Buffers & Latches DQ7 - DQ0 I/O Buffers Control Logic SuperFlash Memory 1107 B1.6 AMS = Most Significant Address ©2003 Silicon Storage Technology, Inc. S71107-05-000 5 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications A16 A15 A14 A13 A12 A11 A9 A8 WE# NC BES# NC A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS BEF# A0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Standard Pinout Top View Die Up 1107 40-tsop P1.2 FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP (10MM A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X Standard Pinout Top View Die Up 14MM) - SSTLF041 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE#/BES# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1107 32-tsop P2.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM ©2003 Silicon Storage Technology, Inc. X 14MM) - SSTLF041A S71107-05-000 6 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. A18-A0 to provide flash address A16-A0 to provide SRAM addresses for SST32LF041/041A During flash Sector-Erase, A18-A12 address lines will select the sector. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. Note: For SST31LF041A, BES# and OE# share pin 32. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low. OE# Output Enable To gate the data output buffers. Note: For SST31LF041A, BES# and OE# share pin 32. WE# Write Enable To control the Write operations. VDD Power Supply 3.0-3.6V Power Supply VSS Ground T2.11 1107 1. AMS = Most significant address ©2003 Silicon Storage Technology, Inc. S71107-05-000 7 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications TABLE 3: OPERATION MODES SELECTION BES#1 BEF#1 Read X2 Program X Erase Mode OE# WE# A9 DQ Address VIL VIL VIH AIN DOUT AIN VIL VIH VIL AIN DIN AIN X VIL VIH VIL X X Sector address, XXH for Bank-Erase Read VIL VIH VIL VIH AIN DOUT AIN Write VIL VIH X VIL AIN DIN AIN VIHC VIHC X X X High Z X X X VIL X X High Z / DOUT X X X X VIH X High Z / DOUT X X VIH X X X High Z / DOUT X Hardware Mode X VIL VIL VIH VH Manufacturer’s ID (BFH) Device ID3 A18-A1=VIL, A0=VIL A18-A1=VIL, A0=VIH Software Mode X VIL VIL VIH AIN ID Code See Table 4 Flash SRAM Standby Flash Write Inhibit Product Identification T3.9 1107 1. BES# and BEF# cannot be asserted simultaneously. For SST31LF041A BES# and OE# share pin 32. When flash is active, pin 32 becomes OE#. When flash is inactive, pin 32 becomes BES#. 2. X can be VIL or VIH, but no other value. 3. Device ID 17H for SST31LF041 and 16H for SST31LF041A. TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle 2nd Bus Write Cycle 3rd Bus Write Cycle 4th Bus Write Cycle Addr1 Data Addr1 Data Addr1 Data Addr1 Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H Bank-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H F0H Software ID Entry4,5 Software ID Exit 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data AAH 2AAAH 55H SAX3 30H AAH 2AAAH 55H 5555H 10H T4.7 1107 1. 2. 3. 4. 5. Address format A14-A0 (Hex), Address A18-A15 can be VIL or VIH, but no other value, for the Command sequence. BA = Program Byte address SAX for Sector-Erase; uses A18-A12 address lines The device does not remain in Software Product ID mode if powered down. With A18-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0, SST31LF041 Device ID = 17H, is read with A0 = 1, SST31LF041A Device ID = 16H, is read with A0 = 1 ©2003 Silicon Storage Technology, Inc. S71107-05-000 8 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD+1.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial Extended AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Ambient Temp VDD 0°C to +70°C 3.0-3.6V Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF -20°C to +85°C 3.0-3.6V See Figures 15 and 16 ©2003 Silicon Storage Technology, Inc. S71107-05-000 9 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications TABLE 5: DC OPERATING CHARACTERISTICS (VDD = 3.0-3.6V) Limits Symbol Parameter IDD Power Supply Current Min Max Units Address input = VILT/VIHT, at f=1/TRC Min, VDD=VDD Max, all DQs open Read OE#=VIL, WE#=VIH Flash 12 mA BEF#=VIL, BES#=VIH SRAM 40 mA BEF#=VIH, BES#=VIL 55 mA Concurrent Operation Write ISB 1 Test Conditions BEF#=VIH, BES#=VIL OE#=VIH, WE#=VIL Flash (Program) 15 mA BEF#=VIL, BES#=VIH SRAM 40 mA BEF#=VIH, BES#=VIL Standby VDD Current 30 µA BEF#=BES#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max 1 µA VOUT=GND to VDD, VDD=VDD Max 0.4 V VDD=VDD Min ILO Output Leakage Current VIL Input Low Voltage VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min VOL Output Low Voltage VOH Output High Voltage VH Supervoltage for A9 pin IH Supervoltage Current for A9 pin 0.2 VDD-0.2 11.4 12.6 V BEF#=OE#=VIL, WE#=VIH 200 µA BEF#=OE#=VIL, WE#=VIH, A9=VH Max T5.15 1107 1. Specification applies to commercial temperature devices only. This parameter may be higher for extended devices. TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 µs Power-up to Write Operation 100 µs T6.2 1107 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF CIN 1 T7.2 1107 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T8.4 1107 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71107-05-000 10 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications AC CHARACTERISTICS TABLE 9: SRAM MEMORY BANK CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) SST31LF041/041A-70 Symbol Parameter Min Max 70 SST31LF041A-300 Min Max Units 300 ns TRCS Read Cycle Time TBES Bank Enable Access Time 70 300 TAAS Address Access Time 70 300 ns TOES1 Output Enable Access Time 35 150 ns TBLZS2 BES# to Active Output 0 0 ns TOLZS1 Output Enable to Active Output 0 0 ns TBHZS1 BES# to High-Z Output 25 30 ns TOHZS1 Output Disable to High-Z Output 25 30 ns TOHS Output Hold from Address Change 0 ns 10 ns T9.8 1107 1. No TOES value for SST31LF041A 2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) SST31LF041/041A-70 Min Max SST31LF041A-300 Symbol Parameter TWCS Write Cycle Time 70 Min 300 Max Unit ns TBWS Bank Enable to End-of-Write 60 230 ns TAWS Address Valid to End-of-Write 60 230 ns TASTS Address Set-up Time 0 0 ns TWPS Write Pulse Width 60 200 ns TWRS Write Recovery Time 0 0 ns TDSS Data Set-up Time 30 150 ns TDHS Data Hold from Write Time 0 0 ns T10.5 1107 TABLE 11: FLASH READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) SST31LF041/041A-70 Min Symbol Parameter TRC Read Cycle Time TBE Bank Enable Access Time 70 300 ns TAA Address Access Time 70 300 ns TOE Output Enable Access Time 150 ns TBLZ1 BEF# Low to Active Output 0 TOLZ1 TBHZ1 TOHZ1 TOH1 OE# Low to Active Output 0 70 Min ns 0 ns 60 15 0 Units ns 0 15 OE# High to High-Z Output Max 300 40 BEF# High to High-Z Output Output Hold from Address Change Max SST31LF041A-300 60 0 ns ns ns T11.5 1107 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2003 Silicon Storage Technology, Inc. S71107-05-000 11 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V) SST31LF041/041A-70 Min Max SST31LF041A-300 Symbol Parameter TBP Byte-Program Time Min TAS Address Setup Time 0 0 ns TAH Address Hold Time 30 50 ns TBS WE# and BEF# Setup Time 0 0 ns TBH WE# and BEF# Hold Time 0 0 ns TOES OE# High Setup Time 0 0 ns TOEH OE# High Hold Time 10 10 ns TBP BEF# Pulse Width 40 100 ns TWP WE# Pulse Width 40 100 ns TWPH WE# Pulse Width High 30 50 ns TBPH BEF# Pulse Width High 30 50 ns TDS Data Setup Time 40 50 ns TDH Data Hold Time 0 0 ns TIDA Software ID Access and Exit Time 150 150 ns TSE Sector-Erase 25 25 ms TSBE Bank-Erase 100 ms TBS Bank Enable Setup Time for Concurrent Operation 20 100 0 Max Units 20 µs 0 ns T12.4 1107 ©2003 Silicon Storage Technology, Inc. S71107-05-000 12 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications TAAS TRCS ADDRESS A16-0 BEF# TBES BES#1 OE# TOHZS TOES 1 VIH TOLZS WE# HIGH-Z DQ7-0 TBHZS TOHS TBLZS DATA VALID HIGH-Z DATA VALID Note 1: For SST31LF041A. BES# and OE# share pin 32. During SRAM operation, pin 32 functions as BES#. 1107 F02.10 FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM TWCS ADDRESS A16-0 ADDRESS BEF# TBWS 1 BES# TAWS OE# 1 TWPS TWRS WE# TASTS TDSS TDHS DATA VALID DQ7-0 Note 1: For SST31LF041A. BES# and OE# share pin 32. During SRAM operation, pin 32 functions as BES#. 1107 F03.11 FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71107-05-000 13 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications TRC TAA ADDRESS A18-0 1 BES# TBE BEF# TOE OE#1 TOLZ VIH TOHZ WE# HIGH-Z DQ7-0 TBHZ TOH TBLZ HIGH-Z DATA VALID DATA VALID 1107 F18.6 Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS A18-0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH 1 OE# BES#1 TCH BEF# TCS DQ7-0 AA SW0 55 A0 DATA SW1 SW2 BYTE (ADDR/DATA) 1107 F04.7 Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71107-05-000 14 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS A18-0 BES# 2AAA 5555 ADDR 1 TAH TDH TCP BEF# TAS TDS TCPH OE#1 TCH WE# TCS DQ7-0 AA SW0 55 A0 SW1 SW2 DATA BYTE (ADDR/DATA) 1107 F05.7 Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM ADDRESS A18-0 1 BES# TCE BEF# TOES TOEH OE#1 TOE WE# DQ7 D D# D# D 1107 F06.7 Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71107-05-000 15 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications ADDRESS A18-0 1 BES# TBE BEF# OE# TOES TOE TOEH 1 WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 1107 F07.7 Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A18-0 5555 2AAA 5555 5555 2AAA SAX BES#1 BEF# OE#1 TWP WE# DQ7-0 AA 55 80 AA 55 30 SW0 SW1 SW2 SW3 SW4 SW5 1107 F08.9 Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) SAX = Sector Address Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 10: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM ©2003 Silicon Storage Technology, Inc. S71107-05-000 16 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications TSBE SIX-BYTE CODE FOR BANK-ERASE 5555 ADDRESS A18-0 2AAA 5555 5555 2AAA 5555 BES#1 BEF# OE#1 TWP WE# DQ7-0 AA 55 SW0 SW1 80 AA 55 10 SW2 SW3 SW4 SW5 1107 F17.9 Note: The device also supports BEF# controlled Bank-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 12) Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 11: WE# CONTROLLED FLASH BANK-ERASE TIMING DIAGRAM THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY 5555 ADDRESS A14-0 BES# 2AAA 5555 0000 0001 1 BEF# OE# 1 TIDA TWP WE# TWPH DQ7-0 TAA AA 55 90 SW0 SW1 SW2 BF Device ID 1107 F09.8 Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. Note: Device ID = 16H for SST31LF041A and 17H for SST31LF041. FIGURE 12: FLASH SOFTWARE ID ENTRY AND READ ©2003 Silicon Storage Technology, Inc. S71107-05-000 17 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A14-0 2AAA 5555 BES#1 DQ7-0 AA 55 F0 TIDA BEF# OE#1 TWP WE# T WHP SW0 SW1 1107 F10.8 SW2 Note 1. For SST31LF041A, BES# and OE# share pin 32. During Flash operation, pin 32 functions as OE#. FIGURE 13: FLASH SOFTWARE ID EXIT AND RESET ADDRESS A18-0 BEj# TBS BEj1# WE# OE# DQ7-0 1107 F22.0 Note: j = F or S j1 = S or F FIGURE 14: TIMING DIAGRAM FOR ALTERNATING BETWEEN ©2003 Silicon Storage Technology, Inc. FLASH/SRAM AND SRAM/FLASH S71107-05-000 18 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1107 F11.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 15: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1107 F12.2 FIGURE 16: A TEST LOAD EXAMPLE ©2003 Silicon Storage Technology, Inc. S71107-05-000 19 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1107 F13.2 FIGURE 17: BYTE-PROGRAM ALGORITHM ©2003 Silicon Storage Technology, Inc. S71107-05-000 20 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications Internal Timer Toggle Bit Data# Polling Byte Program/Erase Initiated Byte Program/Erase Initiated Byte Program/Erase Initiated Read byte Read DQ7 Wait TBP, TSBE, or TSE Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1107 F14.0 FIGURE 18: WAIT OPTIONS ©2003 Silicon Storage Technology, Inc. S71107-05-000 21 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 1107 F15.2 FIGURE 19: SOFTWARE PRODUCT COMMAND FLOWCHARTS ©2003 Silicon Storage Technology, Inc. S71107-05-000 22 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications Chip-Erase Command Sequence Sector-Erase Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: 30H Address: SAX Wait TSBE Wait TSE Chip erased to FFH Sector erased to FFH 1107 F16.2 FIGURE 20: ERASE COMMAND SEQUENCE ©2003 Silicon Storage Technology, Inc. S71107-05-000 23 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications PRODUCT ORDERING INFORMATION Device Speed SST31LF04xx - XXX Suffix1 - XX Suffix2 - XX Package Modifier H = 32 leads I = 40 leads Package Type W = TSOP (type 1, die up, 8mm x 14mm) (type 1, die up, 10mm x 14mm) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 300 = 300 ns Version A = 32-lead TSOP Package Density 041 = 4 Mbit Flash + 1 Mbit SRAM Voltage L = 3.0-3.6V Product Series 31 = Monolithic ComboMemory Valid combinations for SST31LF041 SST31LF041-70-4C-WI SST31LF041-70-4E-WI Valid combinations for SST31LF041A SST31LF041A-70-4C-WH SST31LF041A-300-4C-WH SST31LF041A-70-4E-WH SST31LF041A-300-4E-WH Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2003 Silicon Storage Technology, Inc. S71107-05-000 24 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0˚- 5˚ 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH X ©2003 Silicon Storage Technology, Inc. 32-tsop-WH-7 14MM S71107-05-000 25 12/03 4 Mbit Flash + 1 Mbit SRAM ComboMemory SST31LF041 / SST31LF041A Preliminary Specifications 1.05 0.95 Pin # 1 Identifier 0.50 BSC 0.27 0.17 10.10 9.90 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0˚- 5˚ 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 CA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 1mm 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 10MM SST PACKAGE CODE: WI X 40-tsop-WI-7 14MM TABLE 13: REVISION HISTORY Number Description Date 03 • 2002 Data Book Feb 2002 04 • • • Removed the 256 SRAM parts (SST31LF043/043A) and associated MPNs Corrected the Test Conditions for IDD in Table 5 on page 10 Added Revision History Sep 2003 05 • 2004 Data Book Dec 2003 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2003 Silicon Storage Technology, Inc. S71107-05-000 26 12/03