Cypress CY7C1046DV33 4-mbit (1 m ã 4) static ram Datasheet

CY7C1046DV33
4-Mbit (1 M × 4) Static RAM
4-Mbit (1 M × 4) Static RAM
Features
Functional Description
The CY7C1046DV33[1] is a high-performance CMOS static
RAM organized as 1M words by 4 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0
through I/O3) is then written into the location specified on the
address pins (A0 through A19).
■
Pin- and function-compatible with CY7C1046CV33
■
High speed
❐ tAA = 10 ns
■
Low active power
❐ ICC = 90 mA @ 10 ns
■
Low CMOS standby power
❐ ISB2 = 10 mA
■
2.0 V data retention
■
Automatic power-down when deselected
■
TTL-compatible inputs and outputs
■
Easy memory expansion with CE and OE features
■
Available in lead-free 400-mil-wide 32-pin SOJ package
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1046DV33 is available in a standard 400-mil-wide
32-pin SOJ package with center power and ground
(revolutionary) pinout.
Logic Block Diagram
INPUT BUFFER
I/O0
1 Mbit x 4
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
I/O1
I/O2
I/O3
COLUMN
DECODER
CE
POWER
DOWN
A 11
A 12
A 13
A14
A15
A16
A17
A18
A19
WE
OE
Note
1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05611 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 2, 2010
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CY7C1046DV33
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
AC Test Loads and Waveforms ....................................... 5
AC Switching Characteristics ......................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Waveforms ...................................................... 7
Read Cycle No. 1 ........................................................ 7
Read Cycle No. 2 (OE Controlled) .............................. 7
Write Cycle No. 1 (CE Controlled) ............................... 8
Document Number: 38-05611 Rev. *D
Write Cycle No. 2 (WE Controlled,
OE HIGH During Write) ...................................................... 8
Write Cycle No. 3 (WE Controlled, OE LOW) ............. 9
Truth Table ........................................................................ 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagram ............................................................ 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
Page 2 of 14
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CY7C1046DV33
Selection Guide
–10
10
90
10
Maximum access time
Maximum operating current
Maximum CMOS standby current
Unit
ns
mA
mA
Pin Configuration
SOJ
Top View
A0
A1
A2
A3
A4
CE
I/O0
VCC
GND
I/O1
WE
A5
A6
A7
A8
A9
Document Number: 38-05611 Rev. *D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A19
A18
A17
A16
A15
OE
I/O3
GND
VCC
I/O2
A14
A13
A12
A11
A10
NC
Page 3 of 14
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CY7C1046DV33
DC input voltage[2] ............................... –0.3 V to VCC + 0.3 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, method 3015)
Latch-up current ..................................................... > 200 mA
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Operating Range
Supply voltage on VCC to relative GND[2] ........ –0.3 to +4.6 V
Range
DC voltage applied to outputs
in high Z State[2] .................................. –0.3 V to VCC + 0.3 V
Ambient Temperature
VCC
–40 °C to +85 °C
3.3 V + 0.3 V
Industrial
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW voltage
VCC = Min, IOL = 8.0 mA
VIH
Input HIGH voltage
voltage[2]
–10
Unit
Min
Max
2.4
–
V
–
0.4
V
2.0
VCC + 0.3
V
VIL
Input LOW
–0.3
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, output disabled
–1
+1
A
ICC
VCC operating supply current
VCC = Max, f = fMAX = 1/tRC 100 MHz
–
90
mA
83 MHz
–
80
66 MHz
–
70
40 MHz
–
60
mA
ISB1
Automatic CE Power-Down
Current —TTL inputs
Max VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
–
20
mA
ISB2
Automatic CE Power-Down
Current —CMOS inputs
Max VCC, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0
–
10
mA
Max
Unit
8
pF
8
pF
Capacitance[3]
Parameter
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Thermal Resistance[3]
Parameter
Description
JA
Thermal resistance (Junction to Ambient)
JC
Thermal resistance (Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
SOJ Package
Unit
53.44
°C/W
38.25
°C/W
Notes
2. VIL (min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05611 Rev. *D
Page 4 of 14
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CY7C1046DV33
AC Test Loads and Waveforms[4]
Z=50 
50 
* capacitive load consists
of all components of the
test environment
High Z characteristics:
3.3 V
ALL INPUT PULSES
3.0 V
OUTPUT
1.5 V
(a)
30 pF*
GND
90%
90%
10%
10%
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
R 317 
OUTPUT
5 pF
(c)
R2
351
Note
4. AC characteristics (except high Z) are tested using the load conditions shown in (a). High Z characteristics are tested for all speeds using the test load
shown in (c).
Document Number: 38-05611 Rev. *D
Page 5 of 14
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CY7C1046DV33
AC Switching Characteristics
Over the Operating Range[5]
Parameter
Description
–10
Min
Max
Unit
Read Cycle
tpower[6]
VCC(typical) to the first access
100
–
s
tRC
Read cycle time
10
–
ns
tAA
Address to data valid
–
10
ns
tOHA
Data hold from address change
3
–
ns
tACE
CE LOW to data valid
–
10
ns
tDOE
OE LOW to data valid
–
5
ns
0
–
ns
–
5
ns
3
–
ns
[8]
tLZOE
OE LOW to low Z
tHZOE
OE HIGH to high Z[7, 8]
tLZCE
CE LOW to low
Z[8]
Z[7, 8]
tHZCE
CE HIGH to high
–
5
ns
tPU
CE LOW to power-up
0
–
ns
CE HIGH to power-down
–
10
ns
tWC
Write cycle time
10
–
ns
tSCE
CE LOW to write end
7
–
ns
tPD
Write
Cycle[9, 10]
tAW
Address set-up to write end
7
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address set-up to write start
0
–
ns
tPWE
WE pulse width
7
–
ns
tSD
Data set-up to write end
5
–
ns
tHD
Data hold from write end
0
–
ns
[8]
tLZWE
WE HIGH to low Z
3
–
ns
tHZWE
WE LOW to high Z[7, 8]
–
5
ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high
impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either
of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05611 Rev. *D
Page 6 of 14
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CY7C1046DV33
Data Retention Characteristics
Over the Operating Range
Parameter
Conditions[11]
Description
VDR
VCC for data retention
ICCDR
Data retention current
tCDR[12]
Chip deselect to data retention time
tR[13]
Operation recovery time
Min
VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
Max
Unit
2.0
–
V
–
10
mA
0
–
ns
tRC
–
ns
Data Retention Waveform
DATA RETENTION MODE
3.0 V
VCC
3.0 V
VDR > 2 V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[14, 15]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
11. No inputs may exceed VCC + 0.3 V.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
14. Device is continuously selected. OE, CE = VIL.
15. WE is HIGH for Read cycle.
16. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05611 Rev. *D
Page 7 of 14
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CY7C1046DV33
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[17, 18]
tWC
ADDRESS
tSCE
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[17, 18]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 19
tHZOE
Notes
17. Data I/O is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 38-05611 Rev. *D
Page 8 of 14
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CY7C1046DV33
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[20]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tSD
NOTE 21
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE
OE
WE
I/O0 – I/O3
Mode
Power
H
X
X
High Z
Power-down
L
L
H
Data out
Read
Active (ICC)
L
X
L
Data in
Write
Active (ICC)
L
H
H
High Z
Selected, outputs disabled
Active (ICC)
Standby (ISB)
Notes
20. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
21. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 38-05611 Rev. *D
Page 9 of 14
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CY7C1046DV33
Ordering Information
Speed
(ns)
10
Ordering Code
CY7C1046DV33-10VXI
Package
Diagram
51-85033
Package Type
32-lead (400-mil) Molded SOJ (Pb-free)
Operating
Range
Industrial
Ordering Code Definitions
CY 7 C 1 04 6
D V33 - 10 VX
I
Temperature Range:
I = Industrial
Package Type:
VX = 32-pin (400-Mil) Molded SOJ (Pb-free)
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
6 = Data width × 4-bits
04 = 4-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Please contact your local Cypress sales representative for availability of these parts.
Document Number: 38-05611 Rev. *D
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CY7C1046DV33
Package Diagram
32-pin (400-Mil) Molded SOJ (51-85033)
51-85033 *C
Document Number: 38-05611 Rev. *D
Page 11 of 14
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CY7C1046DV33
Acronyms
Document Conventions
Acronym
Description
CMOS
complementary metal oxide semiconductor
CE
chip enable
I/O
input/output
OE
output enable
SOJ
small outline J-lead
SRAM
static random access memory
TTL
transistor-transistor logic
WE
write enable
Document Number: 38-05611 Rev. *D
Units of Measure
Symbol
Unit of Measure
ns
nano seconds
V
Volts
µA
micro Amperes
µs
micro seconds
mA
milli Amperes
MHz
Mega Hertz
pF
pico Farad
°C
degree Celcius
W
Watts
%
percent
Page 12 of 14
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CY7C1046DV33
Document History Page
Document Title: CY7C1046DV33 4-Mbit (1 M × 4) Static RAM
Document Number: 38-05611
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
307613
See ECN
RKF
New data sheet
*A
397134
See ECN
RXU
Changed from Advance to Preliminary
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed -15 Speed bin
Corrected DC voltage limits in maximum ratings section from - 0.5 to
- 0.3V and VCC + 0.5V to VCC + 0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 100, 80 and 70 mA to 90, 80 and 75 mA for 8, 10
and 12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 70 mA to 90 and 85 mA for 10 and 12ns
speed bins respectively
Removed footnote on rise time and added footnote on Operation Recovery
Time (tR)
Corrected Typo in Truth Table from (I/O0 - I/O7) to (I/O0 to I/O3)
Changed part names from V33 to V32 in the Ordering Information Table
Removed L-Version
Added Lead-Free Product Information
Shaded Ordering Information Table
*B
459072
See ECN
NXR
Converted from Preliminary to Final
Removed -8 and -12 speed bins
Removed Commercial Operating Range product information
Removed the PIn Definition table
Changed the Capacitance value of input pins and I/O pins from 6 pF to 8 pF
Updated the Thermal Resistance table
Updated footnote #7 on High-Z parameter measurement
Added footnote #11
Replaced Package Name column with Package Diagram in the Ordering
Information table
*C
3059211
10/14/2010
PRAS
Added Ordering Code Definitions.
Updated Package Diagram.
*D
3100106
12/02/2010
PRAS
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
Document Number: 38-05611 Rev. *D
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CY7C1046DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2005-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05611 Rev. *D
Revised December 2, 2010
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