Cypress CY62157DV30 8-mbit (512k x 16) mobl static ram Datasheet

CY62157DV30 MoBL®
8-Mbit (512K x 16) MoBL® Static RAM
Functional Description[1]
Features
• Temperature Ranges
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH and WE LOW).
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62157CV25, CY62157CV30, and
CY62157CV33
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = fmax
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
• Ultra-low standby power
• Easy memory expansion with CE1, CE2, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball FBGA,
44-pin TSOPII, and Pb-free 48-pin TSOPI
Logic Block Diagram
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table for a complete description
of read and write modes.
512K × 16
RAM Array
SENSE AMPS
ROW DECODER
DATA-IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A11
A12
A13
A14
A15
A16
A17
A18
BHE
WE
OE
CE2
CE1
BLE
Power-down
Circuit
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05392 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 8, 2006
CY62157DV30 MoBL®
Product Portfolio
Power Dissipation
Operating ICC, (mA)
VCC Range (V)
f = 1MHz
f = fmax
Standby ISB2,
(µA)
Min.
Typ.[2]
Max.
Speed
(ns)
Typ.[2]
Max.
Typ.[2]
Max.
Typ.[2]
Max.
Industrial
2.2
3.0
3.6
45, 55, 70
1.5
3
12
20
2
20
CY62157DV30LL Industrial
2.2
3.0
3.6
45, 55, 70
1.5
3
12
15
2
8
CY62157DV30LL Automotive-A
2.2
3.0
3.6
55
1.5
3
12
15
2
8
CY62157DV30L
2.2
3.0
3.6
55
1.5
3
12
20
2
50
Product
Range
CY62157DV30L
Automotive-E
Pin Configuration[4, 5, 6]
48-Pin TSOP I Pinout
Top View
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Ball FBGA Pinout
44-pin TSOP II Pinout
Top View
Top View
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
A7
I/O3
Vcc
D
I/O12 DNU
A16
I/O4
Vss
E
I/O14 I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
VSS
I/O11
VCC
A17
A16
BYTE
Vss
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
NC
H
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
3. NC pins are not internally connected on the die.
4. DNU pins have to be left floating.
5. The BYTE pin in the 48-TSOPI package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOPI package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. For 1M × 8 Functionality, please refer to the CY62158DV30 datasheet. In the 1M × 8 configuration, Pin 45 is A19, while
BHE, BLE and I/O8 to I/O14 pins are not used.
6. The 44-TSOPII package device has only one chip enable pin (CE).
Document #: 38-05392 Rev. *H
Page 2 of 12
CY62157DV30 MoBL®
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current...................................................... >200 mA
Storage Temperature ................................ –65°C to + 150°C
Operating Range
Ambient Temperature with
Power Applied............................................ –55°C to + 125°C
Supply Voltage to Ground
Potential ............................................ –0.3V to VCC(max) + 0.3V
DC Voltage Applied to Outputs
in High-Z State[8, 9] ............................ –0.3V to VCC(max) + 0.3V
DC Input Voltage[8, 9] ........................–0.3V to VCC(max) + 0.3V
Device
Range
Ambient
Temperature
(TA)
CY62157DV30L
Industrial
–40°C to +85°C
VCC[10]
2.20V
to
3.60V
CY62157DV30LL
CY62157DV30LL Automotive-A –40°C to +85°C
CY62157DV30L
Automotive-E –40°C to +125°C
Output Current into Outputs (LOW) .............................20 mA
Electrical Characteristics Over the Operating Range
-45, -55, -70
Parameter
Description
Min. Typ.[2]
Test Conditions
VOH
Output HIGH
Voltage
IOH = –0.1 mA
VCC = 2.20V
2.0
IOH = –1.0 mA
VCC = 2.70V
2.4
VOL
Output LOW
Voltage
IOL = 0.1 mA
VCC = 2.20V
IOL = 2.1 mA
VCC = 2.70V
VIH
Input HIGH
Voltage
VCC = 2.2V to 2.7V
VIL
Input LOW
Voltage
IIX
IOZ
ICC
Input Leakage
Current
VCC Operating
Supply Current
V
V
0.4
0.4
V
V
VCC= 2.7V to 3.6V
2.2
VCC + 0.3
V
VCC = 2.2V to 2.7V
–0.3
0.6
V
VCC= 2.7V to 3.6V
–0.3
0.8
V
Ind’l/Auto-A[7]
–1
+1
µA
Auto-E[7]
–4
+4
µA
Ind’l/Auto-A[7]
–1
+1
µA
Auto-E[7]
VCC = VCCmax L
IOUT = 0 mA LL
CMOS levels
L
–4
+4
µA
12
20
mA
12
15
mA
GND < VO < VCC, Output Disabled
f = fMAX = 1/tRC
LL
ISB2
V
VCC + 0.3
f = 1 MHz
ISB1
Unit
1.8
GND < VI < VCC
Output Leakage
Current
Max.
Automatic CE
Power-Down
Current — CMOS
Inputs
L
CE1 > VCC − 0.2V, CE2 < 0.2V
Ind’l
VIN > VCC – 0.2V, VIN < 0.2V)
[7] LL
f = fMAX (Address and Data Only), f = 0 Ind’l/Auto-A
(OE, WE, BHE and BLE), VCC = 3.60V Auto-E[7]
L
Automatic CE
Power-Down
Current -CMOS
Inputs
CE1 > VCC– 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
Ind’l[7]
1.5
3
mA
1.5
3
mA
µA
2
20
2
8
2
20
2
8
50
L
Ind’l/Auto-A[7] LL
Auto-E[7]
L
µA
50
Capacitance[11, 12]
Parameter
CIN
Description
Input Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
Unit
10
pF
COUT
Output Capacitance
10
Notes:
7. Automotive-A and Automotive-E available only in -55.
8. VIL(min.) = –2.0V for pulse durations less than 20 ns.
9. VIH(max)= VCC+0.75V for pulse duration less than 20 ns.
10. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
11. Tested initially and after any design or process changes that may affect these parameters.
12. The input capacitance on the CE2 pin of the FBGA and 48TSOPI packages and on the BHE pin of the 44TSOPII package is 15 pF.
Document #: 38-05392 Rev. *H
pF
Page 3 of 12
CY62157DV30 MoBL®
Thermal Resistance[11]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
FBGA
TSOP II
TSOP I
Unit
39.3
35.62
36.9
°C/W
9.69
9.13
10.05
°C/W
AC Test Loads and Waveforms[13]
R1
VCC
OUTPUT
30 pF / 50 pF
VCC
GND
10%
ALL INPUT PULSES
90%
90%
10%
R2
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
2.50V
3.0V
Unit
R1
16667
1103
Ω
R2
15385
1554
Ω
RTH
8000
645
Ω
VTH
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
[11]
Conditions
Min.
Max.
1.5
VCC= 1.5V
CE1 > VCC – 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Ind’l (L)
10
4
Auto-E (L)
25
Operation Recovery Time
Unit
V
Ind’l/Auto-A (LL)
Chip Deselect to Data
Retention Time
tR[14]
Typ.[2]
µA
0
ns
tRC
ns
Data Retention Waveform[15]
VCC
VCC, min.
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC, min.
tR
CE1 or
BHE.BLE
or
CE2
Notes:
13. Test condition for the 45 ns part is a load capacitance of 30 pF.
14. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
Document #: 38-05392 Rev. *H
Page 4 of 12
CY62157DV30 MoBL®
Switching Characteristics Over the Operating Range [16]
45 ns[13]
Parameter
Description
Min.
Max.
55 ns
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
45
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
45
55
70
ns
tDOE
OE LOW to Data Valid
25
25
35
ns
tLZOE
OE LOW to LOW Z[17]
45
10
OE HIGH to High Z
tLZCE
CE1 LOW and CE2 HIGH to Low Z
tHZCE
CE1 HIGH and CE2 LOW to High Z[17, 18]
tPU
CE1 LOW and CE2 HIGH to Power-Up
tPD
CE1 HIGH and CE2 LOW to Power-Down
tDBE
BLE/BHE LOW to Data Valid
tLZBE
BLE/BHE LOW to Low Z[17]
BLE/BHE HIGH to HIGH
tHZBE
Write Cycle
55
10
0
45
Z[17, 18]
55
10
15
25
ns
25
ns
ns
0
55
45
10
ns
10
20
ns
70
ns
70
ns
10
20
ns
ns
5
10
0
70
20
20
ns
10
5
15
[17]
70
10
5
[17, 18]
tHZOE
55
ns
25
ns
[19]
tWC
Write Cycle Time
45
55
70
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
40
40
60
ns
tAW
Address Set-up to Write End
40
40
60
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
35
40
45
ns
tBW
BLE/BHE LOW to Write End
40
40
60
ns
tSD
Data Set-up to Write End
25
25
30
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[17, 18]
tLZWE
[17]
WE HIGH to Low-Z
0
15
10
0
20
10
ns
25
10
ns
ns
Notes:
15. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
19. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write.
Document #: 38-05392 Rev. *H
Page 5 of 12
CY62157DV30 MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[20, 21]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle 2 (OE Controlled)[21, 22]
ADDRESS
tRC
CE1
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
DATA OUT
tDOE
tLZOE
HIGH IMPEDANCE
tHZOE
HIGH
IMPEDANCE
DATA VALID
tLZCE
tPU
SUPPLY
CURRENT
50%
50%
ICC
ISB
Notes:
20. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
21. WE is HIGH for read cycle.
22. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05392 Rev. *H
Page 6 of 12
CY62157DV30 MoBL®
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[19, 23, 24, 25]
tWC
ADDRESS
tSCE
CE1
CE2
tHA
tAW
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
See note 25
tHZOE
Write Cycle 2 (CE1 or CE2 Controlled)[19, 23, 24, 25]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
VALID DATA
See note 25
tHZOE
Notes:
23. Data I/O is high-impedance if OE = VIH.
24. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
25. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05392 Rev. *H
Page 7 of 12
CY62157DV30 MoBL®
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[24, 25]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
See note 25
tHD
VALID DATA
tLZWE
tHZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[24, 25]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
See note 25
Document #: 38-05392 Rev. *H
tHD
VALID DATA
Page 8 of 12
CY62157DV30 MoBL®
Truth Table
CE1
CE2
WE
OE
H
X
X
X
X
X
High Z
Deselect/Power-Down
Standby (ISB)
X
L
X
X
X
X
High Z
Deselect/Power-Down
Standby (ISB)
X
X
X
X
H
H
High Z
Deselect/Power-Down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
Read (Upper byte and Lower Byte)
Active (ICC)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15)
Read (Lower Byte only)
Active (ICC)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15)
Read (Upper Byte only)
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/O0–I/O15)
Write (Upper byte and Lower Byte)
Active (ICC)
L
H
L
X
H
L
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write (Lower Byte only)
Active (ICC)
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write (Upper Byte only)
Active (ICC)
Document #: 38-05392 Rev. *H
BHE
BLE
Inputs/Outputs
Mode
Power
Page 9 of 12
CY62157DV30 MoBL®
Ordering Information
Speed
(ns)
45
55
70
Package
Diagram
51-85150
51-85087
51-85150
Ordering Code
CY62157DV30L-45BVI
CY62157DV30LL-45ZSXI
CY62157DV30LL-55BVI
CY62157DV30L-55BVXI
CY62157DV30LL-55BVXI
CY62157DV30L-55ZXI
CY62157DV30LL-55ZSI
CY62157DV30L-55ZSXI
CY62157DV30LL-55ZSXI
CY62157DV30LL-55BVXA
CY62157DV30L-55BVXE
CY62157DV30L-55ZSXE
CY62157DV30LL-70BVI
CY62157DV30LL-70BVXI
Operating
Range
Industrial
Package Type
48-ball (6 x 8 x 1 mm) FBGA
44-pin TSOP II (Pb-free)
48-ball (6 x 8 x 1 mm) FBGA
48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
51-85183
51-85087
44-pin TSOP I (Pb-free)
44-pin TSOP II
44-pin TSOP II (Pb-free)
51-85150
51-85150
51-85087
51-85150
48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
44-pin TSOP II (Pb-free)
48-ball (6 x 8 x 1 mm) FBGA
48-ball (6 x 8 x 1 mm) FBGA (Pb-free)
Industrial
Automotive-A
Automotive-E
Industrial
Package Diagrams
48-ball FBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
4
5
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
0.55 MAX.
6.00±0.10
0.15(4X)
0.10 C
0.21±0.05
0.25 C
B
51-85150-*D
C
Document #: 38-05392 Rev. *H
1.00 MAX
0.26 MAX.
SEATING PLANE
Page 10 of 12
CY62157DV30 MoBL®
Package Diagrams (continued)
48-pin TSOP I (12 mm x 18.4 mm x 1.0 mm) (51-85183)
DIMENSIONS IN INCHES[MM] MIN.
MAX.
JEDEC # MO-142
0.037[0.95]
0.041[1.05]
N
1
0.020[0.50]
TYP.
0.472[12.00]
0.007[0.17]
0.011[0.27]
0.002[0.05]
0.006[0.15]
0.724 [18.40]
0.047[1.20]
MAX.
SEATING PLANE
0.004[0.10]
0.787[20.00]
0.004[0.10]
0.008[0.21]
0.010[0.25]
GAUGE PLANE
0°-5°
0.020[0.50]
0.028[0.70]
51-85183-*A
44-pin TSOP II (51-85087)
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05392 Rev. *H
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157DV30 MoBL®
Document History Page
Document Title: CY62157DV30 MoBL® 8-Mbit (512K x 16) MoBL® Static RAM
Document Number: 38-05392
REV.
ECN NO. Issue Date
**
126316
05/22/03
*A
131013
11/19/03
Orig. of
Change
HRT
Description of Change
New Data Sheet
CBD/LDZ Change from Advance to Preliminary
*B
133115
01/24/04
CBD
Minor Change: Change MPN and upload.
*C
211601
See ECN
AJU
Change from Preliminary to Final
Changed Marketing part number from CY62157DV to CY62157DV30 in the
title and in the Ordering Information table
Added footnotes 4, 5 and 11
Modified footnote 8 to include ramp time and wait time
Removed MAX value for VDR on Data Retention Characteristics table
Changed ordering code for Pb-free parts
Modified voltage limits in Maximum Ratings section
*D
236628
See ECN
*E
257349
See ECN
PCI
Added test condition for 45 ns part (footnote #13 on page 4)
*F
372074
See ECN
SYT
Added Pb-Free Automotive Part in the Ordering Information
Removed ‘Preliminary’ tag from Automotive Information
*G
433838
See ECN
ZSD
Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”
Updated the thermal resistance table
Updated the ordering information table and changed the package name
column to package diagram
*H
488954
See ECN
VKN
Added Automotive-A product
Updated ordering Information table
Document #: 38-05392 Rev. *H
SYT/AJU Added 45-ns and 70-ns Speed Bins
Added Automotive product information
Page 12 of 12
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