Rohm BD9884FV Silicon monolithic integrated circuit Datasheet

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STRUCTURE
Silicon Monolithic Integrated Circuit
NAME OF PRODUCT
DC-AC Inverter Control IC
TYPE
BD9884FV
FUNCTION
・2ch control with Half-bridge
・Lamp current and voltage sense feed back control
・Sequencing easily achieved with Soft Start Control
・Short circuit protection with Timer Latch
・Under Voltage Lock Out
・Short circuit protection with over voltage
・Mode-selectable the operating or stand-by mode by stand-by pin
・2ch BURST mode selectivity in-phase or reversed phase
・Synchronous operating the other BD9884FV IC’s
○Absolute Maximum Ratings(Ta = 25℃)
Parameter
Supply Voltage
Operating Temperature Range
Storage Temperature Range
Power Dissipation
Maximum Junction Temperature
*
Symbol
VCC
Topr
Tstg
Pd
Tjmax
Limits
12
-35~+85
-55~+125
850*
+125
Unit
V
℃
℃
mW
℃
Pd derated at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm)
〇Recommended operating condition
Parameter
Supply voltage
CT oscillation frequency
BCT oscillation frequency
Symbol
VCC
fCT
fBCT
Limits
5.0~11.0
20~150
0.05~1.00
Unit
V
kHz
kHz
Status of this document
The Japanese version of this document is the official specification.
Please use the translation version of this document as a reference to expedite understanding of the official version.
If these is any uncertainty in translation version of this document, official version takes priority.
REV. D
2/4
○Electric Characteristics(Ta=25℃,VCC=7V)
MIN.
Limits
TYP.
MAX.
Icc1
Icc2
-
-
9.0
4
17.0
10
mA
μA
Vovf
2.70
3.00
3.30
V
VstH1
2.4
-
VCC
V
VstH2
1.4
-
1.8
V
System ON
VstL
⊿Vst
-0.3
0.10
-
0.25
0.5
0.40
V
V
System OFF
Vcp
Icp
1.8
0.5
2.0
1.0
2.2
1.5
V
μA
OSC Max voltage
ICT
VoscH
1.35/RT
1.8
1.5/RT
2.0
1.65/RT
2.2
A
V
OSC Min voltage
VoscL
0.3
0.5
0.7
V
fCT=60kHz
MAXDUTY
44
46.5
49
%
fCT=60kHz
Parameter
((WHOLE DEVICE)
)
Operating current
Stand-by current
((OVER VOLTAGE DETECT))
FB over voltage detect voltage
((STAND BY CONTROL))
Stand-by voltage H1
(BURST mode in reverse phase)
Stand-by voltage H2
(BURST mode in phase)
Stand-by voltage L
Stand-by hysteresis
((TIMER LATCH))
Timer Latch voltage
Timer Latch current
((OSC BLOCK))
OSC constant current
MAX DUTY
Symbol
Unit
Conditions
CT=0.5V
System ON
fCT=60kHz
Iss
1.0
2.0
3.0
μA
Visc
Vss
RSRT
0.45
2.0
-
0.60
2.2
200
0.75
2.4
400
V
V
Ω
VuvloH
VuvloL
Vuvlo1
Vuvlo2
4.100
3.900
1.900
2.100
4.300
4.100
2.000
2.200
4.500
4.300
2.100
2.300
V
V
V
V
IS threshold voltage
Vis
1.220
1.250
1.280
V
VS threshold voltage
IS source current 1
IS source current 2
VS source current
((OUTPUT BLOCK)
)
Pch output voltage H
Nch output voltage H
Pch output voltage L
Nch output voltage L
Pch output sink resistance
Pch output source resistance
Nch output sink resistance
Nch output source resistance
((BURST MODE BLOCK))
Vvs
1.220
1.250
1.280
V
Iis1
Iis2
Ivs
-
13.0
-
-
20.0
-
1.5
27.0
1.0
μA
μA
μA
VoutPH
VoutNH
VoutPL
VoutNL
RsinkP
RsourceP
RsinkN
RsourceN
VCC-0.3
VCC-0.3
-
-
-
-
-
-
VCC-0.1
VCC-0.1
0.1
0.1
8
10
8
10
-
-
0.3
0.3
16
20
16
20
V
V
V
V
Ω
Ω
Ω
Ω
BOSC Max voltage
VburH
1.92
2.0
2.08
V
fBCT=0.3kHz
BOSC Min Voltage
VburL
0.4
0.5
0.6
V
fBCT=0.3kHz
BOSC constant current
IBCT
1.35/BRT
1.5/BRT
1.65/BRT
A
VREG
IREG
Vref
3.038
5.0
1.220
3.100
-
1.250
3.162
-
1.280
V
mA
V
VCOMPH
VCOMPL
2.20
0.590
2.5
0.640
2.80
0.690
V
V
VPH
VPL
2.9
-
3.1
-
3.3
0.5
V
V
Soft start current
IS COMP detect Voltage
SS COMP detect voltage
SRT ON resistance
((UVLO BLOCK))
Operating voltage
Lock out voltage
Operating voltage (External UVLO)
Lock out voltage (External UVLO)
((FEED BACK BLOCK))
((REG BLOCK))
REG output voltage
REG source current
VREF voltage
((COMP BLOCK))
Over voltage detect
Under voltage detect
((PROTECT CLOCK))
Normal output voltage
Protect output voltage
(This product is not designed for normal operation with in a radio active environment.)
REV. D
DUTY=2.0V
DUTY=0V、IS=0.5V
Isink =
Isource
Isink =
Isource
10mA
= 10mA
10mA
= 10mA
3/4
〇Package Dimensions
Device Mark
(Include BURR 10.35)
BD9884FV
1
Lot No.
SSOP-B28 (Unit:mm)
〇Block Diagram
〇Pin Description
CT
REG VREF
VCC
REG
BLOCK
STB
RT
OSC
BRT BCT
DUTY
BOSC
DUTY
BLOCK
Pin No.
1
Pin Name
DUTY
2
BRT
3
BCT
4
RT
5
SRT
6
CT
7
8
GND
FB1
Function
Control PWM mode and BURST mode
External resistor from BRT to GND for
adjusting the BURST triangle oscillator
External capacitor from BCT to GND for
adjusting the BURST triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External resistor from SRT to RT for
adjusting the triangle oscillator
External capacitor from CT to GND for
adjusting the triangle oscillator
GROUND
Error amplifier output①
9
IS1
Error amplifier input①
SYSTEM ON/OFF
STB
BLOCK
VCC
UVLO
BLOCK
UVLO
SS
FB1
IS1
VS1
VCC
F/B
BLOCK①
SS
PWM
BLOCK①
LOGIC
BLOCK
①
OUTPUT
BLOCK①
PWM
BLOCK②
LOGIC
BLOCK
②
OUTPUT
BLOCK②
CT
FB2
IS2
VS2
P1
N1
VCC
F/B
BLOCK②
SS
CT
P2
N2
PGND
GND
PROTECT
BLOCK
COMP1
COMP2
SCP
10
VS1
Error amplifier input②
11
12
13
FB2
IS2
VS2
14
VREF
Error amplifier output②
Error amplifier input③
Error amplifier input④
Reference voltage for ISNECE,VSENCE error
amplifier
15
FAIL
Protect clock output
16
17
18
19
STB
COMP1
COMP2
UVLO
Stand-by switch
Under, over voltage detect for 1ch
Under, over voltage detect for 2ch
External Under Voltage Lock OUT
20
REG
21
SS
22
SCP
23
P2
24
N2
25
PGND
26
N1
FAIL
SRT
REV. D
Internal regulator output
External capacitor from SS to GND for Soft
Start Control
External capacitor from SCP to GND for Timer
Latch
FET driver for 2ch
FET driver for 2ch
Ground for FET drivers
FET driver for 1ch
27
P1
FET driver for 1ch
28
VCC
Supply voltage input
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〇NOTE FOR USE
1. When designing the external circuit, including adequate margins for variation between external devices and the IC.Use
adequate margins for steady state and transient characteristics.
2. Recommended Operating Range
The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended
operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating
ranges, however, the variation will be small.
3. Mounting Failures
Mounting failures, such as misdirection or miscounts, may harm the device.
4. Electromagnetic Fields
A strong electromagnetic field may cause the IC to malfunction.
5.
The GND pin should be the location within
±0.3V compared with the PGND pin
6. BD9884FV has the short circuit protection with Thermal Shut Down System. When STB or Vcc pin re-supplied, They enables
to cancel the latch. If It rise the temperature of the chip more than 170℃(TYP), It make the external FET OFF
7. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened.
Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need
to be considered when using a device beyond its maximum ratings.
8. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching.
Make sure to leave adequate margin for this IC variation.
9. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.
10. By STB voltage, BD9884FV is changed to 3 states. Therefore, do not input STB pin voltage between one state and the other
state (0.5~1.4V, 1.8~2.4V).
11.The pin connected a connector need to connect to the resistor for electrical surge destruction.
12.This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is
formed from this P layer of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which
parasitic diodes operate, such as applying a voltage that is lower than the GND(P substrate)voltage to an input pin.
Transistor (NPN)
Resistance
(PinA)
B
(PinB)
E
C
C
GND
P
P+
N
P+
N
N
N
N
P substrate
GND
Parasitic diode
N
P substrate
GND
Parasitic diode
(PinB)
(PinA)
B
CC
B
EE
Parasitic diode
GND
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. D
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