TC9490F/FA TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9490F, TC9490FA Digital Servo Single-Chip Processor for Use in CD Player TC9490F/FA is a single-chip processor which incorporates the following functions: sync separation protection, interpolation, EFM decoder, error correction, microcontroller interface, digital equalizer for use in servo LSI, and servo control circuit. TC9490F/FA also incorporates a 1-bit DA converter. Combining TC9490F with digital servo head amp TA2147F enables very simple and completely adjustment-free CD player systems. TC9490F Features TC9490FA · Capable of decoding the text data. · Sync pattern detection, sync signal protection, and synchronization can be made correctly. · Built-in EFM demodulation circuit and subcode demodulation. · Capable of correcting dual C1 correction and quadruple C2 correction using the CIRC correction theoretical format. · The TC9490F respond to variable playback system. · Jitter absorbing capacity of ±6 frame. · Built-in 16 k RAM. · Built-in digital out circuit. · Built-in L/R independent digital attenuator. · Audio output responds to bilingual function. · Output format for audio out can be selected 32fs, 48fs or 64fs modes. · Read-timing-free subcode Q data and capable of synchronous output with audio data. · Built-in data slicer and analog PLL (adjustment-free VCO). · Capable of automatic adjustment function of focus and tracking servos for loop gain, offset and balance. · Built-in RF gain automatic adjustment circuit. · Built-in digital equalizer for phase compensation. · Built-in RAM for digital equalizer for coefficient, and capable of variable pickup. · Built-in focus and tracking servo control circuit. · Search control corresponds to every mode and can realize high speed and stable search. · Lens-kick and feed-kick are using speed controlled form. · Built-in AFC and APC circuits for CLV servo of disc motor. · Built-in anti-defect and anti-shock circuit. · Built-in 8 times oversampling digital filter and 1-bit DA converter. · Built-in analog filter for 1-bit DA converter. · Built-in zero data detection output circuit. · The TC9490F/FA capable of 4 times speed operation. · Built-in microcontroller interface circuit. · CMOS silicon structure and high speed, low power consumption. · 64-pin flat package. Weight: QFP64-P-1414-0.80A: 0.5 g (typ.) LQFP64-P-1010-0.50: 0.4 g (typ.) 1 2001-09-03 TC9490F/FA XVDD3 XO XI XVSS3 TESIN VDD3 VSS3 DMO FMO AVDD3 SEL TEBC RFGC VREF TRO FOO Block Diagram (top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DVSS3 49 32 TEZI Clock generator RO 50 DVDD3 51 31 TEI PWM D/A 30 SBAD LPF DVR 52 29 FEI 1-bit DAC A/D Servo control LO 53 28 RFRP DVSS3 54 27 RFZI ZDET 55 ROM Address circuit VSS5 56 Correction circuit BUS0 57 BUS1 58 RAM BUS2 59 24 RFI 23 SLCO 22 AVSS3 Sync signal protection EFM BUS3 60 25 AVDD3 Data slicer CLV servo 16 k RAM 26 RFCT Digital equalizer automatic adjustment circuit VCO 21 VCOF Audio output Digital output circuit BUCK 61 20 PVREF Microcontroller interface /CCE 62 Sub code decoder 19 LPFO PLL TMAX 2 IPF VDD3 VSS3 SBOK 9 10 11 12 13 14 15 16 PDO 8 PVDD3 7 /UHSO 6 /HSO 5 SBSY 4 SFSY 3 DATA 2 CLCK 1 DOUT 17 TMAX AOUT VDD5 64 LRCK 18 LPFN BCK /RST 63 2001-09-03 TC9490F/FA Pin Functions Pin No. Symbol I/O Function Description Remarks 1 BCK O 3-5I/F Bit clock output pin. 32fs, 48fs, or 64fs selectable by command. Normal speed: 32fs = 1.4112 MHz 2 LRCK O 3-5I/F L/R channel clock output pin. “L” for L channel and “H” for R channel. Output polarity can be inverted by command. Normal speed: 44.1 kHz 3 AOUT O 3-5I/F Audio data output pin. MSB-first or LSB-first selectable by command. 4 DOUT O 3-5I/F Digital data output pin. Outputs up to double-speed playback. 5 IPF O 3-5I/F Correction flag output pin. When set to “H”, AOUT output cannot Alias: C2PO be corrected by C2 correction processing. 6 VDD3 ¾ Digital 3.3 V power supply voltage pin. ¾ 7 VSS3 ¾ Digital GND pin. ¾ 8 SBOK O 3-5I/F Subcode Q data CRCC result output pin. “H” level when result is OK. ¾ 9 CLCK I/O 3-5I/F Subcode P-W data read clock I/O pin. I/O polarity selectable by command. 10 DATA O 3-5I/F Subcode P-W data output pin. ¾ 11 SFSY O 3-5I/F Playback frame sync signal output pin. ¾ 12 SBSY O 3-5I/F Subcode block sync signal output pin. “H” level at S1 when subcode sync is detected. ¾ ¾ Based on CP-1201 Schmit input Playback speed mode flag output pins. 13 /HSO O 3-5I/F 14 /UHSO O 3-5I/F 15 PVDD3 ¾ 16 PDO O AI/F 17 TMAX O AI/F /UHSO /HSO Playback Speed H H Normal H L Double L L 4 times ¾ ¾ ¾ ¾ ¾ ¾ PLL-only 3.3 V power supply voltage pin. EFM and PLCK phase difference signal output pin. 3-state output (PVDD3, PVREF, AVSS3) TMAX detection result output pin. 3-state output (PVDD3, HiZ, AVSS3) TMAX Detection Result TMAX Output Longer than fixed period “PVDD3” Within fixed period “HiZ” Shorter than fixed period “AVSS3” 18 LPFN I AI/F inverted input pin for PLL LPF amp. Analog input 19 LPFO O AI/F Output pin for PLL LPF amp. Analog output 20 PVREF ¾ 21 VCOF O AI/F ¾ PLL-only VREF pin. VCO filter pin. Analog output 3 2001-09-03 TC9490F/FA Pin No. Symbol I/O Function Description Remarks 22 AVSS3 ¾ 23 SLCO O AI/F DAC output pin for data slice level generation. Analog output 24 RFI I AI/F RF signal input pin. Zin selectable by command. Analog input 25 AVDD3 ¾ 26 RFCT I AI/F RFRP signal center level input pin. Analog input: Zin = 33 kW 27 RFZI I AI/F RFRP signal zero-cross input pin. Analog input 28 RFRP I AI/F RF ripple signal input pin. Analog input 29 FEI I AI/F Focus error signal input pin. Analog input 30 SBAD I AI/F Sub-beam adder signal input pin. Analog input 31 TEI I AI/F Tracking error input pin. Inputs when tracking servo is on. Analog input 32 TEZI I AI/F Tracking error signal zero-cross input pin. Analog input: Zin = 10 kW 33 FOO O Focus equalizer output pin. Analog output (AVSS3~AVDD3) 34 TRO O AI/F 35 VREF ¾ 36 RFGC O AI/F RF amplitude adjustment control signal output pin. 37 TEBC O AI/F Tracking balance control signal output pin. 38 SEL O AI/F APC circuit ON/OFF signal output pin. At laser on, high impedance with UHS = “L”, H output with UHS = “H”. 39 AVDD3 ¾ 40 FMO O AI/F Feed equalizer output pin. 41 DMO O AI/F Disc equalizer output pin. 42 VSS3 ¾ Digital GND pin. ¾ 43 VDD3 ¾ Digital 3.3 V power supply voltage pin. ¾ 44 TESIN I 3I/F Test input pin. Normally, fixed to “L”. ¾ 45 XVSS3 ¾ System clock oscillator GND pin. ¾ 46 XI I AI/F System clock oscillator input pin. ¾ 47 XO O AI/F System clock oscillator output pin. ¾ 48 XVDD3 ¾ System clock oscillator 3.3 V power supply voltage pin. ¾ 49 DVSS3 ¾ DA converter GND pin. ¾ 50 RO O AI/F R-channel data forward output pin. ¾ 51 DVDD3 ¾ DA converter 3.3 V power supply pin. ¾ 52 DVR ¾ Reference voltage pin. ¾ 53 LO O AI/F L-channel data forward output pin. ¾ ¾ Analog GND pin. ¾ Analog 3.3 V power supply voltage pin. Tracking equalizer output pin. ¾ Analog reference power supply voltage pin. Analog 3.3 V power supply voltage pin. 3-state output (PWM carrier = 88.2 kHz) (AVDD3, VREF, AVSS3) 3-state output ¾ 3-state output (PWM carrier = 88.2 kHz) (AVDD3, VREF, AVSS3) 4 2001-09-03 TC9490F/FA Pin No. Symbol I/O Function Description Remarks 54 DVSS3 ¾ 55 ZDET O 3-5I/F 56 VSS5 ¾ 57 BUS0 58 BUS1 59 BUS2 60 BUS3 61 BUCK I 3-5I/F Microcontroller interface clock input pin. Schmit input 62 /CCE I 3-5I/F Microcontroller interface chip enable signal input pin. At “L”, BUS0 to BUS3 are active. Schmit input 63 /RST I 3-5I/F Reset signal input pin. At reset, “L”. Built-in pull-up resistor 64 VDD5 ¾ DA converter GND pin. ¾ 1 bit DA converter zero data detection flag output pin. ¾ Microcontroller interface GND pin. ¾ Microcontroller interface data I/O pins. Schmit input CMOS ports I/O 3-5I/F ¾ Microcontroller interface 5 V power supply pin. Note: AI/F: analog input/output pin 3-5I/F: 3-5 interface built-in pin (5 V input/output pin) 3I/F: 3 V input/output pin Maximum Ratings (unless otherwise specified, GND reference, Ta = 25°C) Characteristics Symbol Rating VDD5 -0.3~6.0 Unit Remarks 64-56 pin 6-7 pin Power supply voltage VDD3 -0.3~4.5 V 15, 25, 39-22 pin 43-42 pin 48-45 pin 51-49, 54 pin VIN5 Input voltage VIN3 -0.3~ VDD5 + 0.3 -0.3~ VDD3 + 0.3 57~63, (9) pin V 1250 Power dissipation PD mW 18, 24, 26, 27, 28, 29, 30, 31, 32, 44 pin TC9490F TC9490FA 1170 Operating temperature Topr -40~+85 °C ¾ Storage temperature Tstg -55~+150 °C ¾ 5 2001-09-03 TC9490F/FA Electrical Characteristics (unless otherwise specified, VDD5 = 5 V, VDD3 = AVDD3 = DVDD3 = XVDD3 = PVDD3 = 3.3 V, Ta = 25°C) DC Characteristics Symbol Test Circuit Test Condition Min Typ. Max VDD5 ¾ ¾ 4.5 5.0 5.5 VDD3 ¾ ¾ AVDD3 ¾ ¾ DVDD3 ¾ ¾ 3.0 3.3 3.6 XVDD3 ¾ ¾ PVDD3 ¾ ¾ IDD5 ¾ ¾ 2 5 IDD3 ¾ ¾ 30 50 IDD5 ¾ ¾ 2.5 6 IDD3 ¾ ¾ 35 60 IDD5 ¾ ¾ 3 7 IDD3 ¾ ¾ 40 70 “H” level VIH5 ¾ 3.5 ¾ ¾ “L” level VIL5 ¾ CMOS input pins except for analog input pins (5 V) ¾ ¾ 1.5 “H” level IIH5 ¾ VIH5 = 5 V ¾ ¾ 1.0 “L” level IIL5 ¾ VIL5 = 0 V -1.0 ¾ ¾ “H” level ITLH5 ¾ VIH5 = 5 V ¾ ¾ 1.0 “L” level ITLL5 ¾ VIL5 = 0 V -1.0 ¾ ¾ “H” level IOH5 ¾ ¾ ¾ -2.0 “L” level IOL5 ¾ VOH5 = 4.6 V Pins grouped as 1 in V = 0.4 V the following table 2.0 ¾ ¾ “H” level IOH5 ¾ ¾ ¾ -4.0 “L” level IOL5 ¾ 4.0 ¾ ¾- “H” level VIH3 ¾ 2.3 ¾ ¾ “L” level VIL3 ¾ CMOS input pins except for analog input pins (3 V) ¾ ¾ 1.0 “H” level IIH3 ¾ VIH3 = 3.3 V ¾ ¾ 1.0 “L” level IIL3 ¾ VIL3 = 0 V -1.0 ¾ ¾ “H” level ITLH3 ¾ VIH3 = 3.3 V ¾ ¾ 1.0 “L” level ITLL3 ¾ VIL3 = 0 V -1.0 ¾ ¾ “H” level IOH3 ¾ ¾ ¾ -2.0 “L” level IOL3 ¾ VOH3 = 2.9 V Pins grouped as 4 in V = 0.4 V the following table 2.0 ¾ ¾ “H” level IOH3 ¾ ¾ -80 ¾ “L” level IOL3 ¾ VOH3 = 2.9 V Pins grouped as 5 in V = 0.4 V the following table ¾ 80 ¾ “H” level IOH3 ¾ ¾ -121 ¾ “L” level IOL3 ¾ VOH3 = 2.9 V Pins grouped as 6 in V = 0.4 V the following table ¾ 121 ¾ VREF output on resistance RON ¾ ¾ ¾ ¾ 500 Pull-up resistance RUP ¾ Pins grouped as 8 in the following table 25 50 75 RO1 ¾ Pins grouped as 5 in the following table ¾ 5.0 ¾ RO2 ¾ Pins grouped as 6 and 7 in the following table ¾ 3.3 ¾ Characteristics Operating power supply voltage Normal speed Operating power supply current Double speed 4 times speed Input voltage 1 Input current 1 Tri-state leak current 1 Output current 1 Input voltage 2 Input current 2 Tri-state leak current 2 Output current 2 XI = 16.9344 MHz Pins grouped as 1, 2, 3 in the following table OL5 VOH5 = 4.6 V Pins grouped as 2 and 3 in the VOL5 = 0.4 V following table Pins grouped as 4 and 5 in the following table OL3 OL3 OL3 Pin built-in output resistance 6 Unit V mA V mA mA mA V mA mA mA mA W kW kW 2001-09-03 TC9490F/FA Pin Group Pin Name 1 SBOK, SFSY, SBSY, /HSO, /UHSO, ZDET 2 BCK, LRCK, AOUT, DOUT, IPF, CLCK, DATA 3 BUS3, BUS2, BUS1, BUS0 4 SEL, TMAX 5 PDO 6 RFGC, TEBC, FMO, DMO 7 FOO, TRO 8 /RST AC Characteristics 1. Microcontroller Interface Timing Symbol Test Circuit Test Condition Min Typ. Max /CCE = “H” pulse width tCC ¾ ¾ 120 ¾ ¾ Data disable time tSZ1 ¾ BUCK rise reference 0 ¾ ¾ /CCE, BUCK delay time tCB ¾ /CCE fall reference 0 ¾ ¾ BUCK, /CCE delay time tBC ¾ BUCK rise reference 0 ¾ ¾ tBLW ¾ Write, SRC mode 120 ¾ ¾ tBLW ¾ QDRC mode 240 ¾ ¾ BUCHK = “H” pulse width (1) tBHW ¾ Write, SRC mode 120 ¾ ¾ BUCHK = “H” pulse width (2) tBHW ¾ QDRC mode (normal speed) 3000 ¾ ¾ BUCHK = “H” pulse width (3) tBHW ¾ QDRC mode (double speed) 1500 ¾ ¾ BUCHK = “H” pulse width (4) tBHW ¾ QDRC mode (´4 speed) 800 ¾ ¾ Write data setup time tWS ¾ BUCK rise reference 60 ¾ ¾ Write data hold time tWH ¾ BUCK rise reference 20 ¾ ¾ Data disable time tSZ2 ¾ BUCK fall reference 0 ¾ ¾ Read data access time tRD ¾ BUCK fall reference 0 ¾ ¾ Characteristics BUCK = “L” pulse width (1) Unit ns Write command mode tCB tBC tCC /CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS CM tWH CL DM DL Write mode 7 2001-09-03 TC9490F/FA (2) Write command mode: Bxxxxx, Fxxxxx commands tBC tCC tBC tCC Min Typ. Max ¾ ¾ 5 ¾ ¾ 5 ¾ ¾ 5 ¾ ¾ 5 tCB /CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS tWH CM CL DM DL EM EL Write mode (3) Read command mode tCB /CCE tBLW tBHW BUCK tSZ2 BUSi (input) tWS tWH CM tRD BUSi (input) tSZ1 RDO RDn Read mode 2. AOUT Data Output Timing Symbol Test Circuit “H” level tpLH1 ¾ “L” level tpHL1 ¾ “H” level tpLH2 ¾ “L” level tpHL2 ¾ Characteristics Transfer time (1) Transfer time (2) tpHL2 tpLH2 Test Condition LRCK AOUT Unit ns tpHL1 tpLH1 BCK LRCK AOUT 8 2001-09-03 TC9490F/FA 3. DATA, CLCK Input/Output Timing (1) CLCK input mode (regardless of setting of HS and UHS bits of SPEED command) Symbol Test Circuit “H” level tHW “L” level Characteristics Clock pulse width Min Typ. Max ¾ 50 ¾ ¾ tLW ¾ 50 ¾ ¾ tSU ¾ 400 ¾ ¾ “L” level tpHL1 ¾ ¾ ¾ 5 “H” level tpLH2 ¾ ¾ ¾ 15 “L” level tpHL2 ¾ ¾ ¾ 15 Min Typ. Max Input setup time Transfer time (1) Transfer time (2) Test Condition CLCK input mode tpHL1 Unit ns tpHL2 tpLH2 SFSY tSU tHW tLW CLCK SUBP DATA (2) SUBQ CLCK output mode (tHW, tLW, tpLH3 only, ´ 1/n at ´n speed) Symbol Test Circuit “H” level tHW ¾ ¾ ¾ 950 “L” level tLW ¾ ¾ ¾ 950 “L” level tpHL1 ¾ ¾ ¾ 5 “H” level tpLH2 ¾ ¾ ¾ 15 “L” level tpHL2 ¾ ¾ ¾ 15 “H” level tpLH3 ¾ ¾ ¾ 850 Characteristics Clock pulse width Transfer time (1) Transfer time (2) Transfer time (3) Test Condition CLCK output mode tpHL1 Unit ns tpHL2 tpLH2 SFSY tpLH3 tHW tLW CLCK DATA SUBP SUBQ 9 2001-09-03 TC9490F/FA 4. SBSY, SBOK Input/Output Timing Symbol Test Circuit “H” level tpLH1 ¾ “L” level tpHL1 ¾ “H” level tpLH2 ¾ “L” level tpHL2 ¾ Characteristics Transfer time (1) Transfer time (2) Test Condition SBSY SBOK tpLH1 Min Typ. Max ¾ ¾ 5 ¾ ¾ 10 ¾ ¾ 15 ¾ ¾ 20 Min Typ. Max ¾ ¾ 7 ¾ ¾ 12 ¾ ¾ 7 ¾ ¾ 7 ¾ ¾ 7 ¾ ¾ 7 ¾ ¾ 10 ¾ ¾ 10 Unit ns tpHL1 SFSY tpLH2 tpHL2 SBSY SBOK 5. Output Pin Timing Symbol Test Circuit Output rise time (1) tor1 ¾ Output fall time (1) tof1 ¾ Output rise time (2) tor2 ¾ Characteristics Output fall time (2) tof2 ¾ Output rise time (3) tor3 ¾ Output fall time (3) tof3 ¾ Output rise time (4) tor4 ¾ Output fall time (4) Pins grouped as 1 below Pins grouped as 2 below Pins grouped as 3 below Pins grouped as 4 below ¾ tof4 Pin Group Test Condition Unit ns Pin Name 1 SBOK, SFSY, SBSY, /HSO, /UHSO, ZDET 2 BCK, LRCK, AOUT, DOUT, IPF, CLCK, DATA 3 BUS3, BUS2, BUS1, BUS0 4 TMAX, SEL VOH 90% VOH/2 10% VSS tor tof 10 2001-09-03 TC9490F/FA Analog Circuit Characteristics 1. AD Converter Characteristics Test Circuit Test Condition Min Typ. Max Unit ¾ ¾ ¾ 8 ¾ bit ¾ 88.2 ¾ ¾ 88.2 ¾ ¾ 88.2 ¾ ¾ 88.2 ¾ 0.2 ´ AVDD3 ¾ 0.8 ´ AVDD3 V Resolution FE ¾ TE ¾ SBAD ¾ RFRP ¾ Sampling frequency ¾ Conversion input range ¾ AVSS = 0 V, AVDD3 = 3.3 V kHz 2. DA Converter (focus and tracking equalizer output) Test Circuit Test Condition Min Typ. Max Unit Number of bits ¾ ¾ ¾ ¾ 5 bit Sampling frequency ¾ ¾ ¾ ¾ 2.8 MHz Signal output range ¾ AVSS3 ¾ AVDD3 V Characteristics AVSS = 0 V, AVDD3 = 3.3 V 3. PLL Filter Amp Test Circuit Test Condition Min Typ. Max Unit I/O signal range ¾ ¾ AVSS3 ¾ PVDD3 V Frequency characteristic ¾ ¾ 8 ¾ MHz Min Typ. Max Unit ¾ 34 ¾ MHz Characteristics -3 dB point (Gain = 1) 4. VCO (PLL) Characteristics Test Circuit Center oscillation frequency Frequency variable range Test Condition ¾ LPFO = VREF ¾ [VCOGSL] bit = “L” -55 ¾ +55 ¾ [VCOGSL] bit = “H” -65 ¾ +65 % 5. TEZI Signal Comparator Test Circuit Test Condition Min Typ. Max Unit Input range ¾ ¾ AVSS3 ¾ AVDD3 V Hysteresis voltage ¾ -50 ¾ +50 mV Characteristics VREF reference 6. RFZI Signal Comparator Test Circuit Test Condition Min Typ. Max Unit Input range ¾ ¾ AVSS3 ¾ AVDD3 V Hysteresis voltage ¾ -50 ¾ +50 mV Characteristics VREF reference 11 2001-09-03 TC9490F/FA 7. Data Slicer Circuit (1) Comparator Test Circuit Characteristics ¾ Input amplitude (2) Test Condition VREF refenence Min Typ. Max Unit 0.6 1.2 2.0 Vpp R-2R DAC (digital slicer DAC) Test Circuit Test Condition Min Typ. Max Unit Output conversion range ¾ ¾ AVSS3 ¾ AVDD3 V Output impedance ¾ ¾ ¾ 2.5 ¾ kW Characteristics 8. Audio DAC Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit THD + N 1 1 kHz sine wave, full-scale input ¾ -85 -80 dB S/N ratio S/N 1 ¾ 87 92 ¾ dB Dynamic range DR 1 1 kHz sine wave, -60 dB input conversion 85 90 ¾ dB Crosstalk CT 1 1 kHz sine wave, full-scale input ¾ -90 -85 dB DACout 1 1 kHz sine wave, full-scale input 810 860 910 mVrms Characteristics Total harmonic distortion + noise Analog output amplitude Test Circuit 1: Application circuit is used. Lout TC9490F/FA application circuit Distortion meter 20 kHz ideal LPF Rout LPF: Filter with built-in Shibasoku 725C Distortion meter: Shibasoku 725 equivalent Characteristic Distortion Filter Setting A-weight THD + N, CT OFF S/N, DR ON A-weight: IEC-A equivalent Application Circuit TC9490F/FA DVSS3 3.3 V R-ch analog output 10 k9 DVDD3 22 mF DVR XO DVSS3 12 L-ch analog output 10 k9 150 W 150 W 3.3 mF LO 1800 pF XVSS3 1800 pF 16.9344 MHz 1 M9 XI 3.3 V 1800 pF XVDD3 1800 pF 150 W 150 W 3.3 mF RO 2001-09-03 TC9490F/FA Package Dimensions Weight: 0.5 g (typ.) 13 2001-09-03 TC9490F/FA Package Dimensions Weight: 0.4 g (typ.) 14 2001-09-03 TC9490F/FA RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 15 2001-09-03