TI DRV110PWR Power saving solenoid controller with integrated supply regulation Datasheet

DRV110
www.ti.com
SLVSBA8 – MARCH 2012
POWER SAVING SOLENOID CONTROLLER WITH INTEGRATED SUPPLY REGULATION
Check for Samples: DRV110
FEATURES
1
•
•
•
•
Drives an External MOSFET With PWM to
Control Solenoid Current
– External Sense Resistor for Regulating
Solenoid Current
Fast Ramp-Up of Solenoid Current to
Guarantee Activation
Solenoid Current is Reduced in Hold Mode for
Lower Power and Thermal Dissipation
Ramp Peak Current, Keep Time at Peak
Current, Hold Current and PWM Clock
Frequency Can Be Set Externally. They Can
Also Be Operated at Nominal Values Without
External Components.
Internal Supply Voltage Regulation
– 15-V Nominal MOSFET Gate Drive Voltage
•
•
•
– External Pull-Up Resistor to Solenoid
Supply Voltage
Protection
– Thermal Shutdown
– Under Voltage Lockout (UVLO)
– Maximum Ramp Time
– Optional STATUS Output
Operating Temperature Range: -40ºC to 105ºC
8-Pin and 14-Pin TSSOP Package Options
APPLICATIONS
•
•
Electromechanical Driver: Solenoids, Valves,
Relays
White Goods, Solar, Transportation
DESCRIPTION
The DRV110 is a PWM current controller for solenoids. It is designed to regulate the current with a well
controlled waveform to reduce power dissipation. The solenoid current is ramped up fast to ensure opening of
the valve or relay. After initial ramping the solenoid current is kept at peak value to ensure the correct operation,
after which it is reduced to a lower hold level in order to avoid thermal problems and reduce power dissipation.
The peak current duration is set with an external capacitor. The current ramp peak and hold levels, as well as
PWM frequency can independently be set with external resistors. External setting resistors can also be omitted, if
the default values for the corresponding parameters are suitable for the application.
The DRV110 limits its own supply at VIN to 15 V which is also the gate drive voltage of an external switching
device. For example, a MOSFET that is driving the solenoid load. If a lower gate drive voltage is required, an
external supply of at least 6 V can be used.
The DRV110 is available in 8-pin and 14-pin TSSOP package options.
ORDERING INFORMATION (1)
ORDERABLE PART
NUMBER
PACKAGE (2)
(1)
(2)
TOP-SIDE
MARKING
(TSSOP-8) - PW
Reel of 2000
DRV110PWR
110
(TSSOP-14) - PW
Reel of 2000
DRV110APWR
110A
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2012, Texas Instruments Incorporated
PRODUCT PREVIEW
•
DRV110
SLVSBA8 – MARCH 2012
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TYPICAL APPLICATION
PRODUCT PREVIEW
Figure 1. Default Configuration With 8-Pin TSSOP Option
Figure 2. External Parameter Setting for 14-Pin TSSOP Option
2
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SLVSBA8 – MARCH 2012
DEVICE INFORMATION
PRODUCT PREVIEW
Functional Block Diagram
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Table 1. TERMINAL FUNCTIONS
PIN
(8-PIN PW) (1)
PIN
(14-PIN PW)
KEEP
1
2
Keep time set
PEAK
2
3
Peak current set
HOLD
-
4
Hold current set
OSC
3
5
PWM frequency set
VIN
4
7
6-V to 18-V supply
GND
5
8
Ground
SENSE
6
9
Solenoid current sense
OUT
7
11
Solenoid switch gate drive
STATUS
-
12
Open drain fault indicator
EN
8
13
Enable
NC
-
1, 6, 10, 14
NAME
(1)
DESCRIPTION
No connect
In the 8-pin package, the HOLD pin is not bonded out. For this package, the HOLD mode is configured to default (internal) settings.
xxx
xxx
PRODUCT PREVIEW
PW PACKAGE
8-PIN
(TOP VIEW)
4
PW PACKAGE
14-PIN
(TOP VIEW)
KEEP
1
8
EN
PEAK
2
7
OSC
3
VIN
4
NC
1
14
NC
OUT
KEEP
2
13
EN
6
SENSE
PEAK
3
12
STATUS
5
GND
HOLD
4
11
OUT
OSC
5
10
NC
NC
6
9
SENSE
VIN
7
8
GND
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ABSOLUTE MAXIMUM RATINGS (1) (2)
VIN
VALUE
UNIT
–0.3 to 20
V
Voltage range on EN, STATUS, PEAK, HOLD, OSC, SENSE, KEEP
–0.3 to 7
V
Voltage range on OUT
–0.3 to 20
V
Input voltage range
ESD rating
HBM (human body model)
2000
CDM (charged device model)
500
V
TJ
Operating virtual junction temperature range
–40 to 125
°C
Tstg
Storage temperature range
–65 to 150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
IQ
Supply current
1
1.5
3
VIN
Device will start sinking current when VIN > 15 V to limit VIN
6
15
V
1
4.7
µF
Input capacitor between VIN and GND
L
Solenoid inductance
TA
Operating ambient temperature
(1)
mA
1
PRODUCT PREVIEW
CIN
(1)
UNIT
H
-40
105
°C
4.7-µF input capacitor and full wave rectified 230-Vrms AC supply results in approximately 500-mV supply ripple.
ELECTRICAL CHARACTERISTICS
VIN = 14 V, TA = -40°C to 105°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Standby current
EN = 0, VIN = 14 V, bypass deactivated
200
250
Quiescent current
EN = 1, VIN = 14 V, bypass deactivated
360
570
Internally regulated supply
EN = 0, IVIN = 2 mA, bypass activated
10.5
15
19
EN = 1, IVIN = 2 mA, bypass activated
14.5
15
15.5
µA
V
GATE DRIVER
VDRV
Gate drive voltage
Supply voltage in regulation (IVIN > 1 mA)
IDRV_SINK
Gate drive sink current
VOUT = 15 V; VIN = 15 V
IDRV_SOURCE
Gate drive source current
VOUT = GND; VIN = 15 V
fPWM
PWM clock frequency
OSC = GND
DMAX
Maximum PWM duty cycle
100
%
DMIN
Minimum PWM duty cycle
7.5
%
tD
Start-up delay
8
15
VIN
V
15
mA
-15
-10
mA
20
27
kHz
Delay between EN going high until gate driver
starts switching, fPWM = 20 kHz
50
µs
CURRENT CONTROLLER, INTERNAL SETTINGS
IPEAK
Peak current
RSENSE = 1 Ω, PEAK = GND
270
300
330
mA
IHOLD
Hold current
RSENSE = 1 Ω, HOLD = GND
40
50
65
mA
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SLVSBA8 – MARCH 2012
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 14 V, TA = -40°C to 105°C, over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT CONTROLLER, EXTERNAL SETTINGS
tKEEP
Externally set keep time at peak
current
VPEAK
Externally set VPEAK
VHOLD
Externally set VHOLD
fPWM
Externally set PWM clock frequency
CKEEP = 1 µF
100
RPEAK = 50 kΩ
900
RPEAK = 200 kΩ
300
RHOLD = 50 kΩ
150
RHOLD = 200 kΩ
50
ROSC = 50 kΩ
60
ROSC = 200 kΩ
20
ms
mV
mV
kHz
LOGIC INPUT LEVELS (EN)
VIL
Input low level
1.3
VIH
Input high level
1.65
REN
Input pull-up resistance
350
V
V
500
kΩ
LOGIC OUTPUT LEVELS (STATUS)
VOL
Output low level
Pull-down activated, ISTATUS = 2 mA
IIL
Output leakage current
Pull-down deactivated, V(STATUS) = 5 V
0.3
V
2
µA
PRODUCT PREVIEW
UNDERVOLTAGE LOCKOUT
VUVLO
Undervoltage lockout threshold
4.6
V
160
°C
THERMAL SHUTDOWN
TTSD
6
Junction temperature shutdown
threshold
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SLVSBA8 – MARCH 2012
FUNCTIONAL DESCRIPTION
DRV110 controls the current through the solenoid as shown in Figure 3. Activation starts when EN pin voltage is
pulled high either by an external driver or internal pull-up. In the beginning of activation, DRV110 allows the load
current to ramp up to the peak value IPEAK and it regulates it at the peak value for the time, tKEEP, before reducing
it to IHOLD. The load current is regulated at the hold value as long as the EN pin is kept high. The initial current
ramp-up time depends on the inductance and resistance of the solenoid. Once EN pin is driven to GND, DRV110
allows the solenoid current to decay to zero.
ISOLENOID
IPEAK
t
tKEEP
EN
t
Figure 3. Typical Current Waveform Through the Solenoid
tKEEP is set externally by connecting a capacitor to the KEEP pin. A constant current is sourced from the KEEP
pin that is driven into an external capacitor resulting in a linear voltage ramp. When the KEEP pin voltage
reaches 100 mV, the current regulation reference voltage, VREF, is switched from VPEAK to VHOLD. Dependency of
tKEEP from the external capacitor size can be calculated by:
ésù
tKEEP éës ùû = CKEEP éëF ùû × 105 ê ú
ëF û
(1)
The current control loop regulates, cycle-by-cycle, the solenoid current by sensing voltage at the SENSE pin and
controlling the external switching device gate through the OUT pin. During the ON-cycle, the OUT pin voltage is
driven and kept high (equal to VIN voltage) as long as the voltage at the SENSE pin is less than VREF allowing
current to flow through the external switch. As soon as the voltage at the SENSE pin is above VREF, the OUT pin
voltage is immediately driven and kept low until the next ON-cycle is triggered by the internal PWM clock signal.
In the beginning of each ON-cycle, the OUT pin voltage is driven and kept high for at least the time determined
by the minimum PWM signal duty cycle, DMIN.
VPEAK and VHOLD depend on fixed resistance values RPEAK and RHOLD as shown in Figure 4. If the PEAK pin is
connected to ground, the peak current reference voltage, VPEAK, is at it’s default value (internal setting). The
VPEAK value can alternatively be set by connecting an external resistor to ground from the PEAK pin. For
example, if a 50-kΩ (= RPEAK) resistor is connected between PEAK and GND, and RSENSE = 1 Ω, then the
externally set IPEAK level will be 900 mA. If RPEAK = 200 kΩ and RSENSE = 1 Ω, then the externally set IPEAK level
will be 300 mA. In case RSENSE = 2 Ω instead of 1 Ω, then IPEAK = 450 mA (when RPEAK = 50 kΩ) and
IPEAK = 150 mA (when RPEAK = 200 kΩ). External setting of the HOLD current, IHOLD, works in the same way, but
the current levels are 1/6 of the IPEAK levels. External settings for IPEAK and IHOLD are independent of each other.
If RPEAK is decreased below 33.33 kΩ (typ value), then the reference is clamped to the internal setting. The same
is valid for RHOLD and IHOLD. IPEAK and IHOLD values can be calculated by using the formula below.
1W
900mA
IPEAK =
×
× 66.67kW ;66.67kW < RPEAK < 2MW
RSENSE RPEAK
(2)
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PRODUCT PREVIEW
IHOLD
DRV110
SLVSBA8 – MARCH 2012
I
HOLD =
1W
RSENSE
×
www.ti.com
150mA
× 66.67kW ;66.67kW < RHOLD < 333kW
RHOLD
(3)
PRODUCT PREVIEW
Figure 4. PEAK and HOLD Mode VREF Settings
8
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SLVSBA8 – MARCH 2012
Figure 5. PWM Clock Frequency Setting
Voltage at the OUT pin, that is the gate voltage of an external switching device, is equal to VIN voltage during
ON-cycle. It is driven to ground during OFF-cycle. VIN voltages below 15 V can be supplied directly from an
external voltage source. Supply voltages of at least 6 V are supported.
DRV110 is able to regulate VIN voltage to 15 V from a higher external supply voltage, VS, by an internal bypass
regulator that replicates the function of an ideal Zener diode. This requires that the supply current is sufficiently
limited by an external resistor between VS and the VIN pin. An external capacitor connected to the VIN pin is
used to store enough energy to charge the external switch gate capacitance at the OUT pin. Current limiting
resistor size to keep quiescent current less than 1 mA can be calculated by Equation 5.
VS,max DC - 15V
RS =
1mA + IGate,AVE
(5)
Open-drain pull-down path at the STATUS pin is deactivated if either under voltage lockout or thermal shutdown
blocks have triggered.
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PRODUCT PREVIEW
Frequency of the internal PWM clock signal, PWMCLK, that triggers each OUT pin ON-cycle can be adjusted by
external resistor, ROSC, connected between OSC and GND. Frequency as a function of resistor value is shown in
Figure 5. Default frequency is used when OSC is connected to GND directly. PWM frequency as a function of
external fixed adjustment resistor value (greater than 66.67 kΩ) is given below.
60kHz
fPWM =
× 66.67kW ;66.67kW < ROSC < 2MW
ROSC
(4)
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
DRV110APWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DRV110PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-May-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV110APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
DRV110PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-May-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV110APWR
TSSOP
PW
14
2000
346.0
346.0
29.0
DRV110PWR
TSSOP
PW
8
2000
346.0
346.0
29.0
Pack Materials-Page 2
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