TI ADC0803 8-bit analog-to-digital converters with differential input Datasheet

ADC0803, ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986
D
D
D
D
D
D
D
D
D
D
D
8-Bit Resolution
Ratiometric Conversion
100-µs Conversion Time
135-ns Access Time
Guaranteed Monotonicity
High Reference Ladder Impedance
8 kΩ Typical
No Zero Adjust Requirement
On-Chip Clock Generator
Single 5-V Power Supply
Operates With Microprocessor or as
Stand-Alone
Designed to Be interchangeable With
National Semiconductor and Signetics
ADC0803 and ADC0805
N PACKAGE
(TOP VIEW)
CS
RD
WR
CLK IN
INTR
IN +
IN –
ANLG GND
REF/2
DGTL GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC (OR REF)
CLK OUT
DB0 (LSB)
DB1
DB2
DB3
DATA
OUTPUTS
DB4
DB5
DB6
DB7 (MSB)
description
The ADC0803 and ADC0805 are CMOS 8-bit, successive-approximation, analog-to-digital converters that use
a modified potentiometric (256R) ladder. These devices are designed to operate from common microprocessor
control buses with the 3-state output latches driving the data bus. The devices can be made to appear to the
microprocessor as a memory location or an I/O port. Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
A differential analog voltage input allows increased common-mode rejection and offset of the zero-input analog
voltage value. Although a reference input (REF/2) is available to allow 8-bit conversion over smaller analog
voltage spans or to make use of an external reference, ratiometric conversion is possible with the REF/2 input
open. Without an external reference, the conversion takes place over a span from VCC to ANLG GND. The
devices can operate with an external clock signal or with an additional resistor and capacitor, using an on-chip
clock generator.
The ADC0803C and ADC0805C are characterized for operation from 0°C to 70°C. The ADC0803I and
ADC0805I are characterized for operation from – 40°C to 85°C.
Copyright  1986, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
ADC0803, ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986
functional block diagram (positive logic)
RD
CS
WR
2
1
Start
Flip-Flop
3
S
CLK A
CLK
OUT
CLK IN
DGTL
GND
VCC
REF/2
R
1D
CLK
C1
19
Clk
Gen
4
Clk Osc
10
CLK A
CLK
CLK B
CLK B
20
D
Ladder
and
Decoder
9
SAR
Latch
8-Bit
Shift
Register
LE
R
Interrupt
Flip-Flop
R
ANLG
GND
IN +
IN –
R
8
5
DAC
1D
VCC
6
CLK A
Σ
S
Comp
7
LE EN
3-State
Output
Latch
2
C1
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17
16
15
14
13
12
11
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DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7 (MSB)
INTR
ADC0803, ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range: CS, RD, WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 18 V
Other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC 0.3 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC 0.3 V
Operating free-air temperature range: ADC080_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
ADC080_I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTE 1: All voltage values are with respect to digital ground (DGTL GND) with DGTL GND and ANLG GND connected together unless otherwise
noted.
recommended operating conditions
Supply voltage, VCC
Analog input voltage (see Note 2)
MIN
NOM
4.5
5
– 0.05
Voltage at REF/2 (see Note 3), VREF/2
0.25
High-level input voltage at CS, RD, or WR, VIH
Duty cycle for fclock above 640 kHz (see Note 5)
1
1460
100
ADC080_I
V
0
40%
ADC080_C
V
0.8
640
Pulse durartion, WR input low, tW(WR)
V
V
100
275
V
15
– 0.05
Pulse durartion, clock input (high or low) for fclock below 640 kHz, tW(CLK)
free air temperature,
temperature TA
Operating free–air
6.3
2.5
Low-level input voltage at CS, RD, or WR, VIL
Clock iput frequency (see Note 5), fclock
UNIT
VCC = 0.05
2
Analog ground voltage (see Note 4)
MAX
V
kHz
60%
781
ns
ns
0
70
–40
85
°C
NOTES: 2. When the differential input voltage (VI+ – VI–) is less than or equal to 0 V, the output code is 0000 0000.
3. The internal reference voltage is equal to the voltage applied to REF/2 or approximately equal to one-half of the VCC when REF/2
is left open. The voltage at REF/2 should be one-half the full-scale differential input voltage between the analog inputs. Thus, the
differential input voltage range when REF/2 is open and VCC = 5 V is 0 V to 5 V. VREF/2 for an input voltage range from 0.5 V to 3.5 V
(full-scale differential voltage of 3 V) is 1.5 V.
4. These values are with respect to DGTL GND.
5. Total unadjusted error is specified only at an fclock of 640 kHz with a duty cycle of 40% to 60% (pulse duration 625 ns to 937 ns).
For frequencies above this limit or pulse duration below 625 ns, error may increase. The duty cycle limits should be observed for
an fclock greater than 640 kHz. Below 640 kHz, this duty cycle limit can be exceeded provided tw(CLK) remains within limits.
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ADC0803, ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986
electrical characteristics over recommended range of operating free-air temperature, VCC = 5 V,
fclock = 640 kHz, VREF/2 = 2.5 V (unless otherwise noted)
PARAMETER
VOH
High level output voltage
High-level
VOL
Low-level output voltage
TYP†
TEST CONDITIONS
MIN
VCC = 4.75 V,
VCC = 4.75 V,
IOH = – 360 µA
IOH = – 10 µA
2.4
VCC = 4.75 V,
VCC = 4.75 V,
IOL = 1.6 mA
IOL = 1 mA
0.4
INTR output
CLK OUT
VCC = 4.75 V,
IOL = 360 µA
0.4
All outputs
DB and INTR
Data outputs
MAX
UNIT
V
4.5
0.4
V
VT+
VT–
Clock positive-going threshold voltage
2.7
3.1
3.5
V
Clock negative-going threshold voltage
1.5
1.8
2.1
V
VT+ – VT–
IIH
Clock input hysteresis
0.6
IIL
Low-level input current
High-level input current
1.3
2
V
0.005
1
µA
– 0.005
–1
µA
VO = 0
VO = 5 V
–3
µA
IOZ
Off state output current
Off-state
IOHS
IOLS
Short-current output current
Output high
Short-circuit output current
Output low
ICC
RREF/2
Supply current plus reference current
Ci
Input capacitance (control)
5
7.5
pF
Co
Output capacitance (DB)
5
7.5
pF
Input resistance to reference ladder
3
VO = 0,
VO = 5 V,
TA = 25°C
TA = 25°C
VREF/2 = open,
See Note 6
TA = 25°C,
– 4.5
–6
9
16
CS = 5 V
mA
mA
1.1
2.5
1.8
8
mA
kΩ
NOTE 6: Resistance is calculated from the current drawn from a 5-V supply applied to ANLG GND and REF/2.
operating characteristics over recommended operating free-air temperature, VCC = 5 V,
VREF/2 = 2.5 V, fclock = 640 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Supply-voltage-variation error
VCC = 4.5 to 5.5 V,
TYP†
MAX
UNIT
+1/16
±1/8
LSB
±1/4
Total adusted error
ADC0803
With full
full-scale
scale adjust
adjust,
See Notes 7 and 8
Total unadjusted error
ADC0805
VREF/2 = 2.5 V,
VREF/2 open,
See Notes 7 and 8
±1/2
See Notes 7 and 8
±1
LSB
±1/16
±1/8
LSB
135
200
ns
125
200
ns
300
450
nx
73
clock
cycles
DC common-mode error
See Notes 7 and 8
ten
tdis
Output enable time
TA = 25°C,
TA = 25°C, CL = 10 pF,
td(INTR)
Delay time to reset INTR
tconv
See Note 7
MIN
Output disable time
Conversion cycle time
CL = 100 pF
RL = 10 kΩ
TA = 25°C
fclock = 100 kHz to 1.46 MHz,
TA = 25°C,
INTR connected to WR,
See Note 9
±1/2
LSB
CR
Free-running conversion rate
CS at 0 V
66
8770 conv/s
† All typical values are at TA = 25°C.
NOTES: 7. These parameters are specified over the recommended analog input voltage range.
8. All errors are measured with reference to an ideal straight line through the end-points of the analog-to-digital transfer characteristics.
9. Although internal conversion is completed in 64 clock periods, a CS or WR low-to-high transition is followed by 1 to 8 clock periods
before conversion starts. After conversion is complete, part of another clock period is required before a high-to-low transition of INTR
completes the cycle.
4
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• DALLAS, TEXAS 75265
ADC0803, ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986
PARAMETER MEASUREMENT INFORMATION
CS
8 Clock Periods (Min)
50%
RD
50%
td(INTR)
INTR
50%
50%
tdis
ten
VOH
90%
DATA
OUTPUTS
50%
High-Impedance State
10%
VOL
Figure 1. Read Operation Timing Diagram
CS
WR
50%
50%
td(INTR)
1 to 8
Clock Periods
64% Clock Periods
tw(WR)
INTR
50%
50%
t CONV
Figure 2. Write Operation Timing Diagram
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5
ADC0803, ADC0805
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH DIFFERENTIAL INPUTS
SLAS034 – NOVEMBER 1983 – REVISED SEPTEMBER 1986
PRINCIPLES OF OPERATION
The ADC0803 and ADC0805 each contain a circuit equivalent to 256-resistor network. Analog switches are
sequenced by successive-approximation logic to match an analog differential input voltage (VI + – VI –) to a
corresponding tap on the 256R network. The most significant bit (MSB) is tested first. After eight spelled out
comparisons (64 clock periods), an eight-bit binary code (1111 1111 = full scale) is transferred to an output latch and
the interrupt (INTR) output goes low. The device can be operated in a free-running mode by connecting the INTR
output to the write (WR) input and holding the conversion start (CS) input at a low level. To ensure start up under all
conditions, a low-level WR input is required during the power-up cycle. Taking CS low any time after that will interrupt
a conversion in process.
When WR goes low, the internal successive-approximation register (SAR) and 8-bit shift register are reset. As long
as both CS and WR remain low, the analog-to-digital converter remains in a reset state. One to eight clock periods
after CS or WR makes a low-to-high transition, conversion starts.
When CS and WR are low, the start flip-flop is set and the interrupt flip-flop and 8-bit register are reset. The next clock
pulse transfers a logic high to the output of the start flip-flop. The logic high is ANDed with the next clock pulse, placing
a logic high on the reset input of the start flip-flop. If either CS or WR have gone high, the set signal to the start flip-flop
is removed, causing it to be reset. A logic high is placed on the D input of the eight-bit shift register and the conversion
process is started. If CS and WR are still low, the start flip-flop, the 8-bit shift register, and the SAR remain reset.
This action allows for wide CS and WR inputs, with conversion starting from one to eight clock periods after one of
the inputs goes high.
When the logic high input has been clocked through the 8-bit shift register, which completes the SAR search, it is
applied to an AND gate controlling the output latches and to the D input of a flip-flop. On the next clock pulse, the digital
word is transferred to the 3-state output latches and the interrupt flip-flop is set. The output of the interrupt flip-flop
is inverted to provide an INTR output that is high during conversion and low when the conversion is complete.
When a low is at both CS and RD, an output is applied to the DB0 through DB7 outputs and the interrupt flip-flop is
reset. When either CS or RD return to a high state, the DB0 through DB7 outputs are disabled (returned to the
high-impedance state). The interrupt flip-flop remains reset.
6
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