ATMEL AT28LV010-25JC 1 megabit 128k x 8 low voltage paged cmos e2prom Datasheet

AT28LV010
Features
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Single 3.3V ± 10% Supply
Fast Read Access Time - 200 ns
Automatic Page Write Operation
Internal Address and Data Latches for 128-Bytes
Internal Control Timer
Fast Write Cycle Time
Page Write Cycle Time - 10 ms Maximum
1 to 128-Byte Page Write Operation
Low Power Dissipation
15 mA Active Current
20 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Endurance: 100,000K Cycles
Data Retention: 10 Years
JEDEC Approved Byte-Wide Pinout
Commercial and Industrial Temperature Ranges
1 Megabit
(128K x 8)
Low Voltage
Paged CMOS
E2PROM
Description
The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Programmable Read Only Memory. Its 1 megabit of memory is organized as 131,072 words
by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the
device offers access times to 200 ns with power dissipation of just 54 mW. When the
device is deselected, the CMOS standby current is less than 20 µA.
(continued)
Pin Configurations
Pin Name
Function
A0 - A16
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data
Inputs/Outputs
NC
No Connect
DC
Don’t Connect
PDIP
Top View
AT28LV010
PLCC
Top View
TSOP
Top View
0395A
2-155
Description (Continued)
The AT28LV010 is accessed like a Static RAM for the
read or write cycle without the need for external components. The device contains a 128-byte page register to allow writing of up to 128-bytes simultaneously. During a
write cycle, the address and 1 to 128-bytes of data are
internally latched, freeing the address and data bus for
other operations. Following the initiation of a write cycle,
the device will automatically write the latched data using
an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a read or write
can begin.
Atmel’s 28LV010 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved
data retention characteristics. Software data protection is
implemented to guard against inadvertent writes. The device also includes an extra 128-bytes of E2PROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias................. -55°C to +125°C
Storage Temperature...................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
2-156
AT28LV010
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
AT28LV010
Device Operation
READ: The AT28LV010 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus
contention in their system.
TOGGLE BIT: In addition to DATA Polling the AT28LV010
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
WRITE: The write operation of the AT28LV010 allows 1 to
128-bytes of data to be written into the device during a
single internal programming period. Each write operation
must be preceded by the software data protection (SDP)
command sequence. This sequence is a series of three
unique write command operations that enable the internal
write circuitry. The command sequence and the data to be
written must conform to the software protected write cycle
timing. Addresses are latched on the falling edge of WE or
CE, whichever occurs last and data is latched on the rising
edge of WE or CE, whichever occurs first. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28LV010 will
cease accepting data and commence the interal programming operation. If more than one data byte is to be written
during a single programming operation, they must reside
on the same page as defined by the state of the A7 - A16
inputs. For each WE high to low transition during the page
write operation, A7 - A16 must be the same.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
The A0 to A6 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period.
Only bytes which are specified for writing will be written;
unnecessary cycling of other bytes within the page does
not occur.
DATA POLLING: The AT28LV010 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed,
true data is valid on all outputs, and the next write cycle
may begin. DATA Polling may begin at anytime during the
write cycle.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28LV010 in the following ways: (a) VCC power-on delay - once VCC has reached
2.0V (typical) the device will automatically time out 5 ms
(typical) before allowing a write: (b) write inhibit - holding
any one of OE low, CE high or WE high inhibits write cycles; (c) noise filter - pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: The AT28LV010 incorporates the industry standard software data protection
(SDP) function. Unlike standard 5-volt only E2PROM’s,
the AT28LV010 has SDP enabled at all times. Therefore,
all write operations must be preceded by the SDP command sequence.
The data in the 3-byte command sequence is not written
to the device; the addresses in the command sequence
can be utilized just like any other location in the device.
Any attempt to write to the device without the 3-byte sequence will start the internal timers. No data will be written
to the device. However, for the duration of tWC, read operations will effectively be polling operations.
2-157
DC and AC Operating Range
Operating
Temperature (Case)
Com.
Ind.
VCC Power Supply
AT28LV010-20
AT28LV010-25
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
3.3V ± 5%
3.3V ± 10%
Operating Modes
Mode
CE
OE
WE
I/O
Read
VIL
VIL
VIH
DOUT
Write (2)
VIL
VIH
VIL
DIN
VIH
(1)
Standby/Write Inhibit
X
X
High Z
Write Inhibit
X
X
VIH
Write Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Z
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
ILI
Input Load Current
VIN = 0V to VCC
1
µA
ILO
Output Leakage Current
VI/O = 0V to VCC
1
µA
ISB
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC + 1V
Com.
20
µA
Ind.
50
µA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA; VCC = 3.6V
15
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6 mA; VCC = 3.0V
VOH
Output High Voltage
IOH = -100 µA; VCC = 3.0V
2-158
AT28LV010
2.0
V
.45
2.4
V
V
AT28LV010
AC Read Characteristics
AT28LV010-20
Symbol
Parameter
tACC
Min
Max
AT28LV010-25
Min
Max
Units
Address to Output Delay
200
250
ns
tCE
(1)
CE to Output Delay
200
250
ns
tOE
(2)
OE to Output Delay
0
80
0
100
ns
tDF
(3, 4)
CE or OE to Output Float
0
55
0
60
ns
Output Hold from OE, CE or
Address, whichever occurred
first
0
tOH
0
ns
AC Read Waveforms (1, 2, 3, 4)
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first
(CL = 5pF).
4. This parameter is characterized and is not 100% tested.
Output Test Load
Input Test Waveforms and
Measurement Level
tR, tF < 5 ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ
Max
Units
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
Conditions
1. This parameter is characterized and is not 100% tested.
2-159
AC Write Characteristics (1)
Symbol
Parameter
tAS, tOES
Address, OE Set-up Time
tAH
Address Hold Time
tCS
Min
Max
Units
0
ns
100
ns
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
200
ns
tDS
Data Set-up Time
100
ns
tDH, tOEH
Data, OE Hold Time
10
ns
Note:
1. All write operations must be preceded by the SDP command sequence.
AC Write Waveforms
WE Controlled
CE Controlled
2-160
AT28LV010
AT28LV010
Software Protected Write Characteristics
Symbol
Parameter
Min
tWC
Write Cycle Time
tAS
Address Set-up Time
tAH
Max
Units
10
ms
0
ns
Address Hold Time
100
ns
tDS
Data Set-up Time
100
ns
tDH
Data Hold Time
10
ns
tWP
Write Pulse Width
200
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
150
100
µs
ns
Programming Algorithm
LOAD DATA AA
TO
ADDRESS 5555
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Data protect state will be re-activated at the end of program
cycle.
3. 1 to 128-bytes of data are loaded.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED (2)
LOAD DATA XX
TO
ANY ADDRESS (3)
LOAD LAST BYTE
TO
LAST ADDRESS (3)
ENTER DATA
PROTECT STATE
Software Protected Program Cycle Waveforms (1, 2, 3)
Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3-bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A7 - A16)
must be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
2-161
Data Polling Characteristics (1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Typ
Max
10
ns
10
ns
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Units
ns
0
Notes: 1. These parameters are characterized and not 100% tested.
ns
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics (1)
Symbol
Parameter
Min
Typ
Max
Units
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay (2)
tOEHP
OE High Pulse
tWR
Write Recovery Time
ns
150
ns
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms
Notes: 1. Toggling either OE or CE or both OE and CE will
operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
2-162
AT28LV010
3. Any address location may be used but the
address should not vary.
AT28LV010
Ordering Information (1)
tACC
ICC (mA)
Ordering Code
Package
0.2
AT28LV010-20JC
AT28LV010-20PC
AT28LV010-20TC
32J
32P6
32T
Commercial
(0° to 70°C)
15
0.2
AT28LV010-20JI
AT28LV010-20PI
AT28LV010-20TI
32J
32P6
32T
Industrial
(-40° to 85°C)
15
0.2
AT28LV010-25JC
AT28LV010-25PC
AT28LV010-25TC
32J
32P6
32T
Commercial
(0° to 70°C)
15
0.2
AT28LV010-25JI
AT28LV010-25PI
AT28LV010-25TI
32J
32P6
32T
Industrial
(-40° to 85°C)
(ns)
Active
Standby
200
15
250
Operation Range
Note: 1. See Valid Part Number table below.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
Speed
Package and Temperature Combinations
AT28LV010
20
JC, JI, PC, PI, TC, TI
AT28LV010
25
JC, JI, PC, PI, TC, TI
Package Type
32J
32 Lead, Plastic J-Leaded Chip Carrier (PLCC)
32P6
32 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32 Lead, Plastic Thin Small Outline Package (TSOP)
2-163
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