Cypress CY62138EV30LL-45BVXI 2 mbit (256k x 8) mobl static ram Datasheet

CY62138EV30 MoBL®

2 Mbit (256K x 8) MoBL Static RAM
Features
Functional Description
■
Very high speed: 45 ns
❐ Wide voltage range: 2.20 V to 3.60 V
The CY62138EV30[1] is a high performance CMOS static RAM
organized as 256K words by eight bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. The device can be put into standby mode reducing
power consumption when deselected (CE HIGH).
■
Pin compatible with CY62138CV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconducor (CMOS) for
optimum speed and power
■
Offered in Pb-free 36-ball ball grid array (BGA) package
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Logic Block Diagram
I/O0
Data in Drivers
I/O1
256K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A
A6
A87
A
A109
A11
I/O3
I/O4
I/O5
COLUMN
DECODER
CE
I/O6
POWER
DOWN
I/O7
A12
A13
A14
A15
A16
A17
WE
OE
Note
1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05577 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 17, 2011
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CY62138EV30 MoBL®
Contents
Pin Configuration .............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Electrical Characteristics4..................................................
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 5
Data Retention Waveform ................................................ 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 6
Document #: 38-05577 Rev. *C
Ordering Information ........................................................ 9
Ordering Code Definition ............................................. 9
Package Diagram ............................................................ 10
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Document History Page ................................................. 11
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC Solutions ......................................................... 12
Page 2 of 12
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CY62138EV30 MoBL®
Pin Configuration[2]
FBGA
Top View
A0
A1
NC
A3
A6
A8
A
I/O4
A2
WE
A4
A7
I/O0
B
NC
A5
I/O1
C
VSS
Vcc
D
VCC
Vss
E
I/O2
F
I/O5
I/O6
NC
A17
I/O7
OE
CE
A16
A15
I/O3
G
A9
A10
A11
A12
A13
A14
H
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62138EV30LL
Speed
(ns)
Min
Typ[3]
Max
2.2
3.0
3.6
45
Operating ICC (mA)
f = 1 MHz
Standby ISB2 (A)
f = fmax
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
2
2.5
15
20
1
7
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
Document #: 38-05577 Rev. *C
Page 3 of 12
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CY62138EV30 MoBL®
Maximum Ratings
DC input voltage[4,5]...................... –0.3 V to VCC(MAX) + 0.3 V
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ............................................. 55 °C to +125 °C
Supply voltage to ground
potential ....................................... –0.3 V to VCC(MAX) + 0.3 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ..................................................... > 200 mA
Product
Ambient
Temperature
Range
CY62138EV30LL
VCC[6]
Industrial –40 °C to +85 °C 2.2 V to 3.6 V
DC voltage applied to outputs
in High Z state[4,5] ......................... –0.3 V to VCC(MAX) + 0.3 V
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Test Conditions
CY62138EV30-45
Unit
Min
Typ[7]
Max
IOH = –0.1 mA VCC = 2.20 V
2.0
–
–
V
IOH = –1.0 mA VCC = 2.70 V
2.4
–
–
V
IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
V
IOL = 2.1 mA
VCC = 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3V
V
VCC= 2.7 V to 3.6 V
2.2
–
VCC + 0.3V
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC,
Output disabled
–1
–
+1
A
ICC
VCC Operating supply
current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
–
15
20
mA
f = 1 MHz
–
2
2.5
mA
ISB1[8]
Automatic CE power
down current — CMOS
inputs
CE > VCC –0.2 V, VIN > VCC – 0.2 V,
VIN < 0.2 V), f = fmax (Address and
data only), f = 0 (OE, and WE),
VCC = 3.60 V
–
1
7
A
ISB2 [8]
Automatic CE power
down current — CMOS
inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
1
7
A
Notes
4. VIL(min.) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min.) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
8. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
Document #: 38-05577 Rev. *C
Page 4 of 12
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CY62138EV30 MoBL®
Capacitance
Parameter[9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ.)
Unit
10
pF
10
pF
Thermal Resistance
Parameter[9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
BGA
Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
72
C / W
8.86
C / W
Figure 1. AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
OUTPUT
VCC
R2
30 pF
GND
90%
10%
90%
10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.50 V
3.0 V
Unit
R1
R2
16667
1103

15385
1554

RTH
VTH
8000
645

1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min
Typ[10]
Max
Unit
1
–
–
V
–
0.8
3
A
VDR
VCC for data retention
ICCDR [11]
Data retention current
tCDR[9]
Chip deselect to data retention time
0
–
–
ns
tR[12]
Operation recovery time
45
–
–
ns
VCC = 1V, CE > VCC 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC (min.)
tCDR
VDR > 1.5 V
1.5 V
tR
CE
Notes
9. Tested initially and after any design or process changes that may affect these parameters.
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
11. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
12. Full device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.)  100 s.
Document #: 38-05577 Rev. *C
Page 5 of 12
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CY62138EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter[13]
45 ns
Description
Min
Max
45
–
Unit
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to Low Z[14]
5
–
ns
tHZOE
OE HIGH to High Z[14,15]
–
18
ns
tLZCE
CE LOW to Low Z[14]
10
–
ns
tHZCE
CE HIGH to High Z[14,15]
–
18
ns
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to power-up
–
45
ns
tWC
Write cycle time
45
–
ns
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to High Z[14,15]
–
18
ns
tLZWE
WE HIGH to Low Z
10
–
ns
ns
Write Cycle[16]
[14]
Switching Waveforms
Figure 2. Read Cycle No. 1: Address Transition Controlled [17, 18]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes
13. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2,
input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms.
14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
15. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
16. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
17. Device is continuously selected. OE, CE = VIL.
18. WE is HIGH for read cycle.
Document #: 38-05577 Rev. *C
Page 6 of 12
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CY62138EV30 MoBL®
Switching Waveforms
(continued)
Figure 3. Read Cycle No. 2: OE Controlled [19, 20]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
Figure 4. Write Cycle No. 1: WE Controlled
ICC
ISB
[21, 23]
tWC
ADDRESS
tSCE
CE
tAW
tSA
WE
tHA
tPWE
OE
tSD
DATA I/O
NOTE 22
tHD
DATAIN VALID
tHZOE
Notes
19. WE is HIGH for read cycle.
20. Address valid prior to or coincident with CE transition LOW.
21. Data I/O is high impedance if OE = VIH.
22. During this period, the I/Os are in output state and input signals should not be applied.
23. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
Document #: 38-05577 Rev. *C
Page 7 of 12
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CY62138EV30 MoBL®
Switching Waveforms
(continued)
Figure 5. Write Cycle No. 2 CE Controlled [24, 25]
tWC
ADDRESS
tSCE
CE
tHA
tSA
tAW
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
Figure 6. Write Cycle No. 3 : WE Controlled, OE LOW [25]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 26
tLZWE
tHZWE
Truth Table
CE
WE
OE
[27]
X
X
High Z
Deselect/power-down
Standby (ISB)
L
H
L
Data out (I/O0–I/O7)
Read
Active (ICC)
L
H
H
High Z
Output disabled
Active (ICC)
L
L
X
Data in (I/O0–I/O7)
Write
Active (ICC)
H
Inputs/Outputs
Mode
Power
Notes
24. Data I/O is high impedance if OE = VIH
25. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
26. During this period, the I/Os are in output state and input signals should not be applied.
27. Chip enable (CE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
Document #: 38-05577 Rev. *C
Page 8 of 12
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CY62138EV30 MoBL®
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
45
CY62138EV30LL-45BVXI
51-85149
36-Ball Very Fine Pitch BGA (6 mm × 8 mm × 1 mm) (Pb-free)
Industrial
Ordering Code Definition
CY
621
3
8E
V30
LL
45
XXX
X
Temperature Grades
I = Industrial
Package Type BVX: VFBGA (Pb-free)
Speed Grade
Low Power
Voltage Range = 3 V typical
Bus Width = X8
E = 90nm Technology
Density = 2 Mbit
MoBL SRAM Family
Company ID: CY = Cypress
Document #: 38-05577 Rev. *C
Page 9 of 12
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CY62138EV30 MoBL®
Package Diagram
Figure 7. 36-Ball VFBGA (6 x 8 x 1 mm) (51-85149)
51-85149-*D
Acronyms
Document Conventions
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
Symbol
I/O
input/output
SRAM
Acronym
Unit of Measure
°C
degrees Celsius
static random access memory
A
microamperes
VFBGA
very fine ball gird array
mA
milliampere
TSOP
thin small outline package
MHz
megahertz
Document #: 38-05577 Rev. *C
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Page 10 of 12
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CY62138EV30 MoBL®
Document History Page
Document Title: CY62138EV30 MoBL® 2 Mbit (256K x 8) MoBL Static RAM
Document Number: 38-05577
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
237432
AJU
See ECN
New data sheet
*A
427817
NXR
See ECN
Removed 35 ns Speed Bin
Removed “L” version
Removed 32-pin TSOPII package from product Offering.
Changed ball C3 from DNU to NC.
Removed the redundant footnote on DNU.
Moved Product Portfolio from Page # 3 to Page #2.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f = 1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax=1/tRC
Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values
from 2.5 A to 7 A.
Changed VCC stabilization time in footnote #7 from 100 s to 200 s
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed VDR from 1.5V to 1V on Page# 4.
Changed ICCDR from 1 A to 3 A in the Data Retention Characteristics table
on Page # 4.
Corrected tR in Data Retention Characteristics from 100 s to tRC ns
Changed tOHA, tLZCE, tLZWE from 6 ns to 10 ns
Changed tHZOE, tHZCE, tHZWE from 15 ns to 18 ns
Changed tLZOE from 3 ns to 5 ns
Changed tSCE and tAW from 40 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Changed tPWE from 25 ns to 35 ns
Updated the Ordering Information table and replaced Package Name
column with Package Diagram.
*B
2604685
VKN/PYRS
11/12/08
Added footnote 7 related to ISB2 and ICCDR
*C
3143896
RAME
01/17/2011
Document #: 38-05577 Rev. *C
Updated Datasheet as per new template
Added Ordering Code Definition
Added Acronyms and Units of Measure table
Converted all tablenotes to Footnote
Updated Package Diagram 51-85149 from *C to *D
Page 11 of 12
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CY62138EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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cypress.com/go/powerpsoc
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© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05577 Rev. *C
Revised January 17, 2011
Page 12 of 12
All products and company names mentioned in this document may be the trademarks of their respective holders.
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