Intersil CA3193 1.2mhz, bicmos precision operational amplifier Datasheet

®
January 1998
Features
CA3193, CA3193A
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Description
cont -INTERS
8
8
8
1The CA3193A and CA3193 are ultra-stable, precision
• Low VIO
- CA3193A . . . . . . . . . . . . . . . . . . . . . . . . . .200µV (Max)
- CA3193 . . . . . . . . . . . . . . . . . . . . . . . . . . .500µV (Max)
instrumentation, operational amplifiers that employ both
PMOS and bipolar transistors on a single monolithic chip.
The CA3193A and CA3193 amplifiers are internally phase
compensated and provide a gain bandwidth product of
1.2MHz. They are pin compatible with the industry 741
series and many other IC op amps, and may be used as
replacements for 741 series types in most applications.
• Low ∆VIO/∆T
- CA3193A . . . . . . . . . . . . . . . . . . . . . . . . . 3µV/oC (Max)
- CA3193 . . . . . . . . . . . . . . . . . . . . . . . . . . 5µV/oC (Max)
• Low IIO and II
The CA3193A and CA3193 can also be used as functional
replacements for op amp types 725, 108A, OP-5, OP-7,
LM11 and LM714 in many applications where nulling is not
employed. Because of their low offset voltage and low offset
voltage vs temperature coefficient the CA3193A and
CA3193 amplifiers have a wider range of applications than
most op amps and are particularly well suited for use as
thermocouple amplifiers, high gain filters, buffer, strain
gauge bridge amplifiers and precision voltage references.
• Low ∆IIO/∆T: CA3193. . . . . . . . . . . . . . .150pA/oC (Max)
• Low ∆II/∆T: CA3193 . . . . . . . . . . . . . . . . 3.7nA/oC (Max)
Applications
• Thermocouple Preamplifiers
• Strain Gauge Bridge Amplifiers
• Summing Amplifiers
The two types in the CA3193 series are functionally
identical. The CA3193A and CA3193 operate from supply
voltages of ±3.5V to ±18V.
• Differential Amplifiers
• Bilateral Current Sources
Part Number Information
• Log Amplifiers
• Differential Voltmeters
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
• Precision Voltage References
CA3193AE
• Active Filters
-25 to 85
8 Ld PDIP
E8.3
0 to 70
8 Ld PDIP
E8.3
CA3193E
• Buffers
• Integrators
• Sample-and-Hold Circuits
• Low Frequency Filters
Pinout
CA3193
(PDIP)
TOP VIEW
OFFSET NULL
1
INV. INPUT
2
NON-INV. INPUT
3
V-
4
+
8
NC
7
V+
6
OUTPUT
5
OFFSET NULL
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2002. All Rights Reserved
60
All other trademarks mentioned are the property of their respective owners.
FN1249.4
CA3193, CA3193A
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ -4), VInput Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . . . Indefinite
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
CA3193A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC
CA3193 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. Short circuit may be applied to ground or to either supply.
Electrical Specifications
TA = 25oC, VSUPPLY = ±15V, Unless Otherwise Specified
TEST
CONDITIONS
PARAMETER
Input Offset Voltage VIO
25oC
CA3193
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VIO
-
300
500
-
140
200
µV
-
-
725
-
-
380
µV
∆VIO/∆T
-
1
5
-
1
3
µV/oC
IIO
-
5
10
-
3
5
nA
-
-
17
-
-
11
nA
∆IIO/∆T
-
0.04
0.15
-
0.03
0.10
nA/oC
II
-
20
40
-
10
20
nA
-
-
207
-
-
83
nA
∆II/∆T
-
0.15
3.70
-
0.10
1.18
nA/oC
eN P-P
-
0.36
-
-
0.36
-
µVP-P
TMAX
Input Offset Voltage Temperature
Coefficient (Over Specified Temperature Range for Each Device)
Input Offset Current
25oC
TMAX
Input Offset Current Temperature
Coefficient (Over Specified Temperature Range for Each Device)
Input Bias Current
25oC
TMAX
Input Bias Current Temperature
Coefficient
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current
Input Noise Current Density
0.1 to 10Hz
f = 10Hz
-
25
-
-
25
-
nV/√Hz
f = 100Hz
-
25
-
-
25
-
nV/√Hz
f = 1000Hz
-
24
-
-
24
-
nV/√Hz
f = 10kHz
-
24
-
-
24
-
nV/√Hz
f = 100kHz
-
22
-
-
22
-
nV/√Hz
-
12
20
-
12
20
pAP-P
0.1 to 10 Hz
f = 10Hz
eN
IN P-P
-
0.83
-
-
0.83
-
pA/√Hz
f = 100Hz
-
0.80
-
-
0.80
-
pA/√Hz
f = 1000Hz
-
0.75
-
-
0.75
-
pA/√Hz
f = 10kHz
-
0.72
-
-
0.72
-
pA/√Hz
f = 100kHz
-
0.60
-
-
0.60
-
pA/√Hz
VICR
-12
-13.5
to 11.5
10
-12
-13.5
to 11.5
10
V
CMRR
100
110
-
110
115
-
dB
-
3.16
10
-
1.78
3.16
µV/V
Common-Mode Input Voltage
Range
Common-Mode Rejection Ratio
CA3193A
VCM = VICR
IN
Power Supply Rejection Ratio
∆VIO/∆V±
PSRR
100
130
-
100
130
-
dB
-
0.316
10
-
0.316
10
µV/V
Maximum Output Voltage Swing RL ≥ 2kΩ
RL ≥ 2kΩ
Large-Signal Voltage Gain
(VO = ±10)
R ≥ 10kΩ
VOM
±13.0
±13.5
-
±13.0
±13.5
-
V
AOL
100
110
-
110
115
-
dB
-
115
-
-
125
-
dB
L
61
CA3193, CA3193A
TA = 25oC, VSUPPLY = ±15V, Unless Otherwise Specified (Continued)
Electrical Specifications
CA3193
TEST
CONDITIONS
PARAMETER
Short-Circuit Output Current to
the Opposite Rail
CA3193A
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
IOM+, IOM-
-25
±7
25
-25
±7
25
mA
Slew Rate
RL ≥ 2kΩ, AV = +1
SR
-
0.25
-
-
0.25
-
V/µs
Gain-Bandwidth Product
AOL = 0dB, RL = 2kΩ,
CL = 100pF, VIN = 20mVP-P ,
f = 1kHz
fT
-
1.20
-
-
1.20
-
MHz
Rise and Fall Time
VIN = 20mVP-P, f = 1kHz
tR
-
0.29
-
-
0.29
-
µs
I+
-
2.3
3.5
-
2.3
3.5
mA
RL = ∞, VS = ±15V
Supply Current
Test Circuits and Waveforms
10K
V+
2
100Ω
3
+
7
V OUT
V IO = -------------100
+15V
6
VOUT
4
-15V
V-
FIGURE 1. INPUT OFFSET VOLTAGE TEST CIRCUIT
0
10K
+15V
10K
2
7
-
6
+10V
0V
3
+10V
VIN
1kHz
+
4
5K
0
VOUT
RL
10K
200pF
-15V
Top Trace: Input Voltage, Bottom Trace: Output Voltage
Vertical Scale: 10V/Div., Horizontal Scale: 0.1ms/Div.
VOUT = -VIN
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. RESPONSE TO 1kHz, 20VP-P SQUARE WAVE
FIGURE 2. INVERTING AMPLIFIER
10K
+15V
3
+
7
0V
2
+10V
VIN
-
0
6
+10V
VOUT
200pF
4
2K
-15V
SIMULATED
LOAD
0
Top Trace: Input Voltage; Bottom Trace: Output Voltage
Vertical Scale: 10V/Div.; Horizontal Scale: 0.1ms/Div.
FIGURE 3B. RESPONSE TO 20VP-P, 1kHz SQUARE WAVE INPUT
FIGURE 3A. TEST CIRCUIT
62
CA3193, CA3193A
Test Circuits and Waveforms
(Continued)
FIGURE 3. VOLTAGE FOLLOWER
LOW PASS
FILTER
DC TO 10Hz
+15V
2.2MΩ
1%
7
A
2
CA3193
4
100Ω
1%
B
3.3kΩ
1%
2.2µF
1%
4.7µF
1%
1MΩ
6
3
100Ω
1%
HIGH PASS
FILTER
0.1 TO 10Hz
SCOPE
INPUT
RESISTANCE
5
1
20kΩ
20kΩ
V OUT
P–P
V NOISE = ---------------------------3
22x10
1kΩ
-15V
FIGURE 4A. TEST CIRCUIT - 0.1Hz TO 10Hz
FIGURE 4B. OUTPUT A WAVEFORM - 0Hz TO 10Hz NOISE
FIGURE 4C. OUTPUT B WAVEFORM - 0.1Hz TO 10Hz NOISE
FIGURE 4. LOW FREQUENCY NOISE
Functional Block Diagram
2.3mA
BIAS NETWORK
950µA
3µA
7
660µA
70µA
+
V+
600µA
20pF
7.5K
3
INPUT
-
A ≈ 2000
25K
A ≈ 75
A≈7
A≈1
6
2
OUTPUT
6pF
1
5
OFFSET
NULL
4
V-
63
CA3193, CA3193A
Schematic Diagrams
Q12
25K
-
1K
Q1
D7
6pF
D8 Q13
Q30
INPUT
1K
D9
D2
3
OUTPUT
4
V-
60Ω
Q15
Q17
D1
6
60Ω
100Ω
20pF 7.5K
Q2
2
V+
Q14
Q8
Q7
7
Q16
Q19
Q18
680Ω
6K
D13
+
FIGURE 5. CA3193 SIMPLIFIED SCHEMATIC DIAGRAM
7
R1
3K
R2
3K
D4
R3
3K
Q11
V+
R4
120Ω
D3
D5
Q9
Q5
D6
Q3
Q4
R5
1.6K
Q8
Q7
R11
Q1
R6 D7
7.5K
Q20
Q21
D1
R12
Q16
R16
6K
R17
25K
D2
R14
3.7K
3
+
R10
60Ω
Q15
Q22 Q
23
INPUTS
100Ω
D8
2
1K
R8
Q13
6pF
R7
100K
Q2
6
R9
60Ω
Q12
20pF
-
OUTPUT
Q14
Q10
Q6
Q30
1K
Q17
D9
Q24 Q26
Q27
Q19
D10
Q25 Q28
Q29
D11
D12
Q18
D13
R15
680Ω
Q31
R13
15K
D14
4
5
1
OFFSET
NULL
FIGURE 6. SCHEMATIC DIAGRAM OF CA3193A AND CA3193
64
V-
CA3193, CA3193A
Application Information
Circuit Description
The block diagram of the CA3193 amplifier shows the
voltage gain and supply current for each of its four amplifier
stages. Simplified and complete schematic diagrams of the
CA3193 amplifier are shown in Figures 5 and 6, respectively.
(Q14 and Q15, Q16 in Figures 5 and 6). Output-stage shortcircuit protection is activated by voltage drops developed
across the 60Ω resistors adjacent to the output terminal (R9
and R10, Figure 6). When the voltage drop developed across
either of these resistors reaches a potential equal to 1 VBE,
the respective protective transistor (Q12 or Q13) is activated
and shunts the base drive from the bases of the output stage
transistors (Q14 and Q15, Q16).
A quad of physically cross-connected NPN transistors
comprise the input-stage differential pair (Q1, Q2 in Figures
5 and 6); this arrangement contributes to the low input offsetvoltage characteristics of the amplifier. The ultra-high gain
provided in the first stage ensures that subsequent stages
cannot significantly influence the overall offset-voltage
characteristics of the amplifier. High load impedances for the
input-stage differential pair (Q1, Q2) are provided by the
cascode-connected PNP transistors Q3, Q5 and Q4, Q6,
thereby contributing to the high gain developed in the stage.
Internal frequency compensation for the CA3193 amplifier is
provided by two internal networks, a 6pF capacitor
connected between the input-stage transistor collectors and
the node between the third and output stages and a second
network, consisting of a 20pF capacitor in series with a
7.5kΩ resistor connected between the input and output
nodes of the third stage.
The second stage of the amplifier consists of a differential
amplifier employing PMOS/FETs (Q7, Q8 in Figures 5 and 6)
with appropriate drain loading. Since Q7 and Q8 are
M0S/FETs, their loading on the first stage is quite low,
thereby making an additional contribution to the high gain
developed in the first stage. The second stage is also configured to convert its differential signal to a single-ended output
signal by means of current mirror D9, Q30 (Figures 5 and 6)
to drive subsequent gain stage.
Offset Voltage Nulling
The input offset voltage can be nulled to zero by any of the
three methods shown in the table below. A 10K potentiometer between terminals 1 and 5, with its wiper returned to V-,
will provide a gross nulling for all types. For finer nulling,
either of the other two circuits shown below may be used,
thus providing simpler improved resolution for all types.
CAUTION: The CA3193 amplifiers will be damaged if they are
plugged into op amp circuits employing nulling with respect to the
V+ supply bus.
The third stage of the amplifier consists of Darlingtonconnected NPN transistors (Q17, Q19 in Figures 5 and 6),
driving the quasi-complementary Class AB output stage
Offset Voltage Nulling
1
V-
V-
TYPE
1
5
1
R
5
R
R
R
OFFSET NULLING
CIRCUITS
V-
5
1K
10K
RESISTOR R VALUE
RESISTOR R VALUE
RESISTOR R VALUE
CA3193A
10K
50K
10K
CA3193
10K
20K
5K
Gross Offset Adjustment
Finer Offset Adjustments
65
CA3193, CA3193A
Typical Applications
+15V
a
V+
Va 3
2
R
R
R2
7
+
-
+15V
R1
1K
4
-15V
R2
9K
R + ∆R
R
20K
6
CA3193
R1
V1
R3
1K
V2
2
10K
R3
10K
7
-
6
CA3193
3
+
RL
4
R4
20K
-15V
+15V
2
-
CA3193
3
b
R4
9K
7
6
ALL RESISTANCE VALUES ARE IN OHMS.
 R 4   R 1 + R 2
 R 2
V OUT = V 2  ---------------------  --------------------- – V 1  -------
R
R
+
R
 3
 R 1
4 
1 
VOUT
+
4
Vb
VOUT
-15V
R2
R4
If R 4 = R 2 , R 3 = R 1 and ------- = ------R1
R3
 R2
 R4
 R4

V OUT = – V a  ------- + 1 ------- + V b  ------- + 1
R
R
R
 1
 3
 3

 R 2
THEN V OUT = ( V 2 – V 1 )  -------
 R 1
R3
R1
For Ideal Resistors with ------- = ------R2
R4
For values above VOUT = 2(V2 - V1):
 R4

V OUT = V b – V a  ------- + 1
 R3

If AV is To be made 1 and if R1 = R3 = R4 = R
with R2 = 0.999R (0.1% mismatch in R2)
V OUT
 R4

A = -------------------- =  ------- + 1
Vb – Va
 R3

Then VOCM = 0.0005 VIN or CMRR = 66dB
Thus, the CMRR of this circuit is limited by
the matching or mismatching of this network
rather than the amplifier.
FOR VALUES ABOVE VOUT = (Vb - Va) (IO)
FIGURE 7. TYPICAL TWO OP AMP BRIDGE-TYPE
DIFFERENTIAL AMPLIFIER
FIGURE 8. DIFFERENTIAL AMPLIFIER (SIMPLE
SUBTRACTER) USING CA3193
R2
1M
V3
2
3
R1
2M
R3
2MΩ
-
7
CA3193
+
4
RF
10K
+15V
6
-15V
R3
V2
IL
10K
R5
1K
+15V
V1
R4
1M
RS
20K
R2
R1
2
10K
3
RL
(0Ω TO 3.0kΩ)
WITH V = 1V
-
CA3193
+
R4
2.8K
V
ALL RESISTORS ARE 1%
IF R1 = R3 AND R2 ≈ R4 + R5, THEN
IL IS INDEPENDENT OF VARIATIONS IN RL
FOR RL VALUES OF 0Ω TO 3kΩ WITH V = 1V
7
6
4
RL
-15V
RF
RF 
 RF
V OUT = –  ------- V 1 + ------- V 2 + -------V 3
R
R
R3 
 1
2
VR 4
V
V ( 1M )
I L = --------------- = -------------------------- = ------- = 500µA
2K
( 2M ) ( 1K )
R 3 R5
VOUT = - (2V1+ 2V2 + 2V3)
ALL RESISTANCE VALUES ARE IN OHMS.
FIGURE 9. USING CA3193 AS A BILATERAL CURRENT
SOURCE
FIGURE 10. TYPICAL SUMMING AMPLIFIER APPLICATION
66
CA3193, CA3193A
Typical Applications
(Continued)
V+
+15V
22M
22M
22M
7
3
+
10K
2
4
0.1µF
VOUT
5
1
THERMOCOUPLE
6
CA3193
-15V
8.2K
20K
20K
499K
2K
1K
10K
1K
0-1mA
ALL RESISTORS ARE 1%.
ALL RESISTORS ARE IN OHMS.
FIGURE 11. THE CA3193 USED IN A THERMOCOUPLE CIRCUIT
The CA3193 is an excellent choice for use with
thermocouples. In Figure 11, the CA3193 amplifies the
generated signal 500 times. The three 22MΩ resistors will
provide full-scale output if the thermocouple opens.
Typical Performance Curves
300
CA3193
INPUT OFFSET VOLTAGE (µV)
400
INPUT OFFSET VOLTAGE ( µV)
CA3193 (0oC to 70oC)
300
CA3193A (-25oC to 85oC)
200
200
CA3193A
100
100
0
0
500
1000
1500
TIME AT AMBIENT TEMPERATURE = 125oC (HOURS)
0
-50
0
50
100
0
150
385
770
1155
EQUIVALENT TIME AT TEMPERATURE = 25oC (DAYS)
TEMPERATURE (oC)
FIGURE 12. TYPICAL INPUT OFFSET VOLTAGE
TEMPERATURE CHARACTERISTIC
FIGURE 13. INPUT OFFSET VOLTAGE vs TIME
67
CA3193, CA3193A
Typical Performance Curves
(Continued)
8
INPUT OFFSET CURRENT (nA)
INPUT BIAS CURRENT (nA)
40
30
20
CA3193 (0oC to 70oC)
10
CA3193A (-25oC to 85oC)
0
-50
6
4
CA3193
2
CA3193A
0
0
50
100
-50
150
0
TEMPERATURE (oC)
102
10
eN
1
iN
1
101
0.1
102
103
FREQUENCY (Hz)
104
5
POWER SUPPLY CURRENT (mA)
102
TA = 25oC
101
3
2
2
6
10
14
18
22
POWER SUPPLY VOLTAGE (±V)
FIGURE 17. POWER SUPPLY CURRENT vs SUPPLY VOLTAGE
150
TA = 25oC
-50
AOL
50
40
φ OL
0
100
OPEN LOOP GAIN (dB)
80
0
PHASE ANGLE (DEGREE)
OPEN LOOP GAIN (dB)
120
TA = -55oC TO 125oC
1
-100
TA = 25oC
150
4
105
FIGURE 16. INPUT NOISE VOLTAGE AND CURRENT DENSITY
vs FREQUENCY
160
100
FIGURE 15. TYPICAL INPUT OFFSET CURRENT vs
TEMPERATURE
EQUIVALENT INPUT NOISE CURRENT (pA/√Hz)
EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz)
FIGURE 14. TYPICAL INPUT BIAS CURRENT vs TEMPERATURE
103
50
TEMPERATURE (oC)
140
130
120
150
-40
200
-80
0.1
101
103
105
FREQUENCY (Hz)
110
2
107
6
10
14
18
POWER SUPPLY VOLTAGE (±V)
22
FIGURE 19. OPEN LOOP GAIN vs POWER SUPPLY VOLTAGE
FIGURE 18. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE
68
CA3193, CA3193A
Typical Performance Curves
(Continued)
140
TA = 25oC, UPPER SUPPLY VOLTAGE
FOR CA3193A AND CA3193 IS ±18V
INPUT AND OUTPUT EXCURSIONS
FROM TERMINAL 4 (V)
OPEN LOOP GAIN (dB)
4
130
120
CA3193A (-25oC to 85oC)
110
CA3193 (0oC to 70oC)
100
3
2
VOUT
1
VICR
0
-1
-2
-50
0
50
100
150
0
4
TEMPERATURE (oC)
8
12
16
20
SUPPLY VOLTAGE (±V)
40
TA = 25oC
1
RL = 2K
V+ = 15V
V- = -15V
35
30
25
20
15
10
5
0
1
101
102
103
104
28
FIGURE 21.
INPUT AND OUTPUT EXCURSIONS
FROM TERMINAL 7 (V)
MAXIMUM OUTPUT VOLTAGE SWING (VP-P)
FIGURE 20. OPEN LOOP GAIN vs TEMPERATURE
24
0
VOUT
-1
-2
VICR
-3
-4
-5
105
0
4
8
12
16
20
24
28
SUPPLY VOLTAGE (±V)
FREQUENCY (Hz)
FIGURE 22. MAXIMUM UNDISTORTED OUTPUT VOLTAGE vs
FREQUENCY
FIGURE 23. OUTPUT VOLTAGE SWING CAPABILITY AND
COMMON MODE INPUT VOLTAGE vs SUPPLY
VOLTAGE
69
CA3193, CA3193A
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
B
0.010 (0.25) M
A1
eC
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
N
8
0.355
10.16
5
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
8
10.92
7
3.81
4
9
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
70
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