Intersil CDP1823CE 128-word x 8-bit lsi static ram Datasheet

CDP1823,
CDP1823C
128-Word x 8-Bit
LSI Static RAM
March 1997
Features
Description
• Fast Access Time
- VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450ns
- VDD = 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns
The CDP1823 and CDP1823C are 128-word by 8-bit CMOS
SOS static random-access memories. These memories are
compatible with general-purpose microprocessors. The two
memories are functionally identical. They differ in that the
CDP1823 has a recommended operating voltage range of
4V to 10.5V, and the CDP1823C has a recommended operating voltage range of 4V to 6.5V.
• Common Data Inputs and Outputs
• Multiple Chip Select Inputs to Simplify Memory
System Expansion
Ordering Information
5V
10V
PACKAGE
TEMP. RANGE
PKG.
NO.
CDP1823CE
CDP1823E
PDIP
-40oC to +85oC E24.6
CDP1823CD
CDP1823D
SBDIP
-40oC to +85oC D24.6
CDP1823CDX
-
Burn-In
D24.6
The CDP1823 memory has 8 common data input and data
output terminals for direct connection to a bidirectional data
bus and is operated from a single voltage supply. Five chipselect inputs are provided to simplify memory-system expansion. In order to enable the CDP1823, the chip-select inputs
CS2, CS3 and CS5 require a low input signal, and the chipselect inputs CS1 and CS4 require a high input signal.
The MRD signal enables all 8 output drivers when in the low
state and should be in a high state during a write cycle.
After valid data appear at the output, the address inputs may
be changed immediately. Output data will be valid until either
the MRD signal goes high, the device is deselected, or tAA
(access time) after address changes.
Pinout
CDP1823, CDP1823C
(PDIP, SBDIP)
TOP VIEW
BUS 0
1
BUS 1
2
24 VDD
23 MA0
BUS 2
3
22 MA1
BUS 3
4
21 MA2
BUS 4
5
20 MA3
BUS 5
6
19 MA4
BUS 6
7
18 MA5
BUS 7
8
17 MA6
CS1
9
16 MWR
CS2 10
15 MRD
CS3 11
14 CS5
VSS 12
13 CS4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-24
File Number
1198.2
CDP1823, CDP1823C
OPERATIONAL MODES
FUNCTION
MRD
MWR
CS1
CS2
CS3
CS4
CS5
Read
0
X
1
0
0
1
0
Storage State of Addressed Word
Write
1
0
1
0
0
1
0
Input High-Impedance
Stand-By (Active)
1
1
1
0
0
1
0
High Impedance
Not Selected
X
X
0
X
X
X
X
High Impedance
X
X
X
1
X
X
X
High Impedance
X
X
X
X
1
X
X
High Impedance
X
X
X
X
X
0
X
High Impedance
X
X
X
X
X
X
1
High Impedance
Logic 1 = High, Logic 0 = Low, X = Don’t Care
6-25
BUS TERMINAL STATE
CDP1823, CDP1823C
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1823C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range (TA)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Resistance (Typical)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
60
N/A
SBDIP Package . . . . . . . . . . . . . . . . . .
60
17
Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC
Maximum Junction Temperature
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Maximum Lead Temperature (During Soldering) . . . . . . . . . . 300oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions
should be selected so that operation is always within the following ranges:
LIMITS
CDP1823D
PARAMETER
Supply Voltage Range
Recommended Input Voltage Range
CDP1823CD
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
VSS
VDD
VSS
VDD
V
At TA = -40oC to +85oC, Except as Noted:
Static Electrical Specifications
CONDITIONS
LIMITS
CDP1823
CDP1823C
SYMBOL
VO
(V)
VIN
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
Quiescent Device
Current
IDD
-
0, 5
5
-
-
500
-
-
500
µA
-
0, 10
10
-
-
1000
-
-
-
µA
Output Low (Sink)
Current
IOL
0.4
0, 5
5
2
4
-
2
4
-
mA
0.5
0, 10
10
4.5
9
-
-
-
-
mA
Output High (Source)
Current
IOH
Output Voltage
Low-Level
VOL
Output Voltage
High-Level
Input Low Voltage
PARAMETER
Input High Voltage
Input Leakage Current
4.6
0, 5
5
-1
-2
-
-1
-2
-
mA
9.5
0, 10
10
-2.2
-4.4
-
-
-
-
mA
-
0, 5
5
-
0
0.1
-
0
0.1
V
-
0, 10
10
-
0
0.1
-
-
-
V
VOH
-
0, 5
5
4.9
5
-
4.9
5
-
V
-
0, 10
10
9.9
10
-
-
-
-
V
VIL
0.5, 4.5
-
5
-
-
1.5
-
-
1.5
V
0.5, 9.5
-
10
-
-
3
-
-
-
V
0.5, 9.5
-
5
3.5
-
-
3.5
-
-
V
0.5, 9.5
-
10
7
-
-
-
-
-
V
VIH
IIN
Any
Input
0, 5
5
-
-
±5
-
-
±5
µA
0, 10
10
-
-
±10
-
-
-
µA
-
4
8
-
4
8
mA
Operating Current
(Note 2)
IDD1
-
0, 5
5
-
0, 10
10
-
8
16
-
-
-
mA
Three-State Output
Leakage Current
IOUT
0, 5
0, 5
5
-
-
±5
-
-
±5
µA
0, 10
0, 10
10
-
-
±10
-
-
-
µA
CIN
-
-
-
-
5
7.5
-
5
7.5
pF
COUT
-
-
-
-
10
15
-
10
15
pF
Input Capacitance
Output Capacitance
NOTES:
1. Typical values are for TA = +25oC and nominal VDD.
2. Outputs open circuited; Cycle time = 1µs.
6-26
CDP1823, CDP1823C
Dynamic Electrical Specifications
At TA = -40 to +85oC, VDD ±5%, tR, tF = 20ns, CL = 100pF
LIMITS
CDP1823
PARAMETER
CDP1823C
SYMBOL
VDD
(V)
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
UNITS
tAA
5
-
275
450
-
275
450
ns
10
-
150
250
-
-
-
ns
5
-
150
250
-
150
250
ns
10
-
100
150
-
-
-
ns
5
-
150
250
-
150
250
ns
10
-
100
150
-
-
-
ns
5
25
50
75
25
50
75
ns
10
15
25
40
-
-
-
ns
Read Cycle (See Figure 1)
Access Time From Address
Change
Access Time From Chip
Select
MRD to Output Active
tDOA
tAM
Data Hold Time After Read
tDOH
NOTES:
1. Typical values are at TA = 25oC and nominal voltage.
2. Time required by a limit device to allow for the indicated function.
+
tAA
ADDRESS
tAM
MRD
CS2, CS3, CS5
tDOA
CS1, CS4
tDOH
90%
VALID DATA
DATA OUT
10%
HIGH IMPEDANCE
NOTE:
1. MWR is high during read operation. Timing measurement reference is 0.5 VDD.
FIGURE 1. READ CYCLE TIMING DIAGRAM
6-27
CDP1823, CDP1823C
At TA = -40 to +85oC, VDD ±5%, t R, tF = 20ns, CL = 100pF
Dynamic Electrical Specifications
LIMITS
CDP1823
PARAMETER
CDP1823C
SYMBOL
VDD
(V)
(NOTE 2)
MIN
(NOTE 1)
TYP
MAX
(NOTE 2) (NOTE 1)
MIN
TYP
tWR
5
75
-
-
75
10
50
-
-
5
400
-
10
225
5
MAX
UNITS
-
-
ns
-
-
-
ns
-
400
-
-
ns
-
-
-
-
-
ns
200
-
-
200
-
-
ns
10
100
-
-
-
-
-
ns
5
125
-
-
125
-
-
ns
10
75
-
-
-
-
-
ns
5
100
-
-
100
-
-
ns
10
75
-
-
-
-
-
ns
5
75
-
-
75
-
-
ns
10
50
-
-
-
-
-
ns
Write Cycle (See Figure 2)
Write Recovery
Write Cycle
tWC
Write Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time From MWR
tWRW
tAS
tDS
tDH
NOTES:
1. Typical values are at TA = 25oC and nominal voltage.
2. Time required by a limit device to allow for the indicated function.
tWC
tAS
ADDRESS
tWR
CS1, CS4
CS2, CS3, CS5
tWRW
MWR
tDS
BUS 0-7
VALID DATA
NOTE:
1. MRD must be high during write operation.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
6-28
tDH
CDP1823, CDP1823C
At TA = -40 to +85oC, see Figure 3
Data Retention Specifications
LIMITS
TEST
CONDITIONS
CDP1823
CDP1823C
VDR
(V)
VDD
(V)
MIN
(NOTE 1)
TYP
MAX
MIN
(NOTE 1)
TYP
MAX
UNITS
-
-
-
1.5
2
-
1.5
2
V
Data Retention Quiescent Current, IDD
2
-
-
30
100
-
30
100
µA
Chip Deselect to Data Retention Time
-
5
600
-
-
600
-
-
ns
-
10
300
-
-
-
-
-
ns
-
5
600
-
-
600
-
-
ns
-
10
300
-
-
-
-
-
ns
2
5
1
-
-
1
-
-
µs
PARAMETER
Minimum Data Retention Voltage,
VDR
tCDR
Recovery to Normal Operation
Time
VDD to VDR Rise and Fall Time
tRC
tR, tF
NOTE:
Typical values are for TA = 25oC and nominal VDD.
DATA RETENTION
MODE
VDD
0.95 VDD
0.95 VDD
VDR
tCDR
CS1
tF
tR
tRC
VIH
VIH
VIL
VIL
FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS
MA0
MA1
MA2
BUFFER
AND
DECODER
16 x 8 x 8
STORAGE
ARRAY
BUFFER
DECODER
MA3
MA4
MA5
MA6
MRD
MWR
CONTROL
CS1
CS2
CS3
BUS 0-7
CS4
CS5
FIGURE 4. FUNCTIONAL DIAGRAM
6-29
CDP1823, CDP1823C
CPU/ROM SYSTEM
RAM SYSTEM
RAM INTERFACE
ADDRESS
MA0- MA7
MA0 - MA7
MA0 - MA6
TPA
TPA
MRD
MRD
MRD
MWR
MWR
CPU
CDP1802
ROM
CDP1833
RAM
CDP1823
CS
CE0
BUS0 - BUS7
BUS0 - BUS7
BUS0 - BUS7
DATA
FIGURE 5. CDP1823 (128 x 8) MINIMUM SYSTEM (128 x 8)
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