Dallas DS1609 Dual port ram Datasheet

DS1609
DS1609
Dual Port RAM
FEATURES
PIN ASSIGNMENT
• Totally asynchronous 256–byte dual port memory
PORT A
PORT B
AD7A
1
24
VCC
AD6A
2
23
OEB
low
AD5A
3
22
CEB
• Dual
AD4A
4
21
WEB
AD3A
5
20
AD0B
AD2A
6
19
AD1B
AD1A
7
18
AD2B
AD0A
8
17
AD3B
WEA
9
16
AD4B
CEA
10
15
AD5B
OEA
11
14
AD6B
GND
12
13
AD7B
• Multiplexed address
and data bus keeps pin count
port memory cell allows random access with
minimum arbitration
• Each port has standard independent RAM control signals
• Fast access time
• Low power CMOS design
• 24–pin DIP or 24–pin SOIC surface mount package
DS1609
24–PIN DIP (600 MIL)
See Mech. Drawings
Section
• Both CMOS and TTL compatible
• Operating temperature of –40°C to +85°C
PORT A
AD7A
AD6A
AD5A
AD4A
AD3A
AD2A
AD1A
AD0A
WEA
CEA
OEA
GND
• Standby current of 100 nA @ 25°C makes the device
ideal for battery backup or battery operate applications.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PORT B
VCC
OEB
CEB
WEB
AD0B
AD1B
AD2B
AD3B
AD4B
AD5B
AD6B
AD7B
DS1609S
24–PIN SOIC (300 MIL)
See Mech. Drawings
Section
PIN DESCRIPTION
AD0–AD7
CE
WE
OE
VCC
GND
–
–
–
–
–
–
Port address/data
Port enable
Write enable
Output enable
+5 volt supply
Ground
DESCRIPTION
The DS1609 is a random access 256–byte dual port
memory designed to connect two asyncronous address/data buses together with a common memory element. Both ports have unrestricted access to all
256 bytes of memory, and with modest system discipline no arbitration is required. Each port is controlled
by three control signals: output enable, write enable,
and port enable. The device is packaged in plastic
24–pin DIP and 24–pin SOIC. Output enable access
time of 50 ns is available when operating at 5 volts.
020499 1/7
DS1609
OPERATION – READ CYCLE
The main elements of the dual port RAM are shown in
Figure 1.
A read cycle to either port begins by placing an address
on the multiplexed bus pins AD0 – AD7. The port enable
control (CE) is then transitioned low. This control signal
causes address to be latched internally. Addresses can
be removed from the bus provided address hold time is
met. Next, the output enable control (OE) is transitioned
low, which begins the data access portion of the read
cycle. With both CE and OE active low, data will appear
valid after the output enable access time tOEA. Data will
remain valid as long as both port enable and output enable remains low. A read cycle is terminated with the
first occurring rising edge of either CE or OE. The address/data bus will return to a high impedance state after time tCEZ or tOEZ as referenced to the first occurring
rising edge. WE must remain high during read cycles.
OPERATION – WRITE CYCLE
A write cycle to either port begins by placing an address
on the multiplexed bus pins AD0 – AD7. The port enable
control (CE) is then transitioned low. This control signal
causes address to be latched internally. As with a read
cycle, the address can be removed from the bus provided address hold time is met. Next the write enable
control signal (WE) is transitioned low which begins the
write data portion of the write cycle. With both CE and
020499 2/7
WE active low the data to be written to the selected
memory location is placed on the multiplexed bus. Provided that data setup (tDS) and data hold (tDH) times are
met, data is written into the memory and the write cycle
is terminated on the first occurring rising edge of either
CE or WE. Data can be removed from the bus as soon
as the write cycle is terminated. OE must remain high
during write cycles.
ARBITRATION
The DS1609 dual port RAM has a special cell design
that allows for simultaneous accesses from two ports
(see Figure 2). Because of this cell design, no arbitration is required for read cycles occurring at the same instant. However, an argument for arbitration can be
made for reading and writing the cell at the exact same
instant or for writing from both ports at the same instant.
A simple way to assure that read/write conflicts don’t occur is to perform redundant read cycles. Write/write arbitration needs can be avoided by assigning groups of
addresses for write operation to one port only. Groups
of data can be assigned check sum bytes which would
guarantee correct transmission. A software arbitration
system using a “mail box” to pass status information can
also be employed. Each port could be assigned a
unique byte for writing status information which the other port would read. The status information could tell the
reading port if any activity is in progress and indicate
when activity is going to occur.
DS1609
BLOCK DIAGRAM: DUAL PORT RAM Figure 1
PORT A
PORT B
8 ADDRESS
MUX ADDRESS/DATA
ADDRESS/
DATA MUX
LATCH
DECODE
8 ADDRESS
ADDRESS/
DATA MUX
LATCH
DECODE
256 BYTE DUAL
PORT MEMORY
MATRIX
8 DATA
8 DATA
WE
WE
OE
CE
MUX ADDRESS/DATA
CONTROL
LOGIC
CONTROL
LOGIC
OE
CE
DUAL PORT MEMORY CELL Figure 2
VCC
DATA–PORT A
DATA–PORT B
DATA–PORT A
DATA–PORT B
020499 3/7
DS1609
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.5V to +7.0V
–40°C to +85°C
–55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(–40°C to +85°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Power Supply
VCC
4.5
5.0
5.5
V
1
Input Logic 1
VIH
2.0
VCC + 0.3
V
1
Input Logic 0
VIL
–0.3
+0.8
V
1
(–40°C to +85°C; VCC = 5V ± 10%)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MIN
Input Impedance
ZIN
50K
CE, WE, OE Leakage
ILO
–1.0
TYP
MAX
UNITS
NOTES
Ω
2
+1.0
µA
Standby Current
ICCS1
3.0
5.0
mA
3, 4, 13
Standby Current
ICCS2
50
300
µA
3, 5, 13
Standby Current
ICCS3
100
nA
3, 6, 13
Operating Current
ICC
18
mA
7, 13
Logic 1 Output
VOH
V
8
Logic 0 Output
VOL
V
9
30
2.4
0.4
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL
MIN
TYP
MAX
UNITS
Input Capacitance
CIN
5
10
pF
I/O Capacitance
CI/O
5
10
pF
020499 4/7
NOTES
DS1609
(–40°C to +85°C; VCC = 5V ± 10%)
AC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Address Setup Time
tAS
5
ns
Address Hold Time
tAH
25
ns
Output Enable Access
tOEA
0
50
ns
OE to High Z
tOEZ
0
20
ns
CE to High Z
tCEZ
0
20
ns
Data Setup Time
tDS
0
ns
Data Hold Time
tDH
10
ns
Write Pulse Width
tWP
50
ns
11
CE Recovery Time
tCER
20
ns
12
WE Recovery Time
tWER
20
ns
12
OE Recovery Time
tOER
20
ns
12
CE to OE Setup Time
tCOE
25
ns
CE to WE Setup Time
tCWE
25
ns
AC ELECTRICAL CHARACTERISTICS
PARAMETER
10
(–40°C to +85°C; VCC = 2.5V – 4.5V)
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Address Setup Time
tAS
5
ns
Address Hold Time
tAH
25
ns
Output Enable Access
tOEA
0
100
ns
OE to High Z
tOEZ
0
20
ns
CE to High Z
tCEZ
0
20
ns
Data Setup Time
tDS
0
ns
Data Hold Time
tDH
10
ns
Write Pulse Width
tWP
100
ns
11
CE Recovery Time
tCER
20
ns
12
WE Recovery Time
tWER
20
ns
12
OE Recovery Time
tOER
20
ns
12
CE to OE Setup Time
tCOE
25
ns
CE to WE Setup Time
tCWE
25
ns
10
020499 5/7
DS1609
DUAL PORT RAM TIMING: READ CYCLE
DURING READ CYCLE WE = VIH
AD0 – AD7
ADDRESS VALID
DON’T CARE
DATA OUT VALID
tAS
tAH
tCEZ
CE
tCOE
tOEA
tOEZ
OE
NOTES:
1. During read cycle the address must be off the bus prior to tOEA minimum to avoid bus contention.
2. Read cycles are terminated by the first occurring rising edge of OE or CE.
DUAL PORT RAM TIMING: WRITE CYCLE
DURING WRITE CYCLE OE = VIH
AD0 – AD7
ADDRESS VALID
DON’T CARE
DATA IN VALID
tAS
tAH
CE
tCWE
tDS
WE
NOTE:
1. Write cycles are terminated by the first occurring edge of WE or CE.
020499 6/7
tWP
tDH
DS1609
NOTES:
1. All Voltages are referenced to ground.
2. All pins other than CE, WE, OE, VCC and ground are continuously driven by a feedback latch in order to hold the
inputs at one power supply rail or the other when an input is tristated. The minimum driving impedance presented
to any pin is 50KΩ. If a pin is at a logic low level, this impedance will be pulling the pin to ground. If a pin is at a
logic high level, this impedance will be pulling the pin to VCC.
3. Standby current is measured with outputs open circuited.
4. ICCS1 is measured with all pins within 0.3V of VCC or GND and with CE at a logic high or logic low level.
5. ICCS2 is measured with all pins within 0.3V of VCC or ground and with CE within 0.3V of VCC.
6. ICCS3 is measured with all pins at VCC or ground potential and with CE = VCC. Note that if a pin is floating, the
internal feedback latches will pull all the pins to one power supply rail or the other.
7. Active current is measured with outputs open circuited, and inputs swinging full supply levels with one port reading
and one port writing at 100 ns cycle time. Active currents are a DC average with respect to the number of 0’s and
1’s being read or written.
8. Logic one voltages are specified at a source current of 1 mA.
9. Logic zero voltages are specified at a sink current of 4 mA.
10. Measured with a load as shown in Figure 3.
11. tWP is defined as the time from WE going low to the first of the rising edges of WE and CE.
12. Recovery time is the amount of time control signals must remain high between successive cycles.
13. Typical values are at 25°C.
LOAD SCHEMATIC Figure 3
+5 VOLTS
1.1KΩ
D.U.T.
680 Ω
30 pF
020499 7/7
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