AZM AZP81 Pecl/ecl filter-based multiplier & limiting amp with selectable enable Datasheet

ARIZONA MICROTEK, INC.
AZP81
PECL/ECL Filter-Based Multiplier & Limiting Amp with Selectable Enable
FEATURES
•
•
•
•
•
PACKAGE AVAILABILITY
High Bandwidth for 1+GHz
3.0V to 5.5V Power Supply
Selectable Enable Polarity
Designed for Filters to Select Odd or
Even Harmonics
S-Parameter (.s1p and .s2p) Files
Available on Arizona Microtek Website
PACKAGE
MLP 16 (3x3) Green /
RoHS Compliant /
Lead (Pb) Free
1
2
PART NO.
MARKING
NOTES
AZP81LG
AZMG
P81
<Date Code>
1,2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch
(2.5K parts) Tape & Reel.
Date code format: “Y” for year followed by “WW” for week.
DESCRIPTION
The AZP81 is a specialized multiplier chip designed to be used with an external filter. It supplies three different
gain paths. A low gain path is used with a resonator, usually a crystal (D/D̄ to Q̄). An intermediate gain path with
fast output edges supplies a filter (D/D̄ to FLTRDR/FLTRDR
¯¯¯¯¯¯¯¯). A high gain limiting amp (AMPIN to QHG/Q̄HG)
with a selectable enable provides industry standard 100k PECL/ECL outputs.
When QHG/Q̄HG are disabled, the AZP81’s oscillator loop continues to operate. See truth table below for enable
function. It also provides a VBB and 470Ω internal bias resistors from D/D̄ to VBB and AMPIN to VBB. The VBB pin
can support 1.5mA sink/source current. Bypassing VBB and D̄ to ground with 0.01 to 0.1 μF capacitors is
recommended.
Output Q̄ has an on-chip 4mA pull-down current source while output FLTRDR has an on-chip 8mA pull-down
current source. External resistors to VEE may also be used to increase pull-down current to a maximum of 25mA each.
ENABLE TRUTH TABLE
EN-SEL EN (PECL/CMOS)
QHG
NC
Low
Low
NC
High or NC
Data
Low or NC
Data
VEE*
High
Low
VEE*
*Connections to VEE must be less than 1Ω.
D
Q̄HG
High
Data
Data
High
D
Q
FLTRDR
470Ω
FLTRDR
VBB
PIN DESCRIPTION
PIN
D/D̄
Q̄
AMPIN
FLTRDR/FLTRDR
¯¯¯¯¯¯¯¯
QHG/Q̄HG
VBB
EN
EN-SEL
FUNCTION
Inputs from Resonator
Output to Resonator
Inputs from Filter
Outputs to Filter
Outputs w/High Gain
Ref. Voltage Output
Enable Input
Selects Enable Logic
8mA
4mA
470Ω
QHG
AMPIN
LIMITING AMP
QHG
EN
EN-SEL
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (623) 505-2414
www.azmicrotek.com
VEE
AZP81
TIMING DIAGRAMS
D to Q̄/FLTRDR
AMPIN
EN (EN-SEL CONNECTED TO VEE)
EN (EN-SEL OPEN)
QHG
AMPIN to QHG
AZP81L PINOUT
Leave Pad
Open or
Connect to
VEE
TOP VIEW
June 2009 Rev - 4
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2
AZP81
Absolute Maximum Ratings. Beyond which device life may be impaired.
Characteristic
Symbol
Rating
Unit
PECL Power Supply
(VEE = 0V)
PECL Input Voltage
(VEE = 0V)
PECL EN Input Voltage (VEE = 0V)
ECL Power Supply
(VCC = 0V)
ECL Input Voltage
(VCC = 0V)
ECL EN Input Voltage (VEE = 0V)
Output Current
--- Continuous
Q̄, FLTRDR/FLTRDR
¯¯¯¯¯¯¯ --- Surge
Output Current
--- Continuous
--- Surge
QHG/Q̄HG
Operating Temperature Range
VEE
VI
VI
VEE
VI
VI
0 to 6.0
±0.75 with respect to VBB
0 to 6.0
-6.0 to 0
±0.75 with respect to VBB
-6.0 to 0
25
50
50
100
-40 to +85
VDC
VDC
VDC
VDC
VDC
VDC
IOUT
IOUT
TA
mA
mA
°C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
VOH
VOL
VOH
VOL
VIH
VIL
VBB
IIL
IIH
IEE
1.
Characteristic
-40°C
Min
0°C
Max
Min
Output HIGH Voltage
-1045
-895
-1005
Q̄, FLTRDR/FLTRDR
¯¯¯¯¯¯¯
Output LOW Voltage
-2010
-1710
-1985
Q̄, FLTRDR/FLTRDR
¯¯¯¯¯¯¯
Output HIGH Voltage1
-1085
-880
-1025
QHG/Q̄HG
Output LOW Voltage1
-1830
-1555
-1810
QHG/Q̄HG
Input HIGH Voltage
D/D̄
-1165
-390
-1165
EN
-1165
VCC
-1165
Input LOW Voltage
-1475
-2250
D/D̄
-2250
-1475
VEE
EN
VEE
Reference Voltage
-1390
-1250
-1390
Input LOW Current
EN (ECL)
-150
-150
EN (CMOS)
-300
-300
Input HIGH Current EN
150
Power Supply Current
63
Specified with each output terminated through a 50Ω resistor to VCC – 2V.
25°C
85°C
Unit
Max
Min
Max
Min
Max
-855
-980
-830
-910
-760
mV
-1685
-1965
-1665
-1910
-1610
mV
-880
-1025
-880
-1025
-880
mV
-1620
-1810
-1620
-1810
-1620
mV
-390
VCC
-1165
-1165
-390
VCC
-1165
-1165
-390
VCC
mV
-1475
-1475
-1250
-2250
VEE
-1390
-1475
-1475
-1250
-2250
VEE
-1390
-1475
-1475
-1250
mV
-150
-300
μA
-150
-300
150
63
mV
150
63
150
68
μA
mA
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
VOH
VOL
VOH
VOL
VIH
VIL
VBB
IIL
IIH
IEE
1.
2.
Characteristic
-40°C
Min
0°C
Max
Min
25°C
Max
Output HIGH Voltage
2255
2405
2295
2445
Q̄, FLTRDR/FLTRDR
¯¯¯¯¯¯¯
Output LOW Voltage
1290
1590
1315
1615
Q̄, FLTRDR/FLTRDR
¯¯¯¯¯¯¯
1
Output HIGH Voltage
2215
2420
2275
2420
QHG/Q̄HG
1
Output LOW Voltage
1470
1745
1490
1680
QHG/Q̄HG
Input HIGH Voltage
D/D̄
2135
2910
2135
2910
EN
2135
VCC
2135
VCC
Input LOW Voltage
D/D̄
1050
1825
1050
1050
EN
VEE
1825
VEE
VEE
Reference Voltage
1910
2050
1910
2050
Input LOW Current
EN (ECL)
-150
-150
EN (CMOS)
-300
-300
Input HIGH Current EN
150
150
Power Supply Current1
63
63
For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value.
Specified with each output terminated through a 50Ω resistor to VCC – 2V.
June 2009 Rev - 4
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3
85°C
Unit
Min
Max
Min
Max
2320
2470
2390
2540
mV
1335
1635
1390
1690
mV
2275
2420
2275
2420
mV
1490
1680
1490
1680
mV
2135
2135
2910
VCC
2135
2135
2910
VCC
mV
1825
1825
1910
1050
VEE
2050
1825
1825
1910
-1475
-1475
2050
mV
-150
-300
μA
-150
-300
150
63
mV
150
68
μA
mA
AZP81
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
Characteristic
-40°C
Min
0°C
Max
Min
25°C
Max
Output HIGH Voltage
3955
4105
3995
4145
Q̄, FLTRDR/FLTRDR
¯¯¯¯¯¯
Output LOW Voltage
VOL
2990
3290
3015
3315
Q̄, FLTRDR/FLTRDR
¯¯¯¯¯¯
Output HIGH Voltage1
VOH
3915
4120
3975
4120
QHG/Q̄HG
Output LOW Voltage1
VOL
1470
1745
1490
1680
QHG/Q̄HG
Input HIGH Voltage
VIH
D/D̄
3835
4610
3835
4610
EN
3835
VCC
3835
VCC
Input LOW Voltage
VIL
3525
2750
3525
D/D̄
2750
3525
VEE
3525
EN
VEE
VBB
Reference Voltage
3610
3750
3610
3750
Input LOW Current
IIL
EN (ECL)
-150
-150
EN (CMOS)
-300
-300
Input HIGH Current EN
150
150
IIH
IEE
Power Supply Current1
63
63
1. For supply voltages other than 5.0V, use the ECL table values and ADD supply voltage value.
2. Specified with each output terminated through a 50Ω resistor to VCC – 2V.
VOH
85°C
Unit
Min
Max
Min
Max
4020
4170
4090
4240
mV
3035
3335
3090
3390
mV
3975
4120
3975
4120
mV
1490
1680
1490
1680
mV
3835
3835
4610
VCC
3835
3835
4610
VCC
mV
2750
VEE
3610
3525
3525
3750
2750
VEE
3610
3525
3525
3750
mV
-150
-300
mV
μA
-150
-300
150
63
150
68
μA
mA
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VCC = 3.0V to 5.5V, VEE = GND)
Symbol
Characteristic
Min
-40°C
Typ
Max
Min
0°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Propagation Delay
D/D̄ to Q̄
90
200
90
200
90
200
90
200
D/D̄ to FLTRDR/FLTRDR
¯¯¯¯¯¯¯ 2
130
260
130
260
130
260
130
260
AMPIN to QHG/Q̄HG1 (SE)
200
380
200
380
200
380
200
380
tSKEW
Duty Cycle Skew3
(SE)
5
20
5
20
5
20
5
20
300
2000
300
2000
300
2000
300
2000
D/D̄
Input Swing (SE)4
VPP (AC)
AMPIN
150
2000
150
2000
150
2000
150
2000
Output Rise/Fall Times (20%
tr / t f
80
240
80
240
80
240
80
240
- 80%)
Maximum Recommended
Multiply Ratio
xMAX
Even Harmonics
8
8
8
8
Odd Harmonics
7
7
7
7
1.
Specified with QHG/Q̄HG terminated through a 50Ω resistor to VCC – 2V.
2.
Specified with FLTRDR terminated into an AC coupled 50Ω load, FLTRDR
¯¯¯¯¯¯¯ into an AC coupled 50Ω load along an external 8mA pull-down current.
3.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
4.
Single ended input swing for which AC parameters guaranteed.
tPLH / tPHL
SINGLE ENDED AC PP INPUT
June 2009 Rev - 4
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4
Unit
ps
ps
mV
ps
AZP81
1000
900
800
VOUTpp (mV)
700
600
500
400
300
200
100
0
0
500
1000
1500
2000
2500
3000
3500
FREQUENCY (MHz)
Fig 1: Typical Large Signal Outputs, QHG/Q̄HG
Measured with 750mVPP on AMPIN, QHG/Q̄HG each terminated to VCC-2V via 50 Ω resistors.
June 2009 Rev - 4
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5
4000
AZP81
APPLICATION
The AZP81 is a “filter-based” oscillator gain stage and multiplier. Generating a spectrum of harmonics from a sinewave input, an external bandpass filter selects the desired harmonic.
A crystal or SAW (with associated passive discrete components) is connected between D and Q̄ (pins 1 and 16,
respectively) to form an high stability oscillator stage. Alternatively, an external Colpitts, Pierce or similar sinewave oscillator may be fed into D (pin 1) to drive the AZP81. In this case, input amplitude should be less than 1 VPP
on D for best results. Also, tie the Q̄ pin to VCC to reduce fundamental subharmonic and other noise source coupling
into the circuit board.
The D input also drives another higher gain stage. This stage generates fast edges with resultant high harmonic
spectral content. In one mode, the signal on FLTRDR (pin 14) is a square wave with greater spectral energy at odd
harmonics (3x, 5x, 7x). Figure 4 illustrates the typical spectral output at FLTRDR. Another mode is selected by
connecting FLTRDR
¯¯¯¯¯¯¯ and FLTRDR. This mode generates a pulse wave which contains greater spectral energy at
even harmonics (2x, 4x, 6x, 8x). Figure 5 illustrates the typical spectral output at FLTRDR when the two pins are
shorted together.
An external bandpass filter inserted between FLTRDR (or FLTRDR/FLTRDR
¯¯¯¯¯¯¯ ) and AMPIN (pin 7) selects the
desired harmonic and attenuates the rest. This filter is typically either an LC or SAW implementation. The bandpass
filter is AC coupled since both the FLTDR and AMPIN signals are internally biased. The filter must be designed for
the drive impedance found at FLTRDR and the input impedance at AMPIN.
Graphs that follow in this data sheet show the S-parameters for these pins. Also included are graphs of the output
impedance magnitude of FLTRDR and the input impedance magnitude of AMPIN. These impedance graphs provide
a way to approximate the filter required without the use of S-parameter based design software.
The filter and other elements on the circuit board must be placed carefully to minimize subharmonic feed-through.
The resultant signal level at AMPIN should be 150 mV peak-peak or greater for best limiting amplifier performance.
The limiting amplifier provides a high bandwidth PECL/ECL output into the standard load of 50Ω to VCC – 2V.
Figure 1 shows the large signal output swing versus frequency.
It may be desirable to hold off the limiting amplifier operation until the sine-wave oscillator has started. A capacitor
may be used with the EN pin to create a delay. Connect the capacitor from EN to VCC (if EN-SEL is open) or VEE (if
EN-SEL is connected to VEE). This modification will avoid high-frequency parasitic feedback from the circuit board
during oscillator startup. A 220ρF capacitor will provide approximately 10μs delay.
Arizona Microtek’s website (www.azmicrotek.com) contains S-parameters for all signal paths in industry-standard
.s1p and .s2p format supporting an easier RF design process.
June 2009 Rev - 4
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6
AZP81
ADD THIS CONNECTION
TO CONVERT SQUARE
WAVE INTO PULSE WAVE
CRYSTAL
OR
SAW
Q
FLTRDR
16
14
FLTRDR
13
AZP81
D
D
1
2
7
VBB
3
LIMITING
AMP
QHG
9
QHG
EN
Fig 2: Typical Multiplier Application
(Simplified Logic Shown)
Fig 3: Typical LC Band Pass Filter
www.azmicrotek.com
7
AMPIN
10
12
June 2009 Rev - 4
BAND
PASS
FILTER
AZP81
0
155 MHz INPUT
FREQUENCY
-10
ODD
HARMONICS
7x MAXIMUM
RECOMMENDED
HARMONIC
OUTPUT LEVEL (dB relative)
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
200
400
600
800
1000
1200
1400
1600
1800
2000
FREQUENCY (MHz)
Fig 4: Typical Spectrum Output of FLTRDR (Square wave)
Full Limiting 155 MHz Input Signal
0
155 MHz INPUT
FREQUENCY
-10
8x MAXIMUM
RECOMMENDED
HARMONIC
EVEN
HARMONICS
OUTPUT LEVEL (dB relative)
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
200
400
600
800
1000
1200
1400
1600
1800
FREQUENCY (MHz)
Fig 5: Typical Spectrum Output of FLTRDR (Pulse wave)
Full Limiting 155 MHz Input Signal
June 2009 Rev - 4
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8
2000
AZP81
S-PARAMETERS
0
0.85
-10
0.8
-20
Phase
Magnitude
0.9
0.75
-30
0.7
-40
0.65
S11 MAG
S11 PHASE
-50
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
0.04
225
0.032
200
0.024
175
Phase
Magnitude
Fig 6: S11, D to Q̄
0.016
150
0.008
125
0
100
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
Fig 7: S12, D to Q̄
June 2009 Rev - 4
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9
S12 MAG
S12 PHASE
180
7.5
160
7
140
6.5
120
6
100
5.5
Phase
8
S21 MAG
Phase
Magnitude
AZP81
S22 MAG
S21 PHASE
80
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
Magnitude
Fig 8: S21, D to Q̄
0.8
180
0.7
170
0.6
160
0.5
150
0.4
140
0.3
130
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
Fig 9: S22, D to Q̄
June 2009 Rev - 4
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10
S22 PHASE
AZP81
0
0.8
-15
0.75
-30
S11 MAG (1)
Phase
Magnitude
0.85
0.7
-45
0.65
-60
0.6
S11 MAG (2)
S11 PHASE (1)
S11 PHASE (2)
-75
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
0.03
225
0.024
200
0.018
175
S12 MAG (1)
Phase
Magnitude
Fig 10: S11, D to FLTRDR
0.012
150
0.006
125
0
100
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
Fig 11: S12, D to FLTRDR
(1): FLTRDR
¯¯¯¯¯¯¯ open, not connected to FLTRDR
(2): FLTRDR
¯¯¯¯¯¯¯ connected to FLTRDR
June 2009 Rev - 4
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11
S12 MAG (2)
S21 PHASE (1)
S21 PHASE (2)
30
0
24
-50
18
-100
S21 MAG (1)
Phase
Magnitude
AZP81
12
-150
6
-200
0
S21 MAG (2)
S21 PHASE (1)
S21 PHASE (2)
-250
50
150 250 350
450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
1
180
0.8
160
0.6
140
S22 MAG (1)
Phase
Magnitude
Fig 12: S21, D to FLTRDR
0.4
120
0.2
100
0
80
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
Fig 13: S22, D to FLTRDR
(1): FLTRDR
¯¯¯¯¯¯¯ open, not connected to FLTRDR
(2): FLTRDR
¯¯¯¯¯¯¯ connected to FLTRDR
June 2009 Rev - 4
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12
S22 MAG (2)
S22 PHASE (1)
S22 PHASE (2)
0.82
0
0.81
-10
0.8
-20
0.79
-30
0.78
-40
0.77
-50
0.76
-60
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
Fig 14: S11, AMPIN to QHG
June 2009 Rev - 4
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13
Phase
Magnitude
AZP81
S11 MAG
S11 PHASE
AZP81
IMPEDANCES
50
45
40
Magnitude (ohms)
35
30
OUTPUT IMPEDANCE (1)
25
OUTPUT IMPEDANCE (2)
20
15
10
5
0
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
Fig 15: FLTDR Output Impedance
(1): FLTRDR
¯¯¯¯¯¯¯ open, not connected to FLTRDR
(2): FLTRDR
¯¯¯¯¯¯¯ connected to FLTRDR
500
Magnitude (ohms)
400
300
INPUT
IMPEDANCE
200
100
0
50
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
Fig 16: AMPIN Input Impedance
June 2009 Rev - 4
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14
AZP81
PACKAGE DIAGRAM
MLP 16
A
D
D
2
2.
INDEX AREA
(D/2 x E/2)
D2
D2/2
B
E2/2
E2
E
2
3x
E
e
2
e
2x
1
aaa C
2x
aaa C
TOP VIEW
bbb M C A B
5.
16 x b
L
3.
3x e
BOTTOM VIEW
ccc C
A3
A
4.
0.08 C
A1
SIDE
VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING
CONFORM TO ASME T14-1994.
2. THE TERMINAL #1 AND PAD
NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012.
3. DIMENSION b APPLIES TO METALLIZED
PAD AND IS MEASURED BETWEEN 0.25
AND 0.30 mm FROM PAD TIP.
4. COPLANARITY APPLIES TO THE
EXPOSED PADS AS WELL AS THE
TERMINALS.
5. INSIDE CORNERS OF METALLIZED PAD
MAY BE SQUARE OR ROUNDED
June 2009 Rev - 4
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15
C
SEATING
PLANE
MILLIMETERS
DIM
A
A1
A3
b
D
D2
E
E2
e
L
aaa
bbb
ccc
MIN
MAX
0.80
1.00
0.05
0.00
0.25 REF
0.18
0.30
2.90
3.10
0.25
1.95
2.90
3.10
0.25
1.95
0.50 BSC
0.30
0.50
0.25
0.10
0.10
AZP81
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
June 2009 Rev - 4
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16
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