BOURNS SM535-1

oH
V SC
AV ER OM
AI SIO PL
LA N IA
BL S NT
E
*R
■ Designed to meet UL1950 and EN60950
Features
■ For use with Texas Instruments’
1
5SM53
TNET D 4000 C/P chipset
■ Excellent Total Harmonic Distortion
(THD) Performance
■ SMT and small size package
■ Designed to meet IEC1950
■ Operating temperature -40 °C to +85 °C
supplementary insulation requirements
for operating voltages up to 250 Vrms
■ Lead free version available (see How to
Order)
■ Lead free versions are RoHS compliant*
Applications
■ ADSL - TI TNET D4000 C/P
SM535-1 ADSL Line Transformers
Electrical Specifications @ 25 °C
Turns Ratio
(10-7):(1-4) chip to line......1:1.95 ±2 %
OCL @ 10 kHz, 0.1V
(1-4) ..............................1.5 mH ±10 %
Leakage Inductance @ 10 kHz 0.1 V
(1-4) with (10-7) shorted..12.0 µH max.
Interwinding Capacitance
@ 10 kHz, 0.1 V (1-10) ........35 pF max.
Isolation Voltage ............1500 Vrms max.
DC Resistance ........................2.0 Ω max.
Application ..........................................CO
Product Dimensions
Electrical Schematic
Chip
.711 ± .050
10 PLCS.
(.028 ± .002)
13.46
MAX.
(.530)
5
6
4
7
3
2
SM535-1
Packaging Specifications
Tape & Reel* ........................200 pcs./reel
1
7
4
1 : 1.95
10.00
2.50 (.394)
(.098) MAX.
8
(DATECODE)
1
Line
10
9
How to Order
10
SM535-1E __
17.65
MAX.
(.695)
Model
13.50
MAX.
(.531)
Termination
Blank = Tin-lead
L = Tin only (lead free)
*”E” suffix at end of part number
designates tape & reel packaging, e.g.
SM535-1E.
12.07
MAX.
(.475)
12.32
MAX.
(.485)
2.50
(.098)
0.13
(.005)
10 SURFACES
2.54
(.100)
10.00
(.394)
1.30 ± .050
(.051 ± .002)
10 PLCS.
15.37
(.605)
Recommended PAD layout
DIMENSIONS ARE:
TOLERANCE: ±
MM
(INCHES)
0.25
(.010)
03/05
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.