For Communications Equipment
MN6155
PLL LSI with Built-In Prescaler
Overview
The MN6155 is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data parameter
input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (1.65
mW for VDD=1.1 V, F IN= RIN =90 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
It also offers two choices for the reference signal: selfexcited operation using the built-in inverter amplifier or
use of an external, separately excited oscillator.
Pin Assignment
XIN
1
16
RIN
XOUT
2
15
RSL
FV
3
14
LC
VDD
4
13
FR
DOP
5
12
PS
VSS
6
11
LE
VCP
7
10
DATA
FIN
8
9
(TOP VIEW)
SSOP016-P-0225
Features
Low power supply voltage: VDD=1.0 to 1.4V
Low power consumption: 1.65mW(VDD=1.10V,
FIN =90MHz, RIN =90MHz)
High-speed operation: FIN=90MHz, R IN=90MHz
(VDD=1.1V)
Frequency dividing ratios in reference frequency
dividing stage
6 to 131,070 for RSL at "H" level
(even number setting is available)
272 to 131,071 for RSL at "L" level
Frequency dividing ratios for comparator stage: 272
to 262,143
Power supply pin for built-in charge pump
VCP=2.5 to 3.2V
Output monitor pins for both comparator and reference
frequency dividing stages
CLK
FIN
PS
LE
DATA
CLK
XOUT
XIN
RIN
RSL
8
12
11
10
9
2
1
16
15
Data control
Phase
adjustment
Prescaler and
phase adjustment
Prescaler
Prescaler and
phase adjustment
Swallow
counter
3-bit counter
Swallow
counter
Control
13-bit programmable counter
14-bit programmable counter
18-bit latch
18-bit shift register
17-bit latch
Switching
circuit
3
14
5
7
13
6
4
FV
LC
DOP
VCP
FR
VSS
VDD
MN6155
For Communications Equipment
Block Diagram
Phase comparator
For Communications Equipment
MN6155
Pin Descriptions
Pin No.
1
Symbol
XIN
2
XOUT
Function Description
Crystal oscillator connection pins:
XIN =Oscillator circuit input pin;
(XIN is attached to a pull-up resistor when the PS or RSL pin is at "L" level.)
XOUT=Oscillator circuit output pin.
3
FV
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
4
V DD
Power supply
5
D OP
Low-pass filter connection pin. Use a passive filter.
6
V SS
Ground
7
VCP
Power supply pin for built-in charge pump
8
FIN
Frequency divider input pin in comparator stage.
9
CLK
Shift register clock input pin.
10
DATA
Shift register data input pin.
The chip latches data at the rising edge of the CLK signal.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
11
LE
Load enable signal input pin.
This is the latch-write-enable signal. It is at "H" level for write.
12
PS
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational
mode. "L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
13
FR
Reference frequency divider output signal.
14
LC
Charge pump control signal output pin.
Phase comparator input monitor.
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
15
RSL
Reference signal selection pin.
"H" level selects self-excited oscillator (XIN and XOUT).
"L" level selects external oscillator (RIN).
16
RIN
External reference oscillation input pin.
This pin is attached to a pull-up resistor when the PS pin is at "L" level or the
RSL pin is at "H" level.
MN6155
For Communications Equipment
MN6155 Frequency Dividing Data Settings
1)
2)
Comparator side frequency dividing data
FV = FIN ÷ {(16 × N) + A}
Reference side frequency dividing data
a) Low-speed operation (RSL pin at "H" level, using XIN )
FR = XIN ÷ R
b) High-speed operation (RSL pin at "L" level, using RIN )
FR =RIN ÷ {(16 × NR) + AR}
where
FIN
: Comparator side frequency
RIN
: High-speed reference frequency
XIN
: Low-speed reference oscillator frequency
FV
: Comparator frequency divider stage output frequency
FR
: Reference frequency divider stage output frequency
N
: Setting for 14-bit programmable counter on comparator side
A
: Setting for 4-bit swallow counter on comparator side
R
: Setting for 17-bit programmable counter on low-speed reference side
NR
: Setting for 13-bit programmable counter on high-speed reference side
AR
: Setting for 4-bit swallow counter on low-speed reference side
(Note that N should be greater than A; NR, greater than AR.)
N-Side Latch Data
MSB
14 bits
4 bits
Programmable
counter setting (N)
LSB
Swallow counter
setting (A)
R-Side Latch Data
Low-speed operation
MSB
LSB
17 bits
Programmable counter
setting (N)
High-speed operation
MSB
13 bits
Programmable counter
setting (NR)
4 bits
Swallow counter
setting (AR)
LSB
For Communications Equipment
MN6155
Note on Setting Frequency Dividing Data Input
1) Frequency dividing data input
(1) Reference side
Data input direction
Control bits
MSB
LSB
17-bit frequency dividing data
1 bit
1 bit
"L"
Frequencey
Write selection
dividing stage
"H" level
selection "H" level
1
2
17
18
19
CLK
DATA
MSB
LSB
LE
(2) Comparating side
Data input direction
Control bits
*1
3-bit test data
3 bits "L" level
1
2
1 bit
18-bit frequency dividing data
3
4
5
1 bit
"L"
Frequencey
Write selection
dividing stage
"H" level
selection "L" level
21
22
23
CLK
DATA
MSB
LSB
LE
Notes
1.*1: Preceding the input of the frequency dividing data for the comparating side, input test pattern consisting
of three "L" level bits to produce normal operation. Never use any other pattern.
2. When the power is first applied, internal operation remains in an unstable state until data is written. To
eliminate the risk of excessive current consumption, keep the PS pin at "L" level.
3. When the power is first applied, the data settings are indeterminate. Always write data to the chip before
starting operation.
4. Enter the data to fill the entire latch:
5.
6.
7.
8.
9.
Reference side: 19 bits (17 bits for the frequency divider setting and 2 for control bits)
Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2 for
control bits)
Drive the LE pin at "L" level while writing the data.
"H" level input from the LE pin causes the chip to read the data only when the CLK pin and the DATA pin
are both at "L" level.
Writes are possible when the PS pin is either "H" or "L" level.
Input the data MSB first.
The data are inputted at the rising edge of the CLK signal.
MN6155
For Communications Equipment
Absolute Maximum Ratings
Parameter
Power supply voltage
Symbol
VDD
Rating
– 0.3 to +3.0
Power supply voltage
VCP
– 0.3 to +4.0
Input pin voltage
VI
VSS – 0.3 to VDD +0.3
Output pin voltage
VO
VSS – 0.3 to VDD +0.3
Power dissipation
PD
20
Operating ambient temperature
Topr
–10 to +60
Storage temperature
Tstg
–55 to +125
Unit
V
mW
˚C
Operating Conditions
VSS=0V, Ta=–10 to +60˚C
Parameter
Power supply voltage
Symbol
VDD
Power supply voltage
VCP
Test Conditions
min
1.0
typ
1.1
max
1.4
Unit
V
2.5
3.0
3.2
V
min
typ
max
Unit
2.3
mA
3
µA
Electric Characteristics
VCP=2.5V, Ta=–10 to +60˚C
Parameter
Power supply pin
Symbol
VDD
IDD
Power supply current
Test Conditions
VDD =1.1V
FIN =90MHz, RIN=90MHz,
PS="H", RSL="L"
IDstop
PS="L" (Power Save operation)
Input Pins CLK, DATA, LE, and PS VDD =1.0 to 1.4 V
"H" level input voltage
VIH
VDD – 0.2
VDD
"L" level input voltage
VIL
VSS
0.2
Input leakage current
ILI
Input Pins FIN , RIN
±1.0
VIN
Input current
IIF
Pull-up resistor is present
(PS="L")
Input leakage current
ILIF
FINMAX
RINMAX
Minimum operating frequency
µA
VDD =1.0 to 1.4V
Input voltage
Maximum operating frequency
V
FINMIN
RINMIN
0.4
Vp-p
–10
µA
±20
VIN =0 or VDD (PS="H")
VIN =0.4 Vp-p
90
VIN =0.4 Vp-p
µA
MHz
1.0
MHz
Input Pin X IN VDD=1.0 to 1.4V
Input voltage
VIN
Input current
IIX
0.4
Pull-up resistor is present
(PS="L")
Input leakage current
Maximum operating frequency
ILIX
VIN =0 or VDD
XINMAX
VIN =0.4 Vp-p
– 0.1
Vp-p
–1.5
5.0
15
mA
µA
MHz
For Communications Equipment
MN6155
Electrical Characteristics (continued)
VCP=2.5V, Ta=–10 to +60˚C
Parameter
Symbol
Test Conditions
Crystal Oscillator Pins X IN, XOUT
VDD =1.0 to 1.4V
Crystal oscillator frequency
fXtal
Output Pins FV, FR, LC
"L" level output voltage
XOUT
typ
max
15
MHz
VOH
I OH= –10µA
VOL
I OL=10µA
VDD– 0.3
VDD
VSS
0.3
VXOH
IXOH= –100µA
VDD– 0.3
VDD
"L" level output voltage
VXOL
I XOL=100µA
VSS
0.3
DOP
V
VDD =1.0 to 1.4V
"H" level output voltage
Output Pin
Unit
VDD=1.0 to 1.4V
"H" level output voltage
Output Pin
min
V
VDD =1.0 to 1.4V
"H" level output voltage
IDOH
VDop=V CP – 0.3V
–100
"L" level output voltage
IDOL
VDop=0.3V
–100
Output leakage current
ILOH
VDop=V CP
2.0
I LOL
VDop=0.0V
–2.0
Output leakage current
µA
VDD =1.0 to 1.4V
Setup time *1
Hold time *1
tsul
500
ns
tsu2
500
ns
tH
500
ns
Note*1: The following timing chart shows the setup and hold times.
DATA
50%
tsu1
tH
CLK
tsu2
LE
Usage Note
Be particularly careful with this product as it is more sensitive on the static electricity damage than most of
our other products.
VF
*1
Loop filter
0.22µF
10kΩ
VCC
VCO
1µF
35kΩ
100Ω
VDD=1.0V to 1.4V
10µF
390Ω
80 to 90MHz
VCP=3V
VCC=3V
Amplifier
1000pF
0.1µF
0.1µF
8
7
6
5
4
3
2
1
CLK
DATA
LE
PS
FR
LC
RSL
RIN
9
10
11
12
13
14
15
16
Frequency dividing
data input
Frequency dividing
data input
Frequency dividing
data input
Intermittent
operation
control
excited
oscillator
Separately
*1 VCO characteristics may necessitate design revisions.
FIN
VCP
VSS
DOP
VDD
FV
XOUT
XIN
MN6155
MN6155
For Communications Equipment
Application Circuit Example
For Communications Equipment
MN6155
Package Dimensions (Unit: mm)
SSOP016-P-0225
6.5±0.2
16
9
+0.10
0.15 -0.05
6.3±0.2
4.3±0.2
1.0±0.1
0 to 10°
0.8
0.15
0.35±0.10
1.55±0.30
8
(0.45)
0.1±0.1
1
1.45±0.20
0.5±0.1
SEATING PLANE