EL7155 ® Data Sheet January 30, 2002 FN7279 High Performance Pin Driver Features The EL7155 high performance pin driver with 3-state is suited to many ATE and level-shifting applications. The 3.5A peak drive capability makes this part an excellent choice when driving high capacitance loads. • Clocking speeds up to 40MHz Output pins OUTH and OUTL are connected to input pins VH and VL respectively, depending on the status of the IN pin. One of the output pins is always in tri-state, except when the OE pin is active low, in which case both outputs are in 3state mode. The isolation of the output FETs from the power supplies enables VH and VL to be set independently, enabling level-shifting to be implemented. • 3.5pF typical input capacitance This pin driver has improved performance over existing pin drivers. It is specifically designed to operate at voltages down to 0V across the switch elements while maintaining good speed and on-resistance characteristics. Applications Available in 8-Pin SO and 8-Pin PDIP packages, the EL7155 is specified for operation over the full -40°C to +85°C temperature range. • IGBT drivers Pinout 1 OE 2 IN 3 GND 4 L o g i c 1 • 0.5ns rise and fall times mismatch • 0.5ns TON-TOFF prop delay mismatch • 3.5A peak drive • Low on resistance of 3.5Ω • High capacitive drive capability • Operates from 4.5V up to 18V • ATE/burn-in testers • Level shifting • CCD drivers Ordering Information EL7155 (8-PIN PDIP, SO) TOP VIEW VS+ • 15ns tr/tf at 2000pF CLOAD 8 VH 7 OUTH 6 OUTL 5 VL PART NUMBER PACKAGE TAPE & REEL PKG. NO. EL7155CN 8-Pin PDIP - MDP0031 EL7155CS 8-Pin SO - MDP0027 EL7155CS-T7 8-Pin SO 7” MDP0027 EL7155CS-T13 8-Pin SO 13” MDP0027 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL7155 Absolute Maximum Ratings (TA = 25°C) Supply Voltage (VS+ to VL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VL -0.3V, VL+ +0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +15V, VH = +15V, VL = 0V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT VIH Logic ‘1’ Input Voltage IIH Logic ‘1’ Input Current VIL Logic ‘0’ Input Voltage IIL Logic ‘0’ Input Current CIN Input Capacitance 3.5 pF RIN Input Resistance 50 MΩ 2.4 VIH = VS+ V 0.1 VIL = 0V 0.1 10 µA 0.8 V 10 µA OUTPUT ROVH ON Resistance VH to OUTH IOUT = -200mA 2.7 4.5 Ω ROVL ON Resistance VL to OUTL IOUT = +200mA 3.5 5.5 Ω IOUT Output Leakage Current OE = 0V, OUTH = VL, OUTL = VS+ 0.1 10 µA IPK Peak Output Current (linear resistive operation) Source 3.5 A Sink 3.5 A Continuous Output Current Source/Sink IDC 200 mA POWER SUPPLY IS Power Supply Current Inputs = VS+ IVH Off Leakage at VH VH = 0V 1.3 3 mA 4 10 µA SWITCHING CHARACTERISTICS tR Rise Time CL = 2000pF 14.5 ns tF Fall Time CL = 2000pF 15 ns tRF∆ tR, tF Mismatch CL = 2000pF 0.5 ns tD-1 Turn-Off Delay Time CL = 2000pF 9.5 ns tD-2 Turn-On Delay Time CL = 2000pF 10 ns tD∆ tD-1-tD-2 Mismatch CL = 2000pF 0.5 ns tD-3 3-state Delay Enable 10 ns tD-4 3-state Delay Disable 10 ns 2 EL7155 Electrical Specifications PARAMETER VS+ = +5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT VIH Logic ‘1’ Input Voltage IIH Logic ‘1’ Input Current VIL Logic ‘0’ Input Voltage IIL Logic ‘0’ Input Current CIN Input Capacitance 3.5 pF RIN Input Resistance 50 MΩ 2.0 VIH = VS+ V 0.1 VIL = 0V 0.1 10 µA 0.8 V 10 µA OUTPUT ROVH ON Resistance VH to OUTH IOUT = -200mA 3.4 5 Ω ROVL ON Resistance VL to OUTL IOUT = +200mA 4 6 Ω IOUT Output Leakage Current OE = 0V, OUTH = VL, OUTL = VS+ 0.1 10 µA IPK Peak Output Current (linear resistive operation) Source 3.5 A Sink 3.5 A Continuous Output Current Source/Sink IDC 200 mA POWER SUPPLY IS Power Supply Current Inputs = VS+ 1 2.5 mA IVH Off Leakage at VH VH = 0V 4 10 µA SWITCHING CHARACTERISTICS tR Rise Time CL = 2000pF 17 ns tF Fall Time CL = 2000pF 17 ns tRF∆ tR, tF Mismatch CL = 2000pF 0 ns tD-1 Turn-Off Delay Time CL = 2000pF 11.5 ns tD-2 Turn-On Delay Time CL = 2000pF 12 ns tD∆ tD-1-tD-2 Mismatch CL = 2000pF 0.5 ns tD-3 3-state Delay Enable 11 ns tD-4 3-state Delay Disable 11 ns 3 EL7155 Typical Performance Curves Package Power Dissipation vs Ambient Temperature JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board Input Threshold vs Supply Voltage T=25°C 1.8 Max TJ=125°C 1 High Threshold θJA=100°C/W 0.8 1.6 Input Voltage (V) Power Dissipation (W) PDIP8 0.6 SO8 0.4 θJA=160°C/W Hysteresis 1.4 1.2 Low Threshold 0.2 0 1.0 0 25 50 75 85 100 125 150 5 10 Ambient Temperature (°C) Supply Voltage (V) Quiescent Supply Current vs Supply Voltage T=25°C “On” Resistance vs Supply Voltage IOUT=200mA, T=25°C, VS+=VH, VL=0V 2.0 6 “On” Resistance (Ω) Supply Current (mA) VOUT-VL 5 1.6 All Inputs = GND 1.2 0.8 4 VOUT-VH 3 2 All Inputs = VS+ 0.4 1 0 0 5 15 10 5 7.5 Supply Voltage (V) 10 12.5 15 Supply Voltage (V) Rise/Fall Time vs Temperature CL=2000pF, VS+=15V Rise/Fall Time vs Supply Voltage CL=2000pF, T=25°C 30 20 18 Rise/Fall Time (ns) 25 Rise/Fall Time (ns) 15 tR 20 tI tF 15 tF 16 14 tR 12 tR 10 5 10 Supply Voltage (V) 4 15 10 -50 0 50 Temperature (°C) 100 150 EL7155 Typical Performance Curves (Continued) Propagation Delay vs Supply Voltage CL=2000pF, T=25°C Propagation Delay vs Temperature CL=2000pF, VS+=15V 14 17 12 15 tD-2 Delay Time (ns) Delay Time (ns) tD-2 13 tD-1 11 10 tD-1 8 9 5 10 6 -50 15 Supply Voltage (V) -25 0 25 50 75 100 125 Temperature (°C) Supply Current vs Load Capacitance VS+=VH=15V, VL=0V, T=25°C, f=20kHz Rise/Fall Time vs Load Capacitance VS+=+15V, T=25°C 70 5 60 Supply Current (mA) Rise/Fall Time (ns) 4 50 40 tF 30 20 0 100 1000 10000 Load Capacitance (pF) Supply Current (mA) 100 VS+=15V VS+=10V 1.0 VS+=5V 0.1 10k 100k Frequency (Hz) 5 1M 0 100 1000 Load Capacitance (pF) Supply Current vs Frequency CL=1000pF, T=25°C 10 2 1 tR 10 3 10M 10000 EL7155 Truth Table Operating Voltage Range OE IN VH TO OUTH OUTL TO VS- PIN MIN MAX 0 0 Open Open GND - VL -5 0 0 1 Open Open VS+ - VL 5 18 1 0 Closed Open VH - VL 0 18 1 1 Open Closed VS+ - VH 0 18 VS+ - GND 5 18 3-state Output VL VH Timing Diagrams 5V Input 2.5V 0 Inverted Output 90% 10% tD1 tD2 tF tR Standard Test Configuration VS+ VH 1 4.7µ VS+ 10k 0.1µ 2 OE IN 3 8 0.1µ L o g i c 4.7µ 7 OUT 6 2000p GND 4 5 - EL7155 0.1µ 6 4.7µ VL EL7155 Pin Descriptions PIN NAME FUNCTION 1 VS+ Positive Supply Voltage 2 OE Output Enable EQUIVALENT CIRCUIT VS+ INPUT VL Circuit 1 3 IN 4 GND 5 VL 6 OUTL Input Reference Circuit 1 Ground Negative Supply Voltage Lower Switch Output VS+ OUTL VL Circuit 2 7 OUTH Upper Switch Output VH VS+ VL OUTH VL Circuit 3 8 VH Upper Output Voltage Block Diagram OE VH VS+ IN Level Shifter 3-State Control OUTH OUTL GND VL 7 EL7155 Applications Information Product Description The EL7155 is a high performance 40MHz pin driver. It contains two analog switches connecting VH to OUTH and VL to OUTL. Depending on the value of the IN pin, one of the two switches will be closed and the other switch open. An output enable (OE) is also supplied which opens both switches simultaneously. Due to the topology of the EL7155, VL should always be connected to a voltage equal to, or lower than GND. VH can be connected to any voltage between VL and the positive supply, VS+. The EL7155 is available in both the 8-pin SO and the 8-pin PDIP packages. The relevant package should be chosen depending on the calculated power dissipation. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL7155 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125°C). It is necessary to calculate the power dissipation for a given application prior to selecting the package type. Power dissipation may be calculated: 2 2 PD = ( V S × I S ) + ( C INT × V S × f ) + ( C L × V OUT × f ) where: VS is the total power supply to the EL7155 (from VS+ to GND) VOUT is the swing on the output (VH - VL) 3-state Operation CL is the load capacitance When the OE pin is low, the output is 3-state (floating.) The output voltage is the parasitic capacitance’s voltage. It can be any voltage between VH and VL, depending on the previous state. At 3-state, the output voltage can be pushed to any voltage between VH and VL. The output voltage can’t be pushed higher than VH or lower than VL since the body diode at the output stage will turn on. CINT is the internal load capacitance (100pF max) IS is the quiescent supply current (3mA max) f is frequency Having obtained the application’s power dissipation, a maximum package thermal coefficient may be determined, to maintain the internal die temperature below TJMAX: ( T JMAX – T MAX ) θ JA = ---------------------------------------------PD Supply Voltage Range and Input Compatibility The EL7155 is designed for operation on supplies from 5V to 15V (4.5V to 18V maximum). The table on page 6 shows the specifications for the relationship between the VS+, VH, VL, and GND pins. All input pins are compatible with both 3V and 5V CMOS signals. With a positive supply (VS+) of 5V, the EL7155 is also compatible with TTL inputs. Power Supply Bypassing When using the EL7155, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7155 necessitate the use of a bypass capacitor between the VS+ and GND pins. It is recommended that a 2.2µF tantalum capacitor be used in parallel with a 0.1µF low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7155 is driving highly capacitive loads. where: TJMAX is the maximum junction temperature (125°C) TMAX is the maximum operating temperature PD is the power dissipation calculated above θJA thermal resistance on junction to ambient θJA is 160°C/W for the SO8 package and 100°C/W for the PDIP8 package when using a standard JEDEC JESD51-3 single-layer test board. If TJMAX is greater than 125°C when calculated using the equation above, then one of the following actions must be taken: Reduce θJA the system by designing more heat-sinking into the PCB (as compared to the standard JEDEC JESD51-3) Use the PDIP8 instead of the SO8 package De-rate the application either by reducing the switching frequency, the capacitive load, or the maximum operating (ambient) temperature (TMAX) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8