ATMEL AT24C64D Ic-compatible (2-wire) serial eeprom Datasheet

AT24C64D
I2C-Compatible (2-Wire) Serial EEPROM
64-Kbit (8,192 x 8)
DATASHEET
Features
 Low-voltage and standard-voltage operation

VCC = 1.7V to 5.5V
 Internally organized as 8,192 x 8 (64K)
 I2C-compatible (2-Wire) serial interface
 Schmitt Trigger, filtered inputs for noise suppression
 Bidirectional data transfer protocol
 400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) compatibility
 Write Protect pin for hardware protection
 32-byte Page Write mode

Partial Page Writes allowed
 Self-timed Write cycle (5ms max)
 High reliability


Endurance: 1,000,000 write cycles
Data retention: 100 years
 Lead-free/Halogen-free devices available
 Green package options (Pb/Halide-free/RoHS compliant)

8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 6-ball WLCSP,
5-ball WLCSP, and 8-ball VFBGA packages
 Die sale options: wafer form, waffle pack, and bumped wafers
Description
The Atmel® AT24C64D provides 65,536-bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 8,192 words of eight bits
each. The device’s cascading feature allows up to eight devices to share a common
2-wire bus. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The devices are
available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN,
8-pad XDFN, 6-ball WLCSP, 5-ball WLCSP, and 8-ball VFBGA packages. In addition,
this device operates from 1.7V to 5.5V.
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
1.
Pin Configurations and Pinouts
Table 1-1.
Pin
Function
A0
Address Input
A1
Address Input
8-lead TSSOP
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
SDA
5
Address Input
GND
Ground
SDA
Serial Data
SCL
Serial Clock Input
A0 1
8
VCC
A1 2
7
WP
WP
Write Protect
A2 3
6
SCL
GND 4
5
SDA
Note:
Device Power Supply
1.
2.
For use of the 6-ball WLCSP package,
the software bits A1 and A0 in the device
address word must be set to Logic 0 to
properly communicate. See Section 7.
Device Addressing on page 9 for more
details.
A0
A1
A2
GND
1
8
2
7
3
6
4
5
Top View
Top View
8-pad UDFN/XDFN
6-ball WLCSP
Top View
5-ball WLCSP
VCC
GND
SCL
SDA
WP
GND
VCC
A2
WP
(1)
Bottom View
(2)
8-ball VFBGA
VCC
8
1
A0
WP
7
2
A1
SCL
6
3
A2
SDA
5
4
GND
SDA
SCL
VCC
WP
SCL
SDA
For use of the 5-ball WLCSP package,
Bottom View
Bottom View
the three device address pins are not
* Note: Drawings are not to scale
available. For proper comunication with
the device, the software bits A2 and A1
must be set to Logic 0, while software bit
A0 must be set to Logic 1, resulting in a ‘001’ string in the device address byte for bits 3, 2, and 1. See
Section 7. Device Addressing on page 9 for more details.
Absolute Maximum Ratings*
Operating Temperature . . . . . . . . . . .−55°C to +125°C
Storage Temperature . . . . . . . . . . . −65°C to + 150°C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . . − 1.0 V +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . 5.0mA
2
8-lead SOIC
A2
VCC
2.
Pin Configuration
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions beyond those
indicated in the operational sections of this
specification are not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect device reliability.
3.
Block Diagram
VCC
GND
WP
Start
Stop
Logic
SDA
Serial
Control
Logic
LOAD
Device
Address
Comparator
A2
A1
A0
R/W
EN
H.V. Pump/Timing
COMP
LOAD
Data Word
Addr/Counter
Y DEC
Data Recovery
INC
X DEC
SCL
EEPROM
Serial MUX
DOUT/ACK
LOGIC
DIN
DOUT
4.
Pin Descriptions
Serial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge
clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device Addresses (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hard wired (directly to GND
or to VCC) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight 64K devices
may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7., “Device Addressing”
on page 9). A device is selected when a corresponding hardware and software match is true. If these pins are left
floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may
appear during customer applications, Atmel recommends always connecting the address pins to a known state. When
using a pull-up resistor, Atmel recommends using 10k or less.
Write Protect (WP): The Write Protect input, when connected to GND, allows normal Write operations. When WP is
connected directly to VCC, all Write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND: however, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using
10k or less.
Table 4-1.
Write Protect
WP Pin Status
Part of the Array Protected
At VCC
Full Array
At GND
Normal Read/Write Operations
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
3
5.
Memory Organization
AT24C64D, 64K Serial EEPROM: The 64K is internally organized as 256 pages of 32-bytes each. Random word
addressing requires a 13-bit data word address.
Table 5-1.
Pin Capacitance(1)
Applicable over recommended operating range from: TA = 25°C, f = 1.0MHz, VCC = 5.5V
Symbol
Test Condition
CI/O
CIN
Note:
1.
Table 5-2.
Max
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, and SCL)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = 1.7V to 5.5V (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
ICC1
Supply Current
VCC = 5.0V
Read at 400kHz
ICC2
Supply Current
VCC = 5.0V
Write at 400kHz
ISB1
Standby Current
ILI
Input Leakage
Current VCC = 5.0V
VIN = VCC or VSS
ILO
Output Leakage
Current VCC = 5.0V
VOUT = VCC or VSS
VIL
Input Low Level(1)
VIH
Input High Level((1)
VOL1
Output Low Level
VCC = 1.7V
VOL2
Output Low Level
VCC = 3.0V
Note:
4
1.
Test Condition
Min
Max
Units
5.5
V
0.4
1.0
mA
2.0
3.0
mA
1.0
μA
6.0
μA
0.10
3.0
μA
0.05
3.0
μA
-0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
IOL = 0.15mA
0.2
V
IOL = 2.1mA
0.4
V
1.7
VCC = 1.7V
VCC = 5.0V
VIN = VCC or VSS
VIL min and VIH max are reference only and are not tested.
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
Typ
Table 5-3.
AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = 1.7V to 5.5V, CL = 100pF (unless
otherwise noted). Test conditions are listed in Note 2.
1.7V
Symbol
Parameter
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
tHIGH
Clock Pulse Width High
2.5V, 5.0V
Max
Min
400
Max
Units
1000
kHz
1300
400
ns
600
400
ns
(1)
tI
Noise Suppression Time
100
tAA
Clock Low to Data Out Valid
tBUF
Time the bus must be free before a new transmission can start(1)
1300
500
ns
tHD.STA
Start Hold Time
600
250
ns
tSU.STA
Start Set-up Time
600
250
ns
tHD.DAT
Data In Hold Time
0
0
ns
tSU.DAT
Data In Set-up Time
100
100
ns
tR
Inputs Rise Time(1)
50
(1)
900
50
50
ns
550
ns
300
300
ns
300
100
ns
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
600
250
ns
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
5
Endurance(1)
25°C, Page Mode, 3.3V
1,000,000
Notes: 1.
2.
5
ms
Write
Cycles
This parameter is ensured by characterization and is not 100% tested.
AC measurement conditions:

RL (connects to VCC): 1.3kΩ (2.5V, 5.5V), 10kΩ (1.7V)

Input pulse voltages: 0.3VCC to 0.7VCC

Input rise and fall times: ≤ 50ns

Input and output timing reference voltages: 0.5 x VCC
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
5
6.
Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (See Figure 6-1). Data changes during SCL high periods will indicate a start or
stop condition as defined below.
Figure 6-1.
Data Validity
SDA
SCL
Data Stable
Data Stable
Data
Change
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition that must precede every command
(See Figure 6-2).
Figure 6-2. Start and Stop Definition
SDA
SCL
Start
Condition
Stop
Condition
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a Read sequence, the Stop
Condition will place the EEPROM in a standby power mode (See Figure 6-2).
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
receiving device sends a zero during the ninth clock cycle to acknowledge that it has received each word. This zero
response is referred to as an Acknowledge (See Figure 6-6).
Standby Mode: The AT24C64D features a low-power standby mode that is enabled upon power-up and after the receipt
of the Stop condition and the completion of any internal operations.
6
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by
following these steps:
1.
Create a Start condition,
2.
Clock nine cycles,
3.
Create another Start followed by Stop condition as shown below.
The device is ready for next communication after above steps has been completed.
Figure 6-3. Software Reset
Dummy Clock Cycles
1
SCL
2
3
8
9
Start
Condition
Start
Condition
Stop
Condition
SDA
Figure 6-4. Bus Timing
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tAA
tDH
tBUF
SDA Out
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
7
Figure 6-5. Write Cycle Timing
SCL
SDA
8th Bit
ACK
WORDN
tWR
Start
Condition
Stop
Condition
Note:
1.
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of
the internal clear/write cycle.
Figure 6-6. Output Acknowledge
1
SCL
8
9
Data In
Data Out
Start
Condition
8
(1)
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
Acknowledge
7.
Device Addressing
The 64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write
operation. The device address word consists of a mandatory ‘1010’ sequence for the first four most significant bits
(bit 7, bit 6, bit 5, and bit 4 as seen in Figure 7-1). This is common to all 2-wire Serial EEPROM devices.
The next three bits are the A2, A1, and A0 device address bits to allow as many as eight devices on the same bus. These
bits must compare to their corresponding hard wired input pins, where applicable. The A2, A1, and A0 pins use an internal
proprietary circuit that pulls them to GND if the pins are allowed to float.
When utilizing the 6-ball WLCSP package, the A1 and A0 pins are not available and are internally pulled to ground;
therefore, the A1 and A0 device address bits must always be set to a Logic 0 condition to communicate with the device.
This condition is depicted in Figure 7-1 below.
When utilizing the 5-ball WLCSP package, the A2, A1 and A0 pins are not available. The A2 and A1 pins are internally
pulled to ground and thus the A2 and A1 device address bits must always be set to a Logic 0 condition to communicate
with the device. The A0 pin is internally connected to VCC in this specific package only; therefore, the A0 software bit must
be set to Logic 1 to communicate to the device. This condition is depicted in Figure 7-1 below.
The eighth bit of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit is high,
and a Write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return
to a standby state.
Figure 7-1. Device Addressing
Package
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SOIC, TSSOP, UDFN,
XDFN, and VFBGA
1
0
1
0
A2
A1
A0
R/W
6-ball WLCSP
1
0
1
0
A2
0
0
R/W
5-ball WLCSP
1
0
1
0
0
0
1
R/W
MSB
LSB
Data Security: AT24C64D has a hardware data protection scheme that allows the user to Write protect the whole
memory when the WP pin is at VCC.
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
9
8.
Write Operations
Byte Write: A Write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero, and then clock in the first
8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as
a microcontroller, must then terminate the Write sequence with a Stop condition. At this time, the EEPROM enters an
internally-timed Write cycle, tWR, to the nonvolatile memory (See Figure 6-5). All inputs are disabled during this Write
cycle and the EEPROM will not respond until the Write is complete (See Figure 8-1).
Figure 8-1. Byte Write
S
T
A
R
T
Device
Address
W
R
I
T
E
First
Word Address
Second
Word Address
S
T
O
P
Data
SDA Line
M
S
B
Note:
R A
/ C
W K
A
C
K
A
C
K
A
C
K
* = Don’t care bit.
Page Write: The 64K EEPROM is capable of 32-byte Page Writes.
A Page Write is initiated the same way as a Byte Write, but the microcontroller does not send a Stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller
can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The
microcontroller must terminate the Page Write sequence with a Stop condition (See Figure 8-2).
Figure 8-2. Page Write
S
T
A
R
T
Device
Address
W
R
I
T
E
First
Word Address
Second
Word Address
Data (n)
S
T
O
P
Data (n + x)
SDA Line
M
S
B
Note:
R A
/ C
WK
A
C
K
A
C
K
A
C
K
A
C
K
* = Don’t care bit.
The data word address lower five bits are internally incremented following the receipt of each data word. The higher data
word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32
data words are transmitted to the EEPROM, the data word address will roll-over and the previously loaded data will be
altered. The address roll-over during Write is from the last byte of the current page to the first byte of the same page.
Acknowledge Polling: Once the internally-timed Write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The
Read/Write bit is representative of the operation desired. Only if the internal Write cycle has completed will the EEPROM
respond with a zero, allowing the Read or Write sequence to continue.
10
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
9.
Read Operations
Read operations are initiated the same way as Write operations with the exception that the Read/Write select bit in the
device address word is set to one. There are three Read operations:

Current Address Read

Random Address Read

Sequential Read
Current Address Read: The internal data word address counter maintains the last address accessed during the last
Read or Write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address roll-over during read is from the last byte of the last memory page, to the first byte of the first
page.
Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input zero but does
generate a Stop condition (See Figure 9-1).
Figure 9-1. Current Address Read
S
T
A
R
T
Device
Address
R
E
A
D
S
T
O
P
Data
SDA Line
M
S
B
N
O
R A
/ C
WK
A
C
K
Random Read: A Random Read requires a dummy Byte Write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another Start condition. The microcontroller now initiates a Current Address Read by sending a device address
with the Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks out the data
word. The microcontroller does not respond with a zero but does generate a Stop condition. (See Figure 9-2)
Figure 9-2. Random Read
S
T
A
R
T
Device
Address
W
R
I
T
E
First Word
Address
S
T
A
R
T
Second Word
Address
Device
Address
R
E
A
D
S
T
O
P
Data (n)
SDA LINE
M
S
B
R A
/ C
W K
A
C
K
Dummy Write
Note:
L A
S C
B K
R A
/ C
WK
N
O
A
C
K
* = Don’t care bit.
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
11
Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After
the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the
memory address maximum address is reached, the data word address will roll-over and the Sequential Read will
continue from the beginning of the array. The Sequential Read operation is terminated when the microcontroller does not
respond with a zero but does generate a Stop condition (See Figure 9-3).
Figure 9-3. Sequential Read
S
T
A
R
T
W
R
I
T
E
Device
Address
First Word
Address
Second Word
Address
...
SDA LINE
R A
/ C
W K
M
S
B
L A
S C
B K
A
C
K
Dummy Write
S
T
A
R
T
Device
Address
R
E
A
D
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
...
R A
/ C
WK
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Note:
12
* = Don’t care bit.
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
10.
Ordering Code Detail
AT2 4 C 6 4 D - S S H M - B
Atmel Designator
Shipping Carrier Option
B
T
Product Family
24C = Standard I2C Serial EEPROM
Device Density
64 = 64K
Device Revision
= Bulk (Tubes)
= Tape and Reel
Operating Voltage
M = 1.7V to 5.5V
Package Device Grade or
Wafer/Die Thickness
H
= Green, NiPdAu Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
U = Green, Matte Sn Lead Finish,
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil Wafer Thickness
Package Option
SS
X
MA
ME
U
U1
C
WWU
WDT
= JEDEC SOIC
= TSSOP
= UDFN
= XDFN
= 6-ball, 2x3 Grid Array, WLCSP
= 5-ball, 3x3 Grid Array, WLCSP
= VFBGA
= Wafer Unsawn
= Die in Tape and Reel
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
13
11.
Part Markings
AT24C64D: Package Marking Information
8-lead SOIC
8-lead TSSOP
8-pad XDFN
1.8 x 2.2 mm Body
ATHYWW
###% @
AAAAAAA
ATMLHYWW
###%
@
AAAAAAAA
8-pad UDFN
6-ball & 5-ball WLCSP
2.0 x 3.0 mm Body
8-ball VFBGA
1.5 x 2.0 mm Body
###
H%@
YXX
Note 1:
###
YXX
###%
UYMXX
###U
YMXX
PIN 1
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24C64D
Truncation Code ###: 64D
Date Codes
Y = Year
2: 2012
3: 2013
4: 2014
5: 2015
Voltages
6: 2016
7: 2017
8: 2018
9: 2019
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Assembly
Lot Number
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Trace Code
% = Minimum Voltage
M: 1.7V min
Grade/Lead Finish Material
U: Industrial/Matte Tin/SnAguCu
H: Industrial/NiPdAu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
3/8/13
TITLE
Package Mark Contact:
[email protected]
14
24C64DSM, AT24C64D Package Marking Information
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
DRAWING NO.
REV.
24C64DSM
D
12.
Ordering Codes
12.1
Atmel AT24C64D Ordering Information
Ordering Code
Lead Finish
Package
Voltage
Operating Range
1.7V to 5.5V
Industrial Temperature
(−40°C to 85°C)
AT24C64D-SSHM-B(1)
8S1
AT24C64D-SSHM-T(2)
AT24C64D-XHM-B(1)
(2)
AT24C64D-XHM-T
NiPdAu
(Lead-free/Halogen-free)
AT24C64D-MAHM-T(2)
8X
8MA2
AT24C64D-MEHM-T(2)
8ME1
AT24C64D-UUM-T(2)
6U-1
AT24C64D-U1UM-T(2)
SnAgCu
(Lead-free/Halogen-free)
AT24C64D-CUM-T(2)
AT24C64D-WWU11M(3)
Notes: 1.
3.
8U2-1
—
Wafer Sale
Bulk delivery in tubes:

2.
5U-2
SOIC and TSSOP = 100 per tube
Tape and reel delivery:

SOIC = 4k per reel

TSSOP, UDFN, XDFN, WLCSP, and VFBGA = 5k per reel
Contact Atmel Sales for Wafer sales.
Package Type
8S1
8-lead, 0.150” wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.40mm body, Plastic Thin Shrink Small Outline (TSSOP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Dual No Lead (UDFN)
8ME1
8-pad, 1.80mm x 2.20mm body, Extra Thin DFN (XDFN)
6U-1
6-ball, 2x3 Grid Array, Wafer Level Chip Scale (WLCSP)
5U-2
5-ball, 3x3 Grid Array, Wafer Level Chip Scale (WLCSP)
8U2-1
8-ball, Die Ball Grid Array (VFBGA)
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
15
13.
Packaging Information
13.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
[email protected]
16
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
GPC
SWB
DRAWING NO.
REV.
8S1
G
13.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
A2
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
E1
4.30
4.40
4.50
3, 5
b
0.19
–
0.30
4
SYMBOL
D
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
E
NOTE
2, 5
6.40 BSC
e
0.65 BSC
L
0.45
0.60
0.75
L1
1.00 REF
C
0.09
-
0.20
6/22/11
TITLE
Package Drawing Contact:
[email protected]
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
GPC
TNR
DRAWING NO.
8X
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
REV.
D
17
13.3
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
A2
A
A1
E2
COMMON DIMENSIONS
(Unit of Measure = mm)
b (8x)
8
1
7
2
Pin#1 ID
6
D2
3
5
4
e (6x)
K
L (8x)
SYMBOL
MIN
NOM
MAX
D
1.90
2.00
2.10
E
2.90
3.00
3.10
D2
1.40
1.50
1.60
E2
1.20
1.30
1.40
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
–
–
0.55
C
L
NOTE
0.152 REF
0.30
e
0.35
0.40
0.50 BSC
b
0.18
0.25
0.30
K
0.20
–
–
3
9/6/12
Package Drawing Contact:
[email protected]
18
TITLE
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
GPC
YNZ
DRAWING NO.
8MA2
REV.
C
13.4
8ME1 — 8-pad XDFN
D
7
8
6
5
E
PIN #1 ID
2
1
3
4
A1
Top View
A
Side View
e1
b
L
COMMON DIMENSIONS
(Unit of Measure = mm)
0.10
PIN #1 ID
0.15
b
e
End View
SYMBOL
MIN
NOM
MAX
A
–
–
0.40
A1
0.00
–
0.05
D
1.70
1.80
1.90
E
2.10
2.20
2.30
b
0.15
0.20
0.25
e
0.40 TYP
e1
1.20 REF
L
0.26
0.30
NOTE
0.35
9/10/2012
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
REV.
8ME1, 8-pad (1.80mm x 2.20mm body) Extra Thin DFN
(XDFN)
DTP
8ME1
B
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
19
13.5
6U-1 — 6-ball WLCSP
BALL SIDE
TOP VIEW
1
A1 CORNER
2
A
3
d
A
1
2
3
A1 CORNER
0.015 C
A
D
d1
B
B
nb
E
B
j
A
e1
n 0.015 m C
n 0.05 m C A B
A2
SIDE VIEW
C
d
0.075 C
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
PIN ASSIGNMENT MATRIX
1
2
3
SYMBOL
MIN
TYP
MAX
A
SCL
WP
VCC
A
0.270
0.309
0.348
SDA
GND
A2
A1
0.0779
-
0.139
B
A2
0.175
0.200
0.225
E
Contact Atmel for details
e1
0.40
D
Contact Atmel for details
d1
0.40
b
0.148
0.168
NOTE
0.188
Note: 1. Dimensions are NOT to scale.
3/15/13
Package Drawing Contact:
[email protected]
20
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
TITLE
6U-1, 6-ball Wafer Level Chip Scale Package
(WLCSP)
GPC
DRAWING NO.
REV.
GDM
6U-1
A
13.6
5U-2 — 5-ball WLCSP
BALL SIDE
TOP VIEW
e2
1 2 3
A1 CORNER
-B-
3 2
e1
A1 CORNER
1
A
A
d2
B
B
E
C
C
Øb(5X)
D
-Ad
d1
n 0.015m C
n 0.05m C A B
j
0.03 (4X)
d
SIDE VIEW
0.03 C
A
A2
Note: Dimensions are NOT to scale.
-C-
A1
PIN ASSIGNMENT MATRIX
1
2
3
A
VCC
n/a
GND
B
n/a
SDA
n/a
C
WP
n/a
SCL
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
TYP
MAX
A
0.270
0.309
0.348
A1
0.078
-
0.139
A2
0.175
0.200
0.225
E
Contact Atmel for details
e1
0.693
e2
D
0.3465
Contact Atmel for details
d1
0.4
d2
0.4
b
NOTE
0.148
0.168
0.188
7/30/13
Package Drawing Contact:
[email protected]
TITLE
GPC
DRAWING NO.
REV.
5U-2, 5-ball Wafer Level Chip Scale Package
(WLCSP)
GPK
5U-2
A
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
21
13.7
8U2-1 — 8-ball VFBGA
f 0.10 C
d 0.10
A1 BALL
PAD
CORNER
(4X)
d 0.08 C
C
A
D
A1 BALL PAD CORNER
2
1
Øb
A
j n0.15 m C A B
j n0.08 m C
B
e
E
C
D
(e1)
A1
B
d
A2
(d1)
A
TOP VIEW
BOTTOM VIEW
SIDE VIEW
8 SOLDER BALLS
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
Notes:
1. This drawing is for general information.
2. Dimension 'b' is measured at the maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
A
A1
A2
b
D
E
e
e1
d
d1
MIN
0.81
0.15
0.40
0.25
NOM
0.91
0.20
0.45
0.30
2.35 BSC
3.73 BSC
0.75 BSC
0.74 REF
0.75 BSC
0.80 REF
MAX
NOTE
1.00
0.25
0.50
0.35
3/20/12
TITLE
Package Drawing Contact:
[email protected]
22
8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch,
VFBGA Package
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
GPC
DRAWING NO.
GWW
8U2-1
REV.
F
14.
Revision History
Doc. Rev.
Date
8850A
08/2013
Comments
Inital document release.
AT24C64D [DATASHEET]
Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013
23
XXXXXX
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T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
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© 2013 Atmel Corporation. / Rev.: Atmel-8850A-SEEPROM-AT24C64D-Datasheet_082013.
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