Cypress CY14V101LA 1-mbit (128 k x 8/64 k x 16) nvsram infinite read, write, and recall cycle Datasheet

CY14V101LA
CY14V101NA
1-Mbit (128 K × 8/64 K × 16) nvSRAM
1-Mbit (128 K × 8/64 K × 16) nvSRAM
Features
Functional Description
■
25 ns and 45 ns access times
■
Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16
(CY14V101NA)
■
Hands off automatic STORE on power down with only a small
capacitor
■
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power down
■
RECALL to SRAM initiated by software or power up
■
Infinite read, write, and recall cycles
■
1 million STORE cycles to QuantumTrap
■
20 year data retention
■
Core VCC = 3.0 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
■
Industrial temperature
■
48-ball fine-pitch ball grid array (FBGA) package
■
Pb-free and restriction of hazardous substances (RoHS)
compliance
The Cypress CY14V101LA/CY14V101NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 128 K bytes of 8 bits each or 64 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
Logic Block Diagram [1, 2, 3]
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
VCC
Quatrum Trap
1024 X 1024
R
O
W
VCCQ VCAP
POWER
CONTROL
STORE
RECALL
D
E
C
O
D
E
R
STORE/RECALL
CONTROL
STATIC RAM
ARRAY
1024 X 1024
SOFTWARE
DETECT
HSB
A14 - A2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
I
N
P
U
T
B
U
F
F
E
R
S
COLUMN I/O
OE
COLUMN DEC
WE
DQ12
DQ13
CE
DQ14
A0 A1
DQ15
BLE
A2 A3 A4 A10 A11
BHE
Notes
1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-53953 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 4, 2011
[+] Feedback
CY14V101LA
CY14V101NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
Hardware STORE Operation ............................................ 4
Hardware RECALL (Power-Up) ....................................... 5
Software STORE ............................................................... 5
Software RECALL ............................................................. 5
Preventing AutoStore ....................................................... 6
Data Protection ................................................................. 6
Noise Considerations ....................................................... 6
Best Practices ................................................................... 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
DC Electrical Characteristics .......................................... 8
Data Retention and Endurance ....................................... 9
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads ................................................................ 10
AC Test Conditions ........................................................ 10
Document #: 001-53953 Rev. *H
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 11
Switching Waveforms .................................................... 11
AutoStore/Power-up RECALL ....................................... 14
Switching Waveforms .................................................... 14
Software Controlled STORE/RECALL Cycle ................ 15
Switching Waveforms .................................................... 15
Hardware STORE Cycle ................................................. 16
Switching Waveforms .................................................... 16
Truth Table For SRAM Operations ................................ 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Page 2 of 22
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CY14V101LA
CY14V101NA
Pinouts
Figure 1. Pin Diagram – 48-ball FBGA
(× 8)
(× 16)
Top View
(not to scale)
Top View
(not to scale)
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
VCC
A
NC
B
DQ8
BHE
A3
A4
CE
DQ0
B
NC
DQ4
C
DQ9 DQ10
A5
A6
DQ1
DQ2
C
A7
DQ5
VCCQ
D
VSS
A7
DQ3 VCCQ
2
3
4
5
6
NC
OE
A0
A1
A2
VCC
NC
NC
A3
A4
CE
DQ0
NC
A5
A6
VSS
DQ1
[4]
NC
1
[5]
DQ11 NC
[4]
VCAP NC
DQ4
VCCQ
DQ2
VCAP
A16
DQ6
VSS
E
VCCQ DQ12
DQ3
NC
A14
A15
NC
DQ7
F
DQ14 DQ13
A14
A15
NC
HSB
A12
A13
WE
NC
G
DQ15 HSB
A12
[5]
NC
A8
A9
A10
A11
H
NC
A9
NC
[6]
[6]
A8
D
VSS
E
DQ5
DQ6
F
A13
WE
DQ7
G
A10
A11
NC
H
Pin Definitions
Pin Name
I/O Type
Description
Address inputs. Used to select one of the 131,072 bytes of the nvSRAM for × 8 configuration.
A0–A16
Input
A0–A15
Address inputs. Used to select one of the 65,536 words of the nvSRAM for × 16 configuration.
Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.
DQ0–DQ7
Input/Output
DQ0–DQ15
Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation.
WE
Input
Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input
Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
Input
Output enable, active LOW. The active LOW OE input enables the data output buffers during read cycles.
OE
I/O pins are tri-stated on deasserting OE HIGH.
Input
Byte
high enable, active LOW. Controls DQ15–DQ8.
BHE
Input
Byte low enable, active LOW. Controls DQ7–DQ0.
BLE
VSS
Ground
Ground for the device. Must be connected to the ground of the system.
VCC
Power supply Power supply inputs to the core of the device.
VCCQ
Power supply Power supply inputs for the inputs and outputs of the device.
HSB
Input/Output Hardware STORE busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a non-volatile STORE operation. After each hardware
and software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
No connect No connect. This pin is not connected to the die.
NC
Notes
4. Address expansion for 2-Mbit. NC pin not connected to die.
5. Address expansion for 4-Mbit. NC pin not connected to die.
6. Address expansion for 8-Mbit. NC pin not connected to die.
Document #: 001-53953 Rev. *H
Page 3 of 22
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CY14V101LA
CY14V101NA
The CY14V101LA/CY14V101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a non-volatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the non-volatile cell (the STORE
operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations, SRAM read and write operations are inhibited. The
CY14V101LA/CY14V101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the non-volatile cells and up to 1 million STORE
operations. Refer to the Truth Table For SRAM Operations on
page 17 for a complete description of read and write modes.
SRAM Read
The CY14V101LA/CY14V101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–16 or A0–15 determines which of the 131,072
data bytes or 65,536 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
buffers tHZWE after WE goes LOW.
AutoStore on page 6. If AutoStore is enabled without a capacitor
on VCAP pin, the device attempts an AutoStore operation without
sufficient charge to complete the Store. This corrupts the data
stored in nvSRAM.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 8 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. Place a
pull-up on WE to hold it inactive during power up. This pull-up is
only effective if the WE signal is tristate during power up. Many
MPUs tristate their controls on power-up. This must be verified
when using the pull-up. When the nvSRAM comes out of
power-on-RECALL, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 2. AutoStore Mode
VCCQ
VCC
0.1 uF
0.1 uF
10 kOhm
Device Operation
VCCQ
VCC
WE
VCAP
VCAP
VSS
AutoStore Operation
Hardware STORE Operation
The CY14V101LA/CY14V101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power down. The
AutoStore operation is a unique feature of QuantumTrap
technology
and
is
enabled
by
default
on
the
CY14V101LA/CY14V101NA.
The CY14V101LA/CY14V101NA provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14V101LA/CY14V101NA conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE (initiated by any means) is in progress.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled using the soft sequence specified in Preventing
Document #: 001-53953 Rev. *H
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Page 4 of 22
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CY14V101LA
CY14V101NA
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14V101LA/CY14V101NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14V101LA/CY14V101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by
a
software
address
sequence.
The
CY14V101LA/CY14V101NA Software STORE cycle is initiated
by executing sequential CE or OE controlled read cycles from six
specific address locations in exact order. During the STORE
cycle an erase of the previous non-volatile data is first performed,
followed by a program of the non-volatile elements. After a
STORE cycle is initiated, further input and output are disabled
until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the non-volatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
Table 1. Mode Selection
CE
WE
OE
BHE, BLE[7]
A15–A0[8]
Mode
I/O
Power
H
X
X
X
X
Not selected
Output High Z
Standby
L
H
L
L
X
Read SRAM
Output data
Active
L
L
X
L
X
Write SRAM
Input data
Active
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output data
Output data
Output data
Output data
Output data
Output data
Active[9]
Notes
7. BHE and BLE are applicable for x16 configuration only.
8. While there are 17 address lines on the CY14V101LA (16 address lines on the CY14V101NA), only the 13 address lines (A14–A2) are used to control software modes.
Rest of the address lines are don’t care.
9. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-53953 Rev. *H
Page 5 of 22
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CY14V101LA
CY14V101NA
Table 1. Mode Selection (continued)
CE
WE
OE
BHE, BLE[7]
A15–A0[8]
Mode
I/O
Power
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output data
Output data
Output data
Output data
Output data
Output data
Active[10]
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
STORE
Active ICC2[10]
Output data
Output data
Output data
Output data
Output data
Output High Z
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
Active[10]
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The CY14V101LA/CY14V101NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected
when
VCC
<
VSWITCH.
If
the
CY14V101LA/CY14V101NA is in a write mode (both CE and WE
are LOW) at power up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). When VCCQ < VIODIS, I/Os are disabled (no STORE
takes place). This protects against inadvertent writes during
brown out conditions on VCCQ supply.
Noise Considerations
Refer to CY application note AN1064.
Note
10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-53953 Rev. *H
Page 6 of 22
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CY14V101LA
CY14V101NA
Best Practices
nvSRAM products have been used effectively for over 26 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The non-volatile cells in this nvSRAM product are delivered
from Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Document #: 001-53953 Rev. *H
■
Power up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autoStore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this maximum VCAP value. Customers
that want to use a larger VCAP value to make sure there is extra
store charge and store time should discuss their VCAP size
selection with Cypress to understand any impact on the VCAP
voltage level at the end of a tRECALL period.
Page 7 of 22
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CY14V101LA
CY14V101NA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................–65 C to +150 C
Maximum accumulated storage time:
At 150 C ambient temperature ...................... 1000 h
At 85 C ambient temperature ..................... 20 Years
Ambient temperature
with power applied ...................................–55 C to +150 C
Supply voltage on VCC relative to VSS .......... –0.5 V to 4.1 V
Supply voltage on VCCQ relative to VSS ...... –0.5 V to 2.45 V
Transient voltage (< 20 ns) on
any pin to ground potential ............... –2.0 V to VCCQ + 2.0 V
Package power dissipation
capability (TA = 25 °C) ..................................................1.0 W
Surface mount Pb soldering
temperature (3 seconds) ..........................................+260 C
DC output current
(1 output at a time, 1s duration) ..................................15 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch up current ................................................... > 140 mA
Operating Range
Voltage applied to outputs
in High Z State .................................. –0.5 V to VCCQ + 0.5 V
Range
Input voltage ..................................... –0.5 V to VCCQ + 0.5 V
Industrial
Ambient
Temperature
VCC
VCCQ
–40 C to +85 C 3.0 V to 3.6 V 1.65 V to 1.95 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VCC
Description
Test Conditions
Power supply voltage
VCCQ
Min
Typ [11]
Max
Unit
3.0
3.3
3.6
V
1.65
1.8
1.95
V
–
–
70
mA
–
–
52
mA
–
–
25
mA
ICC1
Average VCC current
ICCQ1
Average VCCQ current
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
–
–
15
mA
ICC2
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
10
mA
ICC3
Average VCC current at
tRC= 200 ns, VCC(Typ), 25 °C
–
35
–
mA
ICCQ3
Average VCCQ current at
tRC= 200 ns, VCCQ(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA)
–
5
–
mA
ICC4
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current
for duration tSTORE
–
–
8
mA
ISB
VCC standby current
CE > (VCCQ – 0.2 V).
VIN < 0.2 V or > (VCCQ – 0.2 V).
Standby current level after
non-volatile cycle is complete. Inputs
are static. f = 0 MHz
–
–
8
mA
IIX[12]
Input leakage current
(except HSB)
VCCQ = Max, VSS < VIN < VCCQ
–1
–
+1
µA
Input leakage current (for HSB)
VCCQ = Max, VSS < VIN < VCCQ
–100
–
+1
µA
Notes
11. Typical values are at 25 °C, VCC = VCC(Typ) and VCCQ= VCCQ(Typ). Not 100% tested.
12. The HSB pin has IOUT = –4 µA for VOH of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document #: 001-53953 Rev. *H
Page 8 of 22
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CY14V101LA
CY14V101NA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
IOZ
Description
Test Conditions
Off-state output leakage current VCCQ = Max, VSS < VOUT < VCCQ,
CE or OE > VIH or BHE/BLE > VIH or
Min
Typ [11]
Max
Unit
–1
–
+1
µA
WE < VIL
VIH
Input HIGH voltage
–
0.7 VCCQ
–
VCCQ + 0.3
V
VIL
Input LOW voltage
–
– 0.3
–
0.3 VCCQ
V
VOH
Output HIGH voltage
IOUT = –1 mA
VCCQ – 0.45
–
–
V
VOL
Output LOW voltage
IOUT = 2 mA
–
–
0.45
V
VCAP[13]
Storage capacitor
Between VCAP pin and VSS, 5 V
Rated
61
68
180
µF
Data Retention and Endurance
Parameter
Description
Min
Unit
20
Years
1,000
K
Max
Unit
7
pF
Input capacitance (for BHE, BLE
and HSB)
8
pF
Output capacitance (except HSB)
7
pF
Output capacitance (for HSB)
8
pF
DATAR
Data retention
NVC
Non-volatile STORE operations
Capacitance
Parameter[14]
CIN
COUT
Description
Input capacitance (except BHE,
BLE and HSB)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = VCC(Typ), VCCQ = VCCQ(Typ)
Thermal Resistance
Parameter[14]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and procedures
for measuring thermal impedance, in accordance with
EIA/JESD51.
48-ball FBGA Unit
48.19
C/W
6.5
C/W
Notes
13. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on
VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it
is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
14. These parameters are guaranteed by design and are not tested.
Document #: 001-53953 Rev. *H
Page 9 of 22
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CY14V101LA
CY14V101NA
AC Test Loads
Figure 3. AC Test Loads
450 
1.8 V
450 
1.8 V
R1
for tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
450 
5 pF
R2
450 
AC Test Conditions
Input pulse levels................................................. 0 V to 1.8 V
Input rise and fall times (10% to 90%)...................... < 1.8 ns
Input and output timing reference levels ....................... 0.9 V
Document #: 001-53953 Rev. *H
Page 10 of 22
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CY14V101LA
CY14V101NA
AC Switching Characteristics
Over the Operating Range
Parameters [15]
Cypress
Alt
Parameters
Parameters
SRAM Read Cycle
tACE
tACS
[16]
tRC
tRC
25 ns
Description
Chip enable access time
Read cycle time
45 ns
Min
Max
Min
Max
–
25
25
–
–
45
45
–
Unit
ns
ns
tAA
Address access time
–
25
–
45
ns
tDOE
tOE
Output enable to data valid
–
12
–
20
ns
tOH
Output hold after address change
3
–
3
–
ns
tLZCE[18, 19]
tHZCE[18, 19]
tLZOE[18, 19]
tHZOE[18, 19]
tPU[18]
tPD[18]
tDBE[[18]
tLZBE[18]
tHZBE[18]
tLZ
Chip enable to output active
3
–
3
–
ns
tHZ
Chip disable to output inactive
–
10
–
15
ns
tOLZ
Output enable to output active
0
–
0
–
ns
tOHZ
Output disable to output inactive
–
10
–
15
ns
tPA
Chip enable to power active
0
–
0
–
ns
tPS
Chip disable to power standby
–
25
–
45
ns
–
–
–
SRAM Write Cycle
tWC
tWC
tPWE
tWP
tCW
tSCE
tSD
tDW
tHD
tDH
tAW
tAW
tSA
tAS
tHA
tWR
[18,
19,
20]
tWZ
tHZWE
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
–
0
–
12
–
10
–
0
–
20
–
15
ns
ns
ns
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
25
20
20
10
0
20
0
0
–
–
–
–
–
–
–
–
–
10
45
30
30
15
0
30
0
0
–
–
–
–
–
–
–
–
–
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA[17]
tOHA[17]
tLZWE[18, 19]
tBW
tOW
Output active after end of write
3
–
3
–
ns
–
Byte enable to end of write
20
–
30
–
ns
Switching Waveforms
Figure 4. SRAM Read Cycle #1 (Address Controlled) [16, 17, 21]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
15. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of VCCQ/2, input pulse levels of 0 to VCC Q(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 3 on page 10.
16. WE must be HIGH during SRAM read cycles.
17. Device is continuously selected with CE, OE and BHE / BLE LOW.
18. These parameters are guaranteed by design and are not tested.
19. Measured ±200 mV from steady state output voltage.
20. If WE is low when CE goes low, the outputs remain in the high-impedance state.
21. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-53953 Rev. *H
Page 11 of 22
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CY14V101LA
CY14V101NA
Switching Waveforms (continued)
Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [22, 23, 24]
Address
Address Valid
tRC
tHZCE
tACE
CE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
Data Output
High Impedance
Output Data Valid
tPU
ICC
tPD
Active
Standby
Figure 6. SRAM Write Cycle #1 (WE Controlled) [22, 24, 25, 26]
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
tSA
tSD
Data Input
Input Data Valid
tHZWE
Data Output
tHD
Previous Data
tLZWE
High Impedance
Notes
22. BHE and BLE are applicable for × 16 configuration only.
23. WE must be HIGH during SRAM read cycles.
24. HSB must remain HIGH during READ and WRITE cycles.
25. If WE is low when CE goes low, the outputs remain in the high impedance state.
26. CE or WE must be > VIH during address transitions.
Document #: 001-53953 Rev. *H
Page 12 of 22
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CY14V101LA
CY14V101NA
Switching Waveforms (continued)
Figure 7. SRAM Write Cycle #2 (CE Controlled) [27, 28, 29, 30]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 8. SRAM Write Cycle #3 (BHE and BLE Controlled) [27, 28, 29, 30]
tWC
Address
Address Valid
tSCE
CE
tSA
tHA
tBW
BHE, BLE
tAW
tPWE
WE
tSD
Data Input
tHD
Input Data Valid
High Impedance
Data Output
Notes
27. BHE and BLE are applicable for x16 configuration only.
28. HSB must remain HIGH during READ and WRITE cycles.
29. If WE is low when CE goes low, the outputs remain in the high impedance state.
30. CE or WE must be > VIH during address transitions.
Document #: 001-53953 Rev. *H
Page 13 of 22
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CY14V101LA
CY14V101NA
AutoStore/Power-up RECALL
Over the Operating Range
Parameter
tHRECALL [31]
CY14V101LA/CY14V101NA
Min
Max
–
20
Description
Power-up RECALL duration
Unit
ms
[32]
STORE cycle duration
–
8
ms
[33]
tDELAY
VSWITCH
VIODIS[34]
Time allowed to complete SRAM write cycle
–
25
ns
–
–
150
2.90
1.50
–
V
V
µs
VHDIS[35]
HSB output disable voltage on VCC
–
1.9
V
HSB to output active time
–
5
µs
HSB high active time
–
500
ns
tSTORE
tVCCRISE[35]
tLZHSB[35]
tHHHD[35]
Low voltage trigger level for VCC
I/O disable voltage on VCCQ
VCC rise time
Switching Waveforms
Figure 9. AutoStore or Power-up RECALL[36]
VCC
VSWITCH
VHDIS
VCCQ
VIODIS
32
t VCCRISE
Note
tHHHD
HSB OUT
VCCQ
32
tSTORE
Note
t HHHD
tSTORE
Note
37
37
Note
tDELAY
tLZHSB
AutoStore
t LZHSB
tDELAY
POWERUP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
VCC
BROWN
OUT
AutoStore
Read POWER
POWER-UP Read
&
DOWN
&
RECALL
Write V
Write AutoStore
CCQ
BROWN
OUT
I/O Disable
Notes
31. tHRECALL starts from the time VCC rises above VSWITCH.
32. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
33. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
34. HSB is not defined below VIODIS voltage.
35. These parameters are guaranteed by design and are not tested.
36. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
37. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document #: 001-53953 Rev. *H
Page 14 of 22
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CY14V101LA
CY14V101NA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
Parameters[38, 39]
25 ns
Description
tRC
tSA
tCW
tHA
tRECALL
Min
25
0
20
0
–
STORE/RECALL initiation cycle time
Address setup time
Clock pulse width
Address hold time
RECALL duration
45 ns
Max
–
–
–
–
200
Min
45
0
30
0
–
Unit
Max
–
–
–
–
200
ns
ns
ns
ns
µs
Switching Waveforms
Figure 10. CE and OE Controlled Software STORE/RECALL Cycle [39]
Address
tRC
tRC
Address #1
Address #6
tSA
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tSS
tHZCE
tLZCE
40
Note
t DELAY
DQ (DATA)
Figure 11. AutoStore Enable / Disable Cycle
tRC
Address
tRC
Address #1
tSA
CE
Address #6
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tLZCE
DQ (DATA)
tHZCE
t DELAY
40
Note
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Notes
38. The software sequence is clocked with CE controlled or OE controlled reads.
39. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
40. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document #: 001-53953 Rev. *H
Page 15 of 22
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CY14V101LA
CY14V101NA
Hardware STORE Cycle
Over the Operating Range
Parameters
CY14V101LA/CY14V101NA
Description
Min
Max
25
Unit
tDHSB
HSB to output active time when write latch not set
–
ns
tPHSB
Hardware STORE pulse width
15
–
ns
tSS [41, 42]
Soft sequence processing time
–
100
s
Switching Waveforms
Figure 12. Hardware STORE Cycle [43]
Write Latch set
~
~
tPHSB
HSB (IN)
tSTORE
tHHHD
~
~
~
~
tDELAY
HSB (OUT)
SO
tLZHSB
RWI
Write Latch not set
~
~
tPHSB
HSB (IN)
tDELAY
tDHSB
tDHSB
~
~
HSB (OUT)
HSB pin is driven high to VCCQ only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
RWI
Figure 13. Soft Sequence Processing [41, 42]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Notes
41. This is the amount of time it takes to take action on a soft sequence command. VCC and VCCQ power must remain HIGH to effectively register command.
42. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
43. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
Document #: 001-53953 Rev. *H
Page 16 of 22
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CY14V101LA
CY14V101NA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 2. Truth Table for × 8 Configuration
Inputs/Outputs[44]
CE
WE
OE
Mode
Power
H
X
X
High Z
Deselect / Power-down
Standby
L
H
L
Data out (DQ0–DQ7)
Read
Active
L
H
H
High Z
Output disabled
Active
L
L
X
Data in (DQ0–DQ7)
Write
Active
Table 3. Truth Table for × 16 Configuration
CE
WE
OE
BHE[45]
BLE[45]
Inputs/Outputs[44]
H
X
X
X
X
High Z
Deselect / Power-down
Standby
L
X
X
H
H
High Z
Output disabled
Active
L
H
L
L
L
Data out (DQ0–DQ15)
Read
Active
L
H
L
H
L
Data out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read
Active
L
H
L
L
H
Data out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read
Active
L
H
H
L
L
High Z
Output disabled
Active
L
H
H
H
L
High Z
Output disabled
Active
L
H
H
L
H
High Z
Output disabled
Active
L
L
X
L
L
Data in (DQ0–DQ15)
Write
Active
L
L
X
H
L
Data in (DQ0–DQ7);
DQ8–DQ15 in High Z
Write
Active
L
L
X
L
H
Data in (DQ8–DQ15);
DQ0–DQ7 in High Z
Write
Active
Mode
Power
Notes
44. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
45. BHE and BLE are applicable for × 16 configuration only.
Document #: 001-53953 Rev. *H
Page 17 of 22
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CY14V101LA
CY14V101NA
Ordering Information
Speed
(ns)
25
Ordering Code
CY14V101LA-BA25XIT
Package
Diagram
Package Type
Operating Range
51-85128 48-ball FBGA
Industrial
CY14V101LA-BA25XI
CY14V101NA-BA25XIT
CY14V101NA-BA25XI
45
CY14V101LA-BA45XIT
CY14V101LA-BA45XI
CY14V101NA-BA45XIT
CY14V101NA-BA45XI
All parts are Pb-free. The above table contains final information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 V 101 L A - BA 25 X I T
Option:
T - Tape and Reel
Blank - Std.
Pb-free
Die revision:
Blank - No Rev
A - 1st Rev
Temperature:
I - Industrial (–40 to 85 °C)
Package:
BA - 48-ball FBGA
Data Bus:
L - ×8
N - ×16
Voltage:
V - 3.3 V VCC, 1.8 V VCCQ
Speed:
25 - 25 ns
45 - 45 ns
Density:
101 - 1 Mb
14 - nvSRAM
Cypress
Document #: 001-53953 Rev. *H
Page 18 of 22
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CY14V101LA
CY14V101NA
Package Diagrams
Figure 14. 48-ball FBGA (6 × 10 × 1.2 mm) BA48B, 51-85128
51-85128 *F
Document #: 001-53953 Rev. *H
Page 19 of 22
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CY14V101LA
CY14V101NA
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
degree Celsius
CE
CMOS
chip enable
k
kilo ohms
complementary metal oxide semiconductor
A
micro Amperes
EIA
electronic industries alliance
mA
milli Amperes
FBGA
fine-pitch ball grid array
mm
milli meter
HSB
I/O
hardware STORE busy
F
micro Farad
input/output
MHz
Mega Hertz
nvSRAM
non-volatile static random access memory
s
micro seconds
OE
SRAM
output enable
ms
milli seconds
static random access memory
ns
nano seconds
RoHS
restriction of hazardous substances

ohms
RWI
Read and write inhibited
%
percent
WE
write enable
pF
pico Farad
V
Volts
W
Watts
Document #: 001-53953 Rev. *H
Symbol
Unit of Measure
Page 20 of 22
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CY14V101LA
CY14V101NA
Document History Page
Document Title: CY14V101LA/CY14V101NA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM
Document Number: 001-53953
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
**
2729117
GVCH/
07/02/09
New Datasheet
AESA
*A
2765890
GVCH
09/18/09
Removed commercial temperature related specs
Changed part number from CY14A101L/CY14A101N to
CY14V101LA/CY14V101NA
Removed 20 ns Access speed specs
Figure 3: Updated Autostore Mode
Page 4; Updated Hardware STORE (HSB) Operation description
Page 5; Updated Software STORE Operation description
Added ICCQ1 and ICCQ3 for VCCQ operation
Updated VIH/VIL as 70%/30% of VCCQ
Updated VOH test condition
Updated footnote 24 and added footnote 25, 30
Updated VIODIS parameter value from 1.6 V to 1.5 V
Updated Footnote 10
Added Contents on page 2
*B
2767333
GVCH/
01/06/10
Removed 44-TSOP II package related specs
PYRS
Changed Latch Up Current from 200 mA to 140 mA
Changed STORE cycles to QuantumTrap from 200 K to 1 Million
Added Contents
*C
2923525
GVCH
04/27/10
Pin Definitions: Added more clarity on HSB pin operation
Hardware STORE Operation: Added more clarity on HSB pin operation
Table 1: Added more clarity on status of BHE/BLE pin operation
Updated HSB pin operation in Figure 9
Updated footnote 24
*D
2999981
GVCH
08/04/2010 Changed datasheet status from “Preliminary” to “Final”
*E
3033088
GVCH
09/22/2010 Changed ISB and ICC4 value from 5 mA to 8 mA
Added Acronyms and Units of Measure table
Updated as per new template
*F
3123639
GVCH
12/30/2010 Removed Note “Address expansion for 16 Mbit. NC pin not connected to die.”
in page 3 as 16 Mb address expansion is not supported in 48-ball FBGA
package.
Added CY14V101LA-BA25XI and CY14V101NA-BA25XI parts in Ordering
Information.
*G
3150308
GVCH
01/21/2011 Updated input capacitance for BHE and BLE pin
Updated input and output capacitance for HSB pin
Updated Ordering Information
*H
3301833
GVCH
07/04/2011 Updated DC Electrical Characteristics (Added Note 13 and referred the same
note in VCAP parameter).
Updated AC Switching Characteristics (Added Note 15 and referred the same
note in Parameters).
Updated Thermal Resistance (Values of JA and JC for 48-ball FBGA
package).
Updated Package Diagrams.
Document #: 001-53953 Rev. *H
Page 21 of 22
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CY14V101LA
CY14V101NA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
PSoC Solutions
cypress.com/go/automotive
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Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/interface
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cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
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cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-53953 Rev. *H
Revised July 4, 2011
Page 22 of 22
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