Allegro A3974SEDTR-T Dmos dual full-bridge pwm motor driver Datasheet

ENABLE1
NC
OUT1B
41
40
GND
44
42
GND
1
LOAD
43 SUPPLY1
SENSE1
GND
2
4
3
NC
NC
5
OUT1A
6
DMOS DUAL FULL-BRIDGE PWM MOTOR DRIVER
STROBE
8
CLOCK
9
DATA 10
PROGRAM
PWM TIMER
CHARGE PUMP
7
SERIAL PORT
VBB1
NC
LOGIC
39
NC
38
CP2
37
CP1
36
CP
GND 11
35
GND
GND 12
34
GND
GND 13
33
GND
REF1 14
÷
32
OSC
REF2 15
÷
31
SLEEP
30
VREG
29
NC
LOGIC
16
SUPPLY
PROGRAM
PWM TIMER
LOGIC
VDD
NC 17
OUT2B 28
NC 27
ENABLE2 26
25
GND 24
LOAD
SUPPLY2
23
GND
21
GND 22
SENSE2
NC 19
NC 20
OUT2A 18
VBB2
Dwg. PP-073
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB ............................ 50 V
Output Current, IOUT .................................. ±1.5 A
Logic Supply Voltage, VDD .......................... 7.0 V
Logic Input Voltage Range, VIN
Continous ................... -0.3 V to VDD + 0.3 V
tW < 30 ns ................... -1.0 V to VDD + 1.0 V
Reference Voltage, VREF ................................. 3 V
Sense Voltage (dc), VS
Continous .............................................. 0.5 V
tW < 1 µs ................................................ 2.5 V
Package Power Dissipation, PD .................. 3.9 W
Operating Temperature Range,
TA ......................................... -20°C to +85°C
Junction Temperature, TJ ......................... +150°C
Storage Temperature Range,
TS ....................................... -55°C to +150°C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set
of conditions, do not exceed the specified current rating
or a junction temperature of 150°C.
Data Sheet
29319.35b
3974
Designed for pulse-width modulated (PWM) current control
of two dc motors, the A3974SED is capable of output currents to
±1.5 A and operating voltages to 50 V. Internal fixed off-time
PWM current-control timing circuitry can be programmed via a
serial interface to operate in slow, fast, and mixed current-decay
modes.
Independant ENABLE input terminals are provided for use in
controlling the speed and torque of each dc motor with externally
applied PWM control signals.
Synchronous rectification circuitry allows the load current to
flow through the low rDS(on) of the DMOS output driver during
the current decay. This feature will eliminate the need for
external clamp diodes in most applications, saving cost and
external component count, while minimizing power dissipation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of VDD and the charge
pump, and crossover-current protection. Special power-up
sequencing is not required.
The A3974SED is supplied in a 44-lead plastic PLCC with
four copper batwing tabs for maximum heat dissipation. The
power tabs are at ground potential and need no electrical isolation.
FEATURES
■ ±1.5 A, 50 V Continuous Output Rating
■ Low rDS(on) DMOS Output Drivers
■ Programmable Slow, Fast, and Mixed Current-Decay Modes
■ Serial-Interface Controls Chip Functions
■ Synchronous Rectification for Low Power Dissipation
■ Internal UVLO and Thermal Shutdown Circuitry
■ Crossover-Current Protection
■ Sleep and Idle Modes
Selection Guide
Part Number
Pb-free*
Package
Packing
A3974SED-T
Yes
44-pin PLCC
27 per tube
A3974SEDTR-T
Yes
44-pin PLCC
450 per reel
*Pb-based variants are being phased out of the product line. The variants cited in
this footnote are in production but have been determined to be LAST TIME BUY.
This classification indicates that sale of this device is currently restricted
to existing customer applications. The variants should not be purchased for new
design applications because obsolescence in the near future is probable. Samples
are no longer available. Status change: October 31, 2006. Deadline for LAST TIME
BUY orders: April 27, 2007. These
.
variants include: A3974SED and A3974SEDTR.
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
VBB1
VDD
UNDERVOLTAGE &
FAULT DETECT
CP
CP1
CHARGE PUMP
BANDGAP
VDD
CREG
TSD
CP2
+
LOGIC
SUPPLY
LOAD
SUPPLY1
CHARGE
PUMP
BANDGAP
REGULATOR
VREG
ENABLE1
OUT1A
GATE DRIVE
PHASE
SYNC RECT MODE
SYNC RECT DISABLE
MODE
CONTROL LOGIC
OUT1B
SENSE1
CS1
ZERO CURRENT DETECT
FIXED OFF
PROGRAMMABLE BLANK
DECAY
RS1
PWM TIMER
CURRENT SENSE
OSC
CLOCK
DATA
STROBE
PHASE
ENABLE
SYNC RECT MODE
SYNC RECT DISABLE
PWM MODE INT
PWM MODE EXT
ENABLE2
REF1
VREF
LOAD
SUPPLY2
CHARGE
PUMP
+
VBB2
OUT2A
GATE DRIVE
FIXED OFF
BLANK
DECAY
PROGRAMMABLE
PWM TIMER
SLEEP
MODE
REFERENCE
BUFFER &
DIVIDER
SERIAL
PORT
OUT2B
CONTROL LOGIC
SENSE2
TO PWM TIMER
CS2
ZERO CURRENT DETECT
RS2
CURRENT SENSE
REFERENCE
BUFFER &
DIVIDER
REF2
VREF2
Dwg. FP-048-1
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2001 Allegro MicroSystems, Inc.
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50 kHz (unless
otherwise noted).
Characteristic
Symbol
Test Conditions
Min.
Limits
Typ. Max.
Units
Output Drivers
Load Supply Voltage Range
Output Leakage Current
Output ON Resistance
Body Diode Forward Voltage
Load Supply Current
VBB
IDSS
rDS(on)
VF
IBB
Operating
15
—
50
V
During sleep mode
0
—
50
V
VOUT = VBB
—
<1.0
20
µA
VOUT = 0 V
—
<-1.0
-20
µA
Source driver, IOUT = -1.5 A
—
0.5
0.55
Ω
Sink driver, IOUT = 1.5 A
—
0.315
0.35
Ω
Source diode, IF = 1.5 A
—
—
1.2
V
Sink diode, IF = 1.5 A
—
—
1.2
V
fPWM < 50 kHz
—
4.0
7.0
mA
Charge pump on, outputs disabled
—
2.0
5.0
mA
Sleep or idle mode
—
—
20
µA
Operating
4.5
5.0
5.5
V
Control Logic
Logic Supply Voltage Range
VDD
Logic Input Voltage
VIN(1)
2.0
—
—
V
VIN(0)
—
—
0.8
V
Logic Input Current
(except ENABLE)
IIN(1)
VIN = 2.0 V
—
<1.0
±20
µA
IIN(0)
VIN = 0.8 V
—
<1.0
±20
µA
ENABLE Input Current
IEN(1)
VEN = 2.0 V
—
40
100
µA
IEN(0)
VEN = 0.8 V
—
16
30
µA
OSC Input Frequency
fOSC
2.9
—
6.1
MHz
OSC Input Duty Cycle
—
40
—
60
%
OSC Input Hysterisis
∆VIN
200
—
400
mV
Reference Input Voltage Range
VREF
0
—
2.6
V
Operating
continued next page ...
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3
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50 kHz (unless
otherwise noted), continued.
Characteristic
Control Logic (continued)
Symbol
Reference Input Current
IREF
Reference Input Offset Voltage
VIO
Reference Divider Ratio
Gain (Gm) Error (note 3)
Propagation Delay Time
Crossover Delay Time
VREF/VS
EG
tpd
tCOD
Test Conditions
Min.
Units
—
—
±1.0
µA
—
±10
—
mV
D16 = 1
—
10
—
—
D16 = 0
—
5.0
—
—
VREF = 2.6 V, D16 = 0
—
0
±4.0
%
VREF = 0.5 V, D16 = 0
—
0
±14
%
VREF = 2.6 V, D16 = 1
—
0
±4.0
%
VREF = 0.5 V, D16 = 1
—
0
±10
%
50% TO 90%:
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
600
50
600
50
750
150
750
150
1000
350
1000
350
ns
ns
ns
ns
SR enabled
300
600
1000
ns
VREF = 2.6 V
Thermal Shutdown Temperature
TJ
—
165
—
°C
Thermal Shutdown Hysteresis
∆TJ
—
15
—
°C
3.9
4.2
4.45
V
0.05
0.10
—
V
fPWM < 50 kHz
—
—
10
mA
Outputs off
—
—
8.0
mA
Idle mode (D18 = 1, D19 = 0)
—
—
1.5
mA
Sleep mode (inputs below 0.5 V)
—
—
100
µA
UVLO Enable Threshold
VUVLO
UVLO Hysteresis
∆VUVLO
Logic Supply Current
IDD
Increasing VDD
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3. EG = [(VREF/Range) - VS]/(VREF/Range).
4
Limits
Typ. Max.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
Serial Interface. The A3974SED is controlled via a 3-wire
(clock, data,strobe) serial port. The programmable functions
allow maximum flexibility in configuring the PWM to the
motor drive requirements. The serial data is written as two 20bit words: 1 bit to select the word and 19 bits of data. The data
is clocked in starting with D19.
D2 – D6 Fixed Off Time. This five-bit word sets the fixed
off-time for the internal PWM control circuitry. The off-time is
defined by
Word 0 Bit Assignments
For example, with an oscillator frequency of 4 MHz, the
fixed off-time will be adjustable from 1.75 µs to 63.75 µs in
increments of 2 µs.
Select Word 0 (D18 = 0)
Bit
Function
D0
Bridge 1 blank time LSB
D1
Bridge 1 blank time MSB
D2
Bridge 1 off-time LSB
D3
Bridge 1 off-time bit 1
D4
Bridge 1 off-time bit 2
D5
Bridge 1 off-time bit 3
D6
Bridge 1 off-time MSB
D7
Bridge 1 fast-decay time bit LSB
D8
Bridge 1 fast-decay time bit 1
D9
Bridge 1 fast-decay time bit 2
D10
Bridge 1 fast-decay time MSB
D11
Bridge 1 sync. rect. control
D12
Bridge 1 sync. rect. control
D13
Bridge 1 external PWM mode
D14
Bridge 1 enable
D15
Bridge 1 phase
D16
Bridge 1 reference range select
D17
Bridge 1 internal PWM mode
D18
Word select = 0
D19
Test mode
D0 – D1 Blank Time. The current-sense comparator is
blanked when any output driver is switched on, according to the
table below. fosc is the oscillator input frequency.
D1
0
0
1
1
D0
0
1
0
1
Blank Time
4/fOSC
6/fOSC
12/fOSC
24/fOSC
toff =(8 [1 + N]/fOSC) - 1/fOSC
where N = 0 .... 31
D7 – D10 Fast Decay Time. This four-bit word sets the fastdecay portion of the fixed off-time for the internal PWM control
circuitry. This will only have impact if mixed-decay mode is
selected (via bit D17). For tfd > toff, the device will effectively
operate in fast-decay mode. The fast-decay portion is defined
by
tfd = (8[1 + N]/fOSC] - 1/fOSC
where N = 0 .... 15
For example, with an oscillator frequency of 4 MHz, the fastdecay time will be adjustable from 1.75 µs to 31.75 µs in
increments of 2 µs.
D11 – D12 Synchronous Rectification.
D12
0
0
1
1
D11
0
1
0
1
Synchronous Rectifier
Disabled
Low side only
Active
Passive
The different modes of operation are described in the synchronous rectification section of the functional description.
D13 External PWM Decay Mode. This bit determines the
current-decay mode when using ENABLE chopping for
external PWM current control.
D13
0
1
Mode
Fast
Slow
continued next page ...
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5
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
D14 Enable Logic. This bit, in conjuction with ENABLE,
determines if the output drivers are in the chopped or on state.
ENABLE1
0
1
0
1
D14
0
0
1
1
Mode
Chopped
On
On
Chopped
D15 Phase Logic. This bit determines if the device is
operating in the forward or reverse state.
D15
State
OUTA
OUTB
0
1
Reverse
Forward
L
H
H
L
D16 Gm Range Select. This bit determines if VREF is divided
by 5 or 10.
D16
0
1
Divider
÷10
÷5
D17 Bridge 2 Mode. This bit determines slow or mixed
decay for internal current-control operation.
D17
0
1
Decay Mode
Mixed
Slow
D19 Test Mode. This bit is reserved for testing and should
never be changed by the user. Default (low) operates the
device in normal mode.
Word 1 Bit Assignments
Select Word 1 (D18 = 1)
Bit
Function
D0
Bridge 2 blank time LSB
D1
Bridge 2 blank time MSB
D2
Bridge 2 off-time LSB
D3
Bridge 2 off-time bit 1
D4
Bridge 2 off-time bit 2
D5
Bridge 2 off-time bit 3
D6
Bridge 2 off-time MSB
D7
Bridge 2 fast-decay time bit LSB
D8
Bridge 2 fast-decay time bit 1
D9
Bridge 2 fast-decay time bit 2
D10
Bridge 2 fast-decay time bit MSB
D11
Bridge 2 sync. rect. control
D12
Bridge 2 sync. rect. control
D13
Bridge 2 external PWM mode
D14
Bridge 2 enable
D15
Bridge 2 phase
D16
Bridge 2 reference range select
D17
Bridge 2 internal PWM mode
D18
Word select = 1
D19
Idle mode
D0 - D17. Identical definitions as Word 0, with Word 1
selected. Data is written to Full Bridge 2.
D19 Idle Mode. The device can be placed in a low-power
“idle” mode by writing a “0” to D19. The outputs will be
disabled, the charge pump will be turned off, and the device
will draw a lower load supply currrent. The undervoltage
monitor circuit will remain active. D19 should be programmed
high for 1 ms before attempting to enable any output driver.
continued next page ...
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
VREG. This internally generated supply voltage is used to
operate the sink-side DMOS outputs. VREG is internally
monitored and in the case of a fault condition, the outputs of the
device are disabled. The VREG terminal should be decoupled
with a 0.22 µF capacitor to ground.
Charge Pump. The charge pump is used to generate a supply
voltage greater than VBB to drive the source-side DMOS gates.
A 0.22 µF ceramic capacitor should be connected between CP1
and CP2 for pumping purposes. A 0.22 µF ceramic capacitor
should be connected between VCP and VBB to act as a reservoir
to run the high-side DMOS devices. The CP voltage is internally monitored and in the case of a fault condition, the outputs
of the device are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on CP or VREG, the outputs of the
device are disabled until the fault condition is removed. At
power up, or in the event of low VDD, the UVLO circuit
disables the drivers and resets the data in the serial port to all
zeros.
Current Regulation. Load current is regulated by an internal
fixed off-time PWM control circuit. When the outputs of the
DMOS H-bridge are turned on, the current increases in the
motor winding until it reaches a trip value determined by the
external sense resistor (RS), the applied analog reference
voltage (VREF), and serial data bit D16:
When D16 = 0 ....................... ITRIP = VREF/10RS
When D16 = 1 ....................... ITRIP = VREF/5RS
At the trip point, the sense comparator resets the source-enable
latch, turning off the source driver (except in the case of lowside only mode where the sink driver is turned off). The load
inductance then causes the current to recirculate for the serialport programmed fixed off-time period. The current path
during recirculation is determined by the configuration of slow/
mixed-decay mode (D17) and the synchronous rectification
control bits (D11 and D12).
www.allegromicro.com
Sleep Mode. The input terminal SLEEP is dedicated to
putting the device into a minimum current draw mode. When
asserted low, the serial port will be reset to all zeros and all
circuits will be disabled.
PWM Timer Function. The PWM timer is programmable via
the serial port (bits D2 – D10) to provide fixed off-time PWM
signals to the control circuitry. In mixed current-decay mode,
the first portion of the off time operates in fast decay, until the
fast-decay time count is reached (serial bits D7 – D10), followed by slow decay for the rest of the off-time period (bits D2
– D6). If the fast-decay time is set longer than the off-time, the
device effectively operates in fast-decay mode. Bit D17 selects
mixed or slow decay.
Synchronous Rectification. When a PWM off cycle is
triggered, either by an ENABLE chop command or internal
fixed off-time cycle, load current will recirculate according to
the decay mode selected by the control logic. After a short
crossover delay, the A3974 synchronous rectification feature
will turn on the appropriate MOSFET (or pair of MOSFETs for
the mixed decay portion of the off-time) during the current
decay and effectively short out the body diodes with the low
rDS(on) driver. This will lower power dissipation significantly
and can eliminate the need for external Schottky diodes.
Synchronous rectification can be configured in active mode,
passive mode, low side only, or disabled via the serial port (bits
D11 and D12). The active mode prevents reversal of load
current by turning off synchronous rectification when a zero
current level is detected. Passive mode will allow reversal of
current but will turn off the synchronous rectifier circuit if the
load current inversion ramps up to the current limit set by
VREF/10RS (when D16 = 0) or VREF/5RS(when D16 = 1).
Low side only mode will switch the low-side MOSFETs on
during the off time to short out the current path through the
MOSFET body diode. With this setting, the high-side
MOSFETs will not synchronously rectify so four external
diodes from output to supply are recommended. This mode is
intended for use with high-power applications where it is
desired to save the expense of two external diodes per bridge.
In this mode, the sink-side MOSFETs are chopped during the
PWM off time. In all other cases, the source-side MOSFETs
are chopped in response to a PWM OFF command.
7
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
APPLICATIONS INFORMATION
Current Sensing. To minimize inaccuracies in sensing the
ITRIP current level caused by ground-trace IR drops, the sense
resistor should have an independent ground return to a ground
terminal of the device. For low-value sense resistors, the IR
drops in the PCB sense traces of the resistor can be significant
and should be taken into account. The use of sockets should be
avoided as they can introduce variation in RS due to their
contact resistance.
The maximum value of RS is given as RS = 0.5/ITRIPMAX.
Braking. The braking function is implemented by driving the
device in slow-decay mode via serial port bit D13, enabling
synchronous rectification via bits D11 and D12, and applying
an enable chop command with the combination of D14 and the
ENABLE input terminal. Because it is possible to drive current
in both directions through the DMOS switches, this configuration effectively shorts out the motor-generated BEMF as long as
the ENABLE chop mode is asserted. It is important to note that
the internal PWM current-control circuit will not limit the
current when braking, because the current does not flow
through the sense resistor. The maximum brake current can be
approximated by VBEMF/RL. Care should be taken to ensure that
the maximum ratings of the device are not exceeded in worstcase braking situations of high speed and high inertial loads.
Thermal protection. Circuitry turns off all drivers when the
junction temperature reaches 165°C typically. It is intended
only to protect the device from failures due to excessive
junction temperatures and should not imply that output short
circuits are permitted. Thermal shutdown has a hysteresis of
approximately 15°C.
Layout. The printed wiring board should use a heavy ground
plane. For optimum electrical and thermal performance, the
driver should be soldered directly onto the board. The ground
side of RS should have an individual path to a ground terminal
of the device. This path should be as short as is possible
physically and should not have any other components connected to it. The load supply terminal, VBB, should be
decoupled with an electrolytic capacitor (>47 µF is recommended) placed as close to the device as is possible.
Serial Port Write Timing Operation. Data is clocked into
shift register on the rising edge of CLOCK signal. Normally,
STROBE will be held high, and only will be brought low to
initiate a write cycle. Refer to diagram below and specification
table for timing requirements.
STROBE
C
D
E
F
G
CLOCK
A
DATA
B
D19
D18
D0
Dwg. WP-038
A. Minimum Data Setup Time ........................................... 15 ns
B. Minimum Data Hold Time ............................................ 10 ns
C. Minimum Setup Strobe to Clock Rising Edge .......... 50 ns
D. Minimum Clock High Pulse Width ........................... 50 ns
E. Minimum Clock Low Pulse Width ............................ 50 ns
F. Minimum Setup Clock Rising Edge to Strobe ........... 50 ns
G. Minimum Strobe Pulse Width ................................... 50 ns
8
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
Terminal List
Terminal Name
GND
SENSE1
NC
OUT1A
NC
STROBE
CLOCK
DATA
GND
REF1
REF2
LOGIC SUPPLY
NC
OUT2A
NC
SENSE2
GND
LOAD SUPPLY2
ENABLE2
NC
OUT2B
NC
VREG
SLEEP
OSC
GND
CP
CP1 & CP2
NC
OUT1B
NC
ENABLE1
LOAD SUPPLY1
GND
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Terminal Description
Power and logic ground terminals
Sense resistor terminal for bridge 1
No (internal) connection
DMOS H-bridge 1 – output A
No (internal) connection
Logic input for serial Interface
Logic input for serial Interface
Logic input for serial Interface
Power and logic ground terminals
Gm reference input voltage – bridge 1
Gm reference input voltage – bridge 2
VDD, the low voltage (typically 5 V) supply
No (internal) connection
DMOS H-bridge 2 – output A
No (internal) connection
Sense resistor pin for bridge 2
Power and logic ground terminals
VBB2, the high current, 20 V to 50 V,
supply for bridge 2
Logic input for bridge 2 – enable control
No (internal) connection
DMOS H-bridge 2 – output B
No (internal) connection
Regulator decoupling capacitor (typ. 0.22 µF)
Logic input for SLEEP mode
Logic-level oscillator (square wave) input
Power and logic ground terminals
Reservoir capacitor (typically 0.22 µF)
The charge pump capacitor (typically 0.22 µF)
No (internal) connection
DMOS H-bridge 1 – output B
No (internal) connection
Logic input for bridge 1 – enable control
VBB1, the high current, 20 V to 50 V,
supply for bridge 1
Power and logic ground terminals
Terminal Number
1, 2
3
4, 5
6
7
8
9
10
11, 12, 13
14
15
16
17
18
19, 20
21
22, 23, 24
25
26
27
28
29
30
31
32
33, 34, 35
36
37 & 38
39
40
41
42
43
44
9
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
Dimensions in Inches
(controlling dimensions)
18
28
29
17
0.032
0.026
0.319
0.291
0.695
0.685
0.021
0.013
0.656
0.650
0.319
0.291
0.050
INDEX AREA
BSC
7
39
40
0.020
44
1
2
6
0.656
0.650
MIN
0.695
0.685
0.180
0.165
Dwg. MA-005-44A in
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown.
3. Available in standard sticks/tubes of 28 devices or add “TR” to part number for tape and reel.
10
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
Dimensions in Millimeters
(for reference only)
28
18
29
17
0.812
0.661
8.10
7.39
17.65
17.40
0.533
0.331
16.662
16.510
8.10
7.39
INDEX AREA
1.27
BSC
39
7
40
0.51
MIN
4.57
4.20
44
1
2
6
16.662
16.510
17.65
17.40
Dwg. MA-005-44A mm
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown.
3. Available in standard sticks/tubes of 28 devices or add “TR” to part number for tape and reel.
www.allegromicro.com
11
3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
12
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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