Cypress CY62157CV33LL-70BAI 512k x 16 static ram Datasheet

CY62157CV25/30/33
MoBL™
512K x 16 Static RAM
Features
reducing power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW or both BLE and BHE are
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE1 HIGH or
CE2 LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
• High speed
— 55 ns and 70 ns availability
• Voltage range:
— CY62157CV25: 2.2V–2.7V
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = fmax (70 ns speed)
Low standby power
Easy memory expansion with CE1, CE2 and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Functional Description
The CY62157CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™)
in portable applications such as cellular telephones. The devices also have an automatic power-down feature that significantly reduces power consumption by 80% when addresses
are not toggling. The device can also be put into standby mode
Logic Block Diagram
The CY62157CV25/30/33 are available in a 48-ball FBGA
package.
DATA IN DRIVERS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable
2 (CE2) HIGH while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back
of this data sheet for a complete description of read and write
modes.
512K × 16
RAM Array
2048 × 4096
SENSE AMPS
•
•
•
•
Writing to the device is accomplished by taking Chip Enable 1
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable
(BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is
written into the location specified on the address pins (A0
through A18).
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
A11
A12
A13
A14
A15
A16
A17
A18
BHE
WE
CE2
CE1
OE
BLE
Power-down
Circuit
Cypress Semiconductor Corporation
Document #: 38-05014 Rev. *C
•
3901 North First Street
CE2
BHE
BLE
•
San Jose
CE1
•
CA 95134 • 408-943-2600
Revised April 23, 2002
CY62157CV25/30/33
MoBL™
Pin Configurations[1, 2]
FBGA (Top View)
1
2
3
4
5
6
BLE
OE
A0
A1
A2
CE2
A
I/O8
BHE
A3
A4
CE1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
DNU
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Maximum Ratings
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Device
Supply Voltage to Ground Potential ...–0.5V to Vccmax + 0.5V
CY62157CV25
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.3V
CY62157CV30
2.7V to 3.3V
CY62157CV33
3.0V to 3.6V
DC Input Voltage[3].................................–0.5V to VCC + 0.3V
Range
Ambient
Temperature
Industrial –40°C to +85°C
VCC
2.2V to 2.7V
Output Current into Outputs (LOW) .............................20 mA
Product Portfolio
Power Dissipation (Industrial)
Operating (ICC)
VCC Range
Product
VCC(min.)
CY62157CV25
2.2V
2.5V
2.7V
CY62157CV30
2.7V
3.0V
3.3V
CY62157CV33
VCC(typ.)
[4]
Speed
3.0V
3.3V
f = fmax
[4]
Max.
Typ.
55 ns
1.5 mA
3 mA
7 mA
70 ns
1.5 mA
3 mA
55 ns
1.5 mA
3 mA
70 ns
1.5 mA
3 mA
55 ns
1.5 mA
3 mA
70 ns
1.5 mA
3 mA
VCC(max.)
3.6V
f = 1 MHz
Typ.
[4]
Max.
15 mA
Standby (ISB2)
Typ.
[4]
Max.
6 µA
25 µA
8 µA
25 µA
10 µA
30 µA
5.5 mA 12 mA
7 mA
15 mA
5.5 mA 12 mA
7 mA
15 mA
5.5 mA 12 mA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or VSS to ensure proper application.
3. VIL(min.) = –2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05014 Rev. *C
Page 2 of 13
CY62157CV25/30/33
MoBL™
Electrical Characteristics Over the Operating Range
CY62157CV25-55
Parameter
Description
Test Conditions
Min. Typ.[4]
CY62157CV25-70
Max. Min. Typ.[4]
VOH
Output HIGH Voltage
IOH = –0.1 mA
VCC = 2.2V
2.0
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = 2.2V
VIH
Input HIGH Voltage
1.8
VCC +
0.3V
VIL
Input LOW Voltage
–0.3
IIX
Input Leakage Current
IOZ
Output Leakage Current GND < VO < VCC,
Output Disabled
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down Current—
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE,BHE and BLE)
ISB2
Automatic CE
Power-Down Current—
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 2.7V
f = 1 MHz
2.0
0.4
V
1.8
VCC +
0.3V
V
0.6
–0.3
0.6
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
mA
VCC = 2.7V
IOUT = 0 mA
CMOS Levels
7
15
5.5
12
1.5
3
1.5
3
6
25
6
25
CY62157CV30-55
Parameter
Description
V
0.4
GND < VI < VCC
Test Conditions
Max. Unit
Min. Typ.
[4]
µA
CY62157CV30-70
Max. Min. Typ.[4] Max. Unit
VOH
Output HIGH Voltage
IOH = –1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
+1
–1
+1
µA
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC
mA
ISB1
Automatic CE
Power-Down Current—
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE,BHE and BLE)
ISB2
Automatic CE
Power-Down Current—
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.3V
Document #: 38-05014 Rev. *C
f = 1 MHz
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
2.4
2.4
2.2
VCC + 2.2
0.3V
V
0.4
0.4
V
VCC +
0.3V
V
7
15
5.5
12
1.5
3
1.5
3
8
25
8
25
µA
Page 3 of 13
CY62157CV25/30/33
MoBL™
CY62157CV33-55
Parameter
Description
Test Conditions
Min.
Typ.
[4]
Max.
CY62157CV33-70
Min.
Max.
Output HIGH Voltage IOH = –1.0 mA
VCC = 3.0V
VOL
Output LOW Voltage IOL = 2.1 mA
VCC = 3.0V
0.4
V
VIH
Input HIGH Voltage
2.2
VCC +
0.3V
2.2
VCC +
0.3V
V
VIL
Input LOW Voltage
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage
Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
–1
+1
µA
ICC
VCC Operating Supply f = fMAX = 1/tRC VCC = 3.6V
Current
IOUT = 0 mA
f = 1 MHz
CMOS Levels
mA
Automatic CE
Power-Down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE,BHE,and BLE)
ISB2
Automatic CE
Power-Down Current—CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.6V
2.4
Unit
VOH
ISB1
2.4
Typ.[4]
V
0.4
7
15
5.5
12
1.5
3
1.5
3
10
30
10
30
µA
Capacitance[5]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Description
Thermal Resistance
(Junction to Ambient)[5]
Thermal Resistance
(Junction to Case)[5]
Test Conditions
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
Symbol
ΘJA
BGA
55
Unit
°C/W
ΘJC
16
°C/W
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05014 Rev. *C
Page 4 of 13
CY62157CV25/30/33
MoBL™
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC Typ
OUTPUT
10%
GND
Rise TIme: 1 V/ns
R2
30 pF
90%
10%
90%
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5V
3.0V
3.3V
Unit
R1
16.6
1.105
1.216
K Ohms
R2
15.4
1.550
1.374
K Ohms
RTH
8.0
0.645
0.645
K Ohms
VTH
1.20
1.75
1.75
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[5]
Chip Deselect to Data
Retention Time
tR[6]
Operation Recovery Time
Min.
Typ.[4]
1.5
VCC = 1.5V
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
4
Max.
Unit
Vccmax
V
20
µA
0
ns
tRC
ns
Data Retention Waveform[7]
DATA RETENTION MODE
VCC
VCC(min.)
tCDR
VDR > 1.5 V
VCC(min.)
tR
CE1 or
BHE.BLE
or
CE2
Note:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) >100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05014 Rev. *C
Page 5 of 13
CY62157CV25/30/33
MoBL™
Switching Characteristics Over the Operating Range[8]
55 ns
Parameter
Description
Min.
70 ns
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low-Z
tHZOE
55
55
10
[9]
OE HIGH to High-Z
CE1 LOW and CE2 HIGH to Low-Z
tHZCE
CE1 HIGH or CE2 LOW to High-Z[9, 10]
tPU
CE1 LOW and CE2 HIGH to Power-up
tPD
CE1 HIGH or CE2 LOW to Power-down
tDBE
BHE/BLE LOW to Data Valid
tLZBE[11]
BHE/BLE LOW to Low-Z[9]
Write Cycle
BHE/BLE HIGH to High-Z
70
10
10
0
0
55
5
ns
ns
70
ns
70
ns
5
20
ns
ns
25
55
[9, 10]
ns
25
20
ns
ns
5
20
[9]
ns
10
5
[9, 10]
tLZCE
tHZBE
70
ns
25
ns
[12]
tWC
Write Cycle Time
55
70
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
45
60
ns
tAW
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
45
50
ns
tBW
BHE/BLE Pulse Width
50
60
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High-Z[9, 10]
tLZWE
WE HIGH to Low-Z
[9]
0
20
5
ns
25
5
ns
ns
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of
the specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. When both byte enables are toggled together this value is 10 ns.
12. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate
a Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the
signal that terminates the Write.
Document #: 38-05014 Rev. *C
Page 6 of 13
CY62157CV25/30/33
MoBL™
C
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)
[14, 15]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZBE
BHE/BLE
tLZBE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
ICC
50%
ISB
Notes:
13. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05014 Rev. *C
Page 7 of 13
CY62157CV25/30/33
MoBL™
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled) [12, 16, 17]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE18
tHZOE
Write Cycle No. 2 (CE1 or CE2 Controlled)
[12, 16, 17]
tWC
ADDRESS
tSCE
CE1
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE18
tHZOE
Notes:
16. Data I/O is high-impedance if OE = VIH.
17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05014 Rev. *C
Page 8 of 13
CY62157CV25/30/33
MoBL™
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[17]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tHD
tSD
DATAI/O
NOTE 18
DATAIN VALID
tLZWE
tHZWE
[17]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tSD
DATA I/O
NOTE 18
Document #: 38-05014 Rev. *C
tHD
DATAIN VALID
Page 9 of 13
CY62157CV25/30/33
MoBL™
Typical DC and AC Characteristics
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.)
Operating Current vs. Supply Voltage
MoBL
12.0
10.0
8.0
(f = fmax, 55ns)
6.0
(f = fmax, 70ns)
12.0
10.0
8.0
(f = fmax, 55ns)
6.0
(f = fmax, 70ns)
ICC (mA)
MoBL
ICC (mA)
ICC (mA)
12.0
14.0
14.0
14.0
10.0
2.0
4.0
2.0
(f = 1 MHz)
0.0
3.3
3.0
3.6
SUPPLY VOLTAGE (V)
(f = 1 MHz)
0.0
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
0.0
2.2
2.5 2.7
SUPPLY VOLTAGE (V)
(f = fmax, 70ns)
6.0
2.0
(f = 1 MHz)
(f = fmax, 55ns)
8.0
4.0
4.0
MoBL
12.0
12.0
12.0
10.0
10.0
10.0
MoBL
8.0
ISB (µA)
8.0
MoBL
ISB (µA)
ISB (µA)
Standby Current vs. Supply Voltage
MoBL
8.0
6.0
6.0
6.0
4.0
4.0
4.0
2.0
2.0
2.0
0
0
2.2 2.5 2.7
SUPPLY VOLTAGE (V)
0
3.0
2.7
SUPPLY VOLTAGE (V)
3.3
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
MoBL
60
MoBL
50
50
40
40
40
30
30
30
20
20
10
10
0
0
2.2
2.5
2.7
SUPPLY VOLTAGE (V)
Document #: 38-05014 Rev. *C
TAA (ns)
50
TAA (ns)
TAA (ns)
60
20
10
0
2.7
MoBL
3.0
3.3
SUPPLY VOLTAGE (V)
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
Page 10 of 13
CY62157CV25/30/33
MoBL™
Truth Table
CE1
CE2
WE
OE
BHE
BLE
H
X
X
X
X
X
High Z
Deselect/Power-Down
Standby (ISB)
X
L
X
X
X
X
High Z
Deselect/Power-Down
Standby (ISB)
X
X
X
X
H
H
High Z
Deselect/Power-Down
Standby (ISB)
L
H
H
L
L
L
Data Out (I/OO–I/O15) Read
Active (ICC)
L
H
H
L
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
L
H
H
L
L
H
Data Out (I/O8–I/O15); Read
I/O0–I/O7 in High Z
Active (ICC)
L
H
H
H
L
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
H
L
High Z
Output Disabled
Active (ICC)
L
H
H
H
L
H
High Z
Output Disabled
Active (ICC)
L
H
L
X
L
L
Data In (I/OO–I/O15)
Write
Active (ICC)
L
H
L
X
H
L
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
H
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Document #: 38-05014 Rev. *C
Inputs/Outputs
Mode
Power
Page 11 of 13
CY62157CV25/30/33
MoBL™
Ordering Information
Speed (ns)
70
Ordering Code
CY62157CV25LL-70BAI
Package Name
Package Type
Operating Range
BA48F
48-ball Fine-pitch BGA
Industrial
CY62157CV30LL-70BAI
CY62157CV33LL-70BAI
55
CY62157CV30LL-55BAI
CY62157CV33LL-55BAI
Package Diagram
48-Ball (6 mm x 10 mm x 1.2 mm) FBGA BA48F
51-85128-*B
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05014 Rev. *C
Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62157CV25/30/33
MoBL™
Document Title: CY62157CV25/30/33 MoBL™ 512K x 16 STATIC RAM
Document Number: 38-05014
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106184
05/10/01
*A
107241
07/24/01
MGN
Make Corrections to Advance Information.
Added 55 ns bin.
*B
109621
03/11/02
MGN
Change from Advance Information to Final
*C
114218
05/01/02
GUG/
MGN
Improved Typical & Max ICC values
Document #: 38-05014 Rev. *C
HRT/MGN New Datasheet – Advance Information
Page 13 of 13
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