Dallas DS1315N-33 Phantom time chip Datasheet

DS1315
Phantom Time Chip
www.dalsemi.com
www.maxim-ic.com
DESCRIPTION
FEATURES
The DS1315 Phantom Time Chip is a
combination of a CMOS timekeeper and a
nonvolatile memory controller. In the absence of
power, an external battery maintains the
timekeeping operation and provides power for a
CMOS static RAM. The watch keeps track of
hundredths of seconds, seconds, minutes, hours,
day, date, month, and year information. The last
day of the month is automatically adjusted for
months with less than 31 days, including leap
year correction. The watch operates in one of two
formats: a 12-hour mode with an AM/PM
indicator or a 24-hour mode. The nonvolatile
controller supplies all the necessary support
circuitry to convert a CMOS RAM to a
nonvolatile memory. The DS1315 can be
interfaced with either RAM or ROM without
leaving gaps in memory.
Real-Time Clock Keeps Track of Hundredths
of Seconds, Seconds, Minutes, Hours, Days,
Date of the Month, Months, and Years
Adjusts for Months with Fewer than 31 Days
Automatic Leap Year Correction Valid Up to
2100
No Address Space Required to Communicate
with RTC
Provides Nonvolatile Controller Functions for
Battery Backup of SRAM
Supports Redundant Battery Attachment for
High-Reliability Applications
Full ±10% VCC Operating Range
+3.3V or +5V Operation
Industrial (–45°C to +85°C) Operating
Temperature Ranges Available
Drop-In Replacement for DS1215
PIN DESCRIPTION
PIN CONFIGURATIONS
X1, X2
WE
16
VCC1
15
VCC0
BAT1
GND
D
Q
ROM/ RAM
X1
1
X2
2
WE
3
14
BAT2
BAT1
4
13
RST
GND
5
12
OE
CEI
D
6
11
CEI
OE
Q
7
10
CEO
RST
GND
8
9
DS1315
ROM/RAM
DIP (300 mils)
CEO
BAT2
VCC0
VCC1
- 32.768 kHz Crystal Connection
- Write Enable
- Battery 1 Input
- Ground
- Data Input
- Data Output
- ROM/RAM Mode Select
- Chip Enable Output
- Chip Enable Input
- Output Enable
- Reset
- Battery 2 Input
- Switched Supply Output
- Power Supply Input
Pin Configurations continued at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 062807
DS1315 Phantom Time Chip
ORDERING INFORMATION
PART
DS1315-33
TEMP RANGE
0°C to +70°C
VOLTAGE
PIN-PACKAGE
(V)
3.3
16 DIP (300 mils)
TOP MARK*
DS1315 336
DS1315N-33
-40°C to +85°C
3.3
16 DIP (300 mils)
DS1315 336
DS1315N-33+
-40°C to +85°C
3.3
16 DIP (300 mils)
DS1315 336
0°C to +70°C
5
16 DIP (300 mils)
DS1315 56
DS1315N-5
-40°C to +85°C
5
16 DIP (300 mils)
DS1315 56
DS1315N-5+
-40°C to +85°C
5
16 DIP (300 mils)
DS1315 56
DS1315E-33
0°C to +70°C
3.3
20 TSSOP (4.4mm)
DS1315E XXXX-336
DS1315E-33+
0°C to +70°C
3.3
20 TSSOP (4.4mm)
DS1315E XXXX-336 +
DS1315EN-33
-40°C to +85°C
3.3
20 TSSOP (4.4mm)
DS1315E XXXX-336
DS1315EN-33+
-40°C to +85°C
3.3
DS1315E XXXX-336 +
DS1315EN-33/T&R
-40°C to +85°C
3.3
DS1315EN-33+T&R
-40°C to +85°C
3.3
DS1315E-5
0°C to +70°C
5
20 TSSOP (4.4mm)
20 TSSOP/Tape and Reel
(4.4mm)
20 TSSOP/Tape and Reel
(4.4mm)
20 TSSOP (4.4mm)
DS1315E-5+
0°C to +70°C
5
20 TSSOP (4.4mm)
DS1315E XXXX-56 +
DS1315EN-5
-40°C to +85°C
5
20 TSSOP (4.4mm)
DS1315E XXXX-56
DS1315EN-5+
-40°C to +85°C
5
20 TSSOP (4.4mm)
DS1315E XXXX-56 +
DS1315EN-5/T&R
-40°C to +85°C
5
20 TSSOP (4.4mm)
DS1315E XXXX-56
DS1315EN-5+T&R
-40°C to +85°C
5
20 TSSOP (4.4mm)
DS1315E XXXX-56 +
DS1315S-33
0°C to +70°C
3.3
16 SO (300 mils)
DS1315 336
DS1315S-33+
0°C to +70°C
3.3
16 SO (300 mils)
DS1315 336 +
DS1315SN-33
-40°C to +85°C
3.3
16 SO (300 mils)
DS1315 336
DS1315SN-33+
-40°C to +85°C
3.3
16 SO (300 mils)
DS1315 336 +
DS1315S-5
0°C to +70°C
5
16 SO (300 mils)
DS1315 56
DS1315S-5+
0°C to +70°C
5
16 SO (300 mils)
DS1315 56 +
DS1315SN-5
-40°C to +85°C
5
16 SO (300 mils)
DS1315S 56
DS1315SN-5+
-40°C to +85°C
5
16 SO (300 mils)
DS1315S 56 +
DS1315S-5/T&R
0°C to +70°C
5
16 SO (300 mils)
DS1315S 56 +
DS1315S-5+T&R
0°C to +70°C
5
16 SO (300 mils)
DS1315S 56 +
DS1315-5
DS1315E XXXX-336
DS1315E XXXX-336 +
DS1315E XXXX-56
+ Denotes a lead-free/RoHS-compliant device.
* A “+” symbol located anywhere on the top mark indicates a lead-free device. An “N” located in the bottom right-hand corner of the top of the
package denotes an industrial device. “xxxx” can be any combination of characters.
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DS1315 Phantom Time Chip
Figure 1. Block Diagram
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DS1315 Phantom Time Chip
Operation
Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecutive write cycles containing the proper data on data in
(D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the
chip enable output pin ( CEO ).
After recognition is established, the next 64 read or write cycles either extract or update data in the Time
Chip and CEO remains high during this time, disabling the connected memory.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable input ( CEI ), output enable ( OE ), and write enable ( WE ). Initially, a read cycle using the
CEI and OE control of the Time Chip starts the pattern recognition sequence by moving pointer to the
first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CEI
and WE control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.
When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match
is found, the pointer increments to the next location of the comparison register and awaits the next write
cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If
a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the
comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as
described above until all the bits in the comparison register have been matched. (This bit pattern is shown
in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on
D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations
outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition
sequence or data transfer sequence to the Time Chip.
A standard 32.768 kHz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (X1, X2).
The crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information
on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal
Considerations with Dallas Real Time Clocks.”
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DS1315 Phantom Time Chip
Figure 2. Time Chip Comparison Register Definition
Note: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Time Chip are less than 1 in 1019.
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DS1315 Phantom Time Chip
Nonvolatile Controller Operation
The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the
ROM/ RAM select pin. When ROM/ RAM is connected to ground, the controller is set in the RAM mode
and performs the circuit functions required to make CMOS RAM and the timekeeping function
nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a
maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninterrupted power to CMOS
SRAM. The DS1315 also performs redundant battery control for high reliability. On power-fail, the
battery with the highest voltage is automatically switched to VCCO. If only one battery is used in the
system, the unused battery input should be connected to ground.
The DS1315 safeguards the Time Chip and RAM data by power-fail detection and write protection.
Power-fail detection occurs when VCCI falls below VPF which is set by an internal bandgap reference. The
DS1315 constantly monitors the VCCI supply pin. When VCCI is less than VPF, power-fail circuitry forces
the chip enable output ( CEO ) to VCCI or VBAT-0.2 volts for external RAM write protection. During
nominal supply conditions, CEO will track CEI with a propagation delay. Internally, the DS1315 aborts
any data transfer in progress without changing any of the Time Chip registers and prevents future access
until VCCI exceeds VPF. A typical RAM/Time Chip interface is illustrated in Figure 3.
When the ROM/ RAM pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a
read-only device that retains data in the absence of power, battery backup and write protection is not
required. As a result, the chip enable logic will force CEO low when power fails. However, the Time
Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. A
typical ROM/Time Chip interface is illustrated in Figure 4.
Figure 3. DS1315-to-RAM/Time Chip Interface
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DS1315 Phantom Time Chip
Figure 4. ROM/Time Chip Interface
Time Chip Register Information
Time Chip information is contained in eight registers of 8 bits, each of which is sequentially accessed 1
bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Time
Chip registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a
register could produce erroneous results. These read/write registers are defined in Figure 5.
Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing
the registers is always accomplished by stepping though all eight registers, starting with bit 0 of register 0
and ending with bit 7 of register 7.
AM–PM/12/24 Mode
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,
bit 5 is the second 10-hour bit (20-23 hours).
Oscillator and Reset Bits
Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the
reset pin input. When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set
to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing
data in the timekeeping registers. Reset operates independently of all other in-puts. Bit 5 controls the
oscillator. When set to logic 0, the oscillator turns on and the real time clock/calendar begins to
increment.
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DS1315 Phantom Time Chip
Zero Bits
Registers 1, 2, 3, 4, 5, and 6 contain 1 or more bits that will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
Figure 5. Time Chip Register Definition
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DS1315 Phantom Time Chip
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range, Commercial
Operating Temperature Range, Industrial
Storage Temperature Range
Soldering Temperature
-0.3V to +7.0V
0°C to +70°C
-45°C to +85°C
-55°C to +125°C
See IPC/JEDEC J-STD-020
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage 5
Volt Operation
Power Supply Voltage 3.3
Volt Operation
Input Logic 1
Input Logic 0
Battery Voltage VBAT1 or
VBAT2
(0°C to 70°C)
SYMBOL
VCC
MIN
4.5
TYP
5.0
MAX
5.5
UNITS
V
NOTES
1
VCC
3.0
3.3
3.6
V
1
VIH
VIL
VBAT1,
VBAT2
2.2
-0.3
2.5
VCC+0.3
+0.6
3.7
V
V
V
1
1
DC OPERATING ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 5.0 ± 10%)
PARAMETER
Average VCC Power
Supply Current
VCC Power Supply Current,
(VCC0 = VCCI-0.3)
TTL Standby Current
( CEI = VIH)
CMOS Standby Current
( CEI = VCCI-0.2)
Input Leakage Current
(any input)
Output Leakage Current
(any input)
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = 4.0 mA)
Power-Fail Trip Point
Battery Switch Voltage
SYMBOL
ICC1
MIN
TYP
MAX
6
UNITS
mA
NOTES
6
ICC01
150
mA
7
ICC2
4
mA
6
ICC3
1.3
mA
6
10
IIL
-1
+1
µA
IOL
-1
+1
µA
VOH
2.4
VOL
VPF
VSW
4.25
VBAT1,
VBAT2
9 of 22
V
2
0.4
V
2
4.5
V
13
DS1315 Phantom Time Chip
DC POWER DOWN ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC < 4.5V)
PARAMETER
CEO Output Voltage
VBAT1 or VBAT2 Battery
Current
Battery Backup Current
@ VCCO = VBAT-0.2V
SYMBOL
VCEO
MIN
VCCI-0.2
or
VBAT1,2
-0.2
TYP
MAX
UNITS
V
NOTES
8
IBAT
0.5
µA
6
ICCO2
10
µA
9
AC ELECTRICAL OPERATING CHARACTERISTICS
(0°C to 70°C; VCC = 5.0 ± 10%)
ROM/ RAM = GND
PARAMETER
Read Cycle Time
CEI Access Time
OE Access Time
CEI to Output Low Z
OE to Output Low Z
CEI to Output High Z
OE to Output High Z
Read Recovery
Write Cycle
Write Pulse Width
Write Recovery
Data Setup
Data Hold Time
CEI Pulse Width
OE Pulse Width
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tOW
tRST
MIN
65
TYP
MAX
55
55
5
5
25
25
10
65
55
10
30
0
55
55
65
10 of 22
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
5
5
DS1315 Phantom Time Chip
AC ELECTRICAL OPERATING CHARACTERISTICS
(0°C to 70°C; VCC = 5.0 ± 10%)
ROM/ RAM = VCCO
PARAMETER
Read Cycle Time
CEI Access Time
OE Access Time
CEI to Output Low Z
OE to Output Low Z
CEI to Output High Z
OE to Output High Z
Address Setup Time
Address Hold Time
Read Recovery
Write Cycle
CEI Pulse Width
OE Pulse Width
Write Recovery
Data Setup
Data Hold Time
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tAS
tAH
tRR
tWC
tCW
tOW
tWR
tDS
tDH
tRST
MIN
65
TYP
MAX
55
55
5
5
25
25
5
5
10
65
55
55
10
30
0
65
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
5
5
DC OPERATING ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC = 3.3 ± 10%)
PARAMETER
Average VCC Power
Supply Current
Average VCC Power
Supply Current,
(VCCO = VCCI-0.3)
TTL Standby Current
( CEI = VIH)
CMOS Standby Current
( CEI = VCCI-0.2)
Input Leakage Current
(any input)
Output Leakage Current
(any input)
Output Logic 1 Voltage
(IOUT = 0.4 mA)
Output Logic 0 Voltage
(IOUT = 1.6 mA)
Power-Fail Trip Point
Battery Switch Voltage
SYMBOL
ICC1
MIN
TYP
MAX
3
UNITS
mA
NOTES
6
ICC01
100
mA
7
ICC2
2
mA
6
ICC3
1
mA
6
IIL
-1
+1
µA
ILO
-1
+1
µA
VOH
2.4
VOL
VPF
VSW
2.8
VBAT1,
VBAT2,
or VPF
11 of 22
V
2
0.4
V
2
2.97
V
14
DS1315 Phantom Time Chip
DC POWER DOWN ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC < 2.97V)
PARAMETER
CEO Output Voltage
SYMBOL
VCEO
MIN
VCCI
or
VBAT1,2
-0.2
TYP
MAX
UNITS
V
NOTES
8
VBAT1 OR VBAT2
Battery Current
IBAT
0.3
µA
6
Battery Backup Current
@ VCCO = VBAT-0.2
ICCO2
10
µA
9
AC ELECTRICAL OPERATING CHARACTERISTICS
ROM/ RAM = GND
(0°C to 70°C; VCC = 3.3 ± 10%)
PARAMETER
Read Cycle Time
CEI Access Time
OE Access Time
CEI to Output Low Z
OE to Output Low Z
CEI to Output High Z
OE to Output High Z
Read Recovery
Write Cycle
Write Pulse Width
Write Recovery
Data Setup
Data Hold Time
CEI Pulse Width
OE Pulse Width
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tOW
tRST
MIN
120
TYP
MAX
100
100
5
5
40
40
20
120
100
20
45
0
100
100
120
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UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
4
5
5
DS1315 Phantom Time Chip
AC ELECTRICAL OPERATING CHARACTERISTICS
(0°C to 70°C; VCC = 3.3 ± 10%)
ROM/ RAM = VCCO
PARAMETER
Read Cycle Time
CEI Access Time
OE Access Time
CEI to Output Low Z
OE to Output Low Z
CEI to Output High Z
OE to Output High Z
Address Setup Time
Address Hold Time
Read Recovery
Write Cycle
CEI Pulse Width
OE Pulse Width
Write Recovery
Data Setup
Data Hold Time
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tAS
tAH
tRR
tWC
tCW
tOW
tWR
tDS
tDH
tRST
MIN
120
SYMBOL
CIN
COUT
MIN
TYP
MAX
100
100
5
5
40
40
10
10
20
120
100
100
20
45
0
120
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
NOTES
4
5
5
(tA = 25°C)
13 of 22
TYP
MAX
10
10
UNITS
pF
pF
NOTES
DS1315 Phantom Time Chip
Figure 6. Timing Diagram: Read Cycle to Time Chip ROM/RAM = GND
Figure 7. Timing Diagram: Write Cycle to Time Chip ROM/RAM = GND
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DS1315 Phantom Time Chip
Figure 8. Timing Diagram: Read Cycle to Time Chip ROM/RAM = VCCO
Figure 9. Timing Diagram: Write Cycle to Time Chip ROM/RAM = VCCO
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DS1315 Phantom Time Chip
Figure 10. Timing Diagram: Reset Pulse
tRST
RST
5V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS,
ROM/ RAM = VCCO OR GND
PARAMETER
Recovery Time at
Power-Up
VCC Slew Rate
Power-Down
VPF(max) to VPF(min)
VCC Slew Rate
Power-Down
VPF(min) to VSW
VCC Slew Rate
Power-Up
VPF(min) to VPF(max)
CEI High to Power-Fail
CEI Propagation Delay
SYMBOL
MIN
tREC
1.5
tF
MAX
UNITS
NOTES
2.5
mS
11
300
µs
11
tFB
10
µs
11
tR
0
µs
11
µs
ns
11
2, 3, 11
tPF
tPD
TYP
(0°C to 70°C)
0
5
Figure 11. 5V Power-Up Condition
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DS1315 Phantom Time Chip
Figure 12. 5V Power-Down Condition
3.3V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS,
(0°C to 70°C)
ROM/ RAM = VCCO OR GND
PARAMETER
Recovery Time at
Power-Up
VCC Slew Rate
Power-Down
VPF(max) to VPF(min)
VCC Slew Rate
Power-Up
VPF(min) to VPF(max)
CEI High to Power-Fail
CEI Propagation Delay
SYMBOL
MIN
tREC
1.5
tF
TYP
MAX
UNITS
NOTES
2.5
ms
12
300
µs
12
tR
0
µs
12
tPF
tPD
0
µs
ns
12
2, 3, 11
10
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DS1315 Phantom Time Chip
NOTES:
1)
2)
3)
4)
All voltages are referenced to ground.
Measured with load shown in Figure 15.
Input pulse rise and fall times equal 10 ns.
tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM
mode.
5) tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in
ROM mode.
6) Measured without RAM connected.
7) ICCO1 is the maximum average load current the DS1315 can supply to external memory.
8) Applies to CEO with the ROM/ RAM pin grounded. When the ROM/ RAM pin is connected to VCCO,
CEO will go to a low level as VCCI falls below VBAT.
9) ICCO2 is the maximum average load current that the DS1315 can supply to memory in the battery
backup mode.
10) Applies to all input pins except RST . RST is pulled internally to VCCI.
11) See Figures 11 and 12.
12) See Figures 13 and 14.
13) VSW is determined by the larger of VBAT1 and VBAT2.
14) VSW is determined by the smaller of VBAT1, VBAT2, and VPF.
Figure 13. 3.3V Power-Up Condition
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DS1315 Phantom Time Chip
Figure 14. 3.3V Power-Down Condition
Figure 15. Output Load
19 of 22
DS1315 Phantom Time Chip
PIN CONFIGURATIONS (continued)
X1
1
16
VCC1
X1
1
20
VCC1
X2
2
15
VCC0
X2
2
19
VCC0
WE
3
14
BAT2
WE
3
18
BAT2
NC
4
17
NC
BAT1
5
16
RST
GND
15
OE
NC
6
7
14
NC
D
8
13
CEI
Q
9
12
CEO
GND
10
11
ROM/RAM
BAT1
4
13
RST
GND
5
12
OE
D
6
11
CEI
Q
7
10
CEO
GND
8
9
ROM/RAM
16-Pin SO (300 mil)
20-Pin TSSOP
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.)
16-PIN DIP
PKG
DIM.
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
20 of 22
16-PIN
MIN
MAX
0.740
0.780
0.240
0.260
0.120
0.140
0.300
0.325
0.015
0.040
0.110
0.140
0.090
0.110
0.300
0.370
0.008
0.012
0.015
0.021
DS1315 Phantom Time Chip
16-PIN SO
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
L IN.
MM
PHI
21 of 22
16-PIN
MIN
MAX
0.402
0.412
10.21
10.46
0.290
0.300
7.37
7.65
0.089
0.095
2.26
2.41
0.004
0.012
0.102
0.30
0.094
0.105
2.38
2.68
0.050 BSC
1.27 BSC
0.398
0.416
10.11
10.57
0.009
0.013
0.229
0.33
0.013
0.019
0.33
0.48
0.016
0.040
0.40
1.02
0°
8°
DS1315 Phantom Time Chip
16-PIN TSSOP
DIM
A MM
A1 MM
A2 MM
C MM
L MM
e1 MM
B MM
D MM
E MM
G MM
H MM
phi
MIN
MAX
—
1.10
0.05
—
0.75
1.05
0.09
0.18
0.50
0.70
0.65 BSC
0.18
0.30
6.40
6.90
4.40 NOM
0.25 REF
6.25
6.55
0°
8°
22 of 22
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