Cadeka CDK1300 8-bit, 250 msps adc with demuxed output Datasheet

Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
CDK1300
8-bit, 250 MSPS ADC with Demuxed Outputs
n
TTL/CMOS/PECL input logic compatible
n
High conversion rate: 250 MSPS
n
Single +5V power supply
n
Very low power dissipation: 310mW
n
220MHz full power bandwidth
n
Power-down mode
n
+3.0V/+5.0V (LVCMOS) digital output The CDK1300 is a high-speed, 8-bit analog-to-digital converter implemented
in an advanced BiCMOS process. An advanced folding and interpolating
architecture provides both a high conversion rate and very low power
dissipation of only 310mW. The analog inputs can be operated in
either single-ended or differential input mode. A 2.5V common mode
reference is provided on chip for the single-ended input mode to minimize
external components.
logic compatibility
n
The CDK1300 digital outputs are demuxed (double-wide) with both dualchannel and single-channel selectable output modes. Demuxed mode
supports either parallel aligned or interleaved data output. The output logic
is both +3.0V and +5.0V compatible. The CDK1300 is available in a 44-lead
TQFP surface mount package over the industrial temperature range of -40°C
to +85°C.
Single/demuxed output ports selectable
Applications
n
RGB video processing
n
Digital communications
n
High-speed instrumentation
n
Digital Sampling Oscilloscopes (DSO)
n
Projection display systems
Block Diagram
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
General Description
features
REV 1A
Ordering Information
Part Number
Package
Pb-Free
RoHS Compliant
Operating Temperature Range
Packaging Method
CDK1300ITQ44
TQFP-44
Yes
Yes
-40°C to +85°C
Rail
CDK1300ITQ44_Q
TQFP-44
No
No
-40°C to +85°C
Rail
Moisture sensitivity level for all parts is MSL-1.
©2008 CADEKA Microcircuits LLC www.cadeka.com
Data Sheet
Pin Configuration
TQFP-44
Pin Assignments
Pin Name
40
VIN+
Description
Non-inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally
39
VIN-
Inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally
16-9
DA0–DA7
Data output bank A; 3V/5V LVCMOS compatible
19-26
DB0–DB7
Data output bank B; 3V/5V LVCMOS compatible
28
DCLKOUT
Non-inverted data output clock; 3V/5V LVCMOS compatible
27
DCLKOUT
Inverted data output clock; 3V/5V LVCMOS compatible
4
CLK
Non-inverted clock input pin; 100k pulldown to AGND, internally
3
CLK
Inverted clock input pin; 17.5k pullup to Vcc and 7.5k pulldown to AGND, internally
5
RESET
RESET synchronizes the data sampling and data output bank relationship when in dual channel
mode (DMODE1 = 0); 100k pulldown to AGND, internally
6
RESET
Inverted RESET input pin; 17.5k pullup to Vcc and 7.5 pulldown to AGND, internally
REV 1A
Pin No.
Internally: 100k pulldown to AGND on DMODE1 50k pullup to Vcc on DMODE2
32, 31
DMODE1,2
Data output mode pins: DMODE1 = 0, DMODE2 = 0: parallel dual channel output
DMODE1 = 0, DMODE2 = 1: interleaved dual channel output
DMODE1 = 1, DMODE2 = x: single channel data output on bank a (125 MSPS max)
2
PD
Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down
mode; 100k pulldown to AGND, internally
37
VCM
2.5V common mode voltage reference output
35, 36,
42, 43
AVCC
+5V analog supply
7, 17, 30
OVDD
+3V/+5V digital output supply
1, 33, 34,
38, 41, 44
AGND
Analog ground
8, 18, 29
DGND
Digital ground
©2008 CADEKA Microcircuits LLC www.cadeka.com
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
CDK1300
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Supply Voltage
AVCC
OVDD
Input Voltages
Analog inputs
Digital inputs
Min
-0.5V
-0.5V
Max
Unit
+6
+6
V
V
Vcc +0.5V
Vcc +0.5V
V
V
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
Parameter
Reliability Information
Parameter
Min
Storage Temperature Range
-65
Typ
Max
Unit
+125
°C
Max
Unit
+85
°C
Recommended Operating Conditions
Parameter
Min
Operating Temperature Range
-40
Typ
REV 1A
©2008 CADEKA Microcircuits LLC www.cadeka.com
3
Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
Symbol
Parameter
Conditions
Min
Resolution
Typ
Max
Units
bits
DLE
ILE
Differential Linearity Error
+25°C, ƒIN = 1KHz
-0.7/1.05
LSB
-40°C to +85°C, ƒIN = 1KHz
Integral Linearity Error
No Missing Codes
-0.95/+1.5
LSB
+25°C, ƒIN = 1KHz
±1.7
LSB
-40°C to +85°C, ƒIN = 1KHz
±2.25
LSB
@250 MSPS, ƒIN = 1KHz
Guaranteed
Analog Input
Input Voltage Range
VCM
PSRR
with respect to VIN-
±470
Input Common Mod
2.3
(2)
2.5
mVpp
2.0
V
Input Bias Current
+25°C
10
µA
Input Resistance
+25°C
50
kΩ
Input Capacitance
+25°C
Input Bandwidth
+25°C (-3dB of FS)
Gain Error
4
pF
220
MHz
+25°C
2
%
Offset Error
+25°C
±10
mV
Offset Power Supply Rejection Ratio
AVcc = 5V ±0.25V
0.5
mV/V
Timing Characteristics
250
Conversion Rate(1)
tpd1
tap
Output Delay (Clock-to-Data)
(2)
-40°C to +85°C
6
MSPS
8
10.5
ns
22
ps/°C
Aperture Delay Time
0.5
ns
Aperture Jitter Time
2.0
ps-RMS
Single Channel Mode
2.5
Cycle
Demuxed Interleaved Mode
2.5
Cycle
Channel B
2.5
Cycle
Channel A
3.5
Cycle
Pipeline Delay (Latency)
Demuxed Parallel Mode
CLK to DCLKOUT Delay Time
tpd2
Single Channel Mode(2)
tpd3
Dual Channel Mode
(2)
4
6
7
ns
5.3
6.16
7.8
ns
5.8
6.4
Bits
Dynamic Performance
ENOB
SNR
THD
SINAD
Effective Number of Bits
Signal-to-Noise Ratio
Total Harmonic Distortion
Signal-to-Noise and Distortion
ƒIN = 70MHz, +25°C(1)
ƒIN = 70MHz, -40°C to +85°C
5.5
6.0
Bits
ƒIN = 70MHz, +25°C(1)
42
43
dB
ƒIN = 70MHz, -40°C to +85°C(2)
36
40
dB
ƒIN = 70MHz, +25°C
(2)
(1)
ƒIN = 70MHz, -40°C to +85°C(2)
ƒIN = 70MHz , +25°C(1)
ƒIN = 70MHz, -40°C to +85°C
(2)
-43
-40
dB
-42
-37
dB
37
40
dB
35
38
dB
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
©2008 CADEKA Microcircuits LLC www.cadeka.com
4
REV 1A
Output Delay Tempco
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
8
DC Performance
Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
5.0
5.25
V
5.25
V
Power Supply Requirements
Analog Voltage Supply(2)
4.75
OVDD
Digital Voltage Supply(2)
2.75
AVcc
Current
(1)
Power Dissipation(1)
with Internal Voltage Reference
62
70
mA
310
350
mW
2.5
2.55
Common Mode Reference Output
Voltage(1)
2.45
Voltage Tempco
Output Impedance
PSRR
IOUT = ±50µA
Power Supply Rejection Ratio
V
100
ppm/°C
1
kΩ
63
mV/V
Clock and Reset Inputs (Differential and Single-Ended)
VDIFF
Differental Signal Amplitude(1)
400
VIHD
Differental High Input Voltage
VILD
Differental Low Input Voltage(2)
VCMD
mVpp
1.4
5
V
0
3.9
V
Differental Common Mode Input(2)
1.2
4.1
V
VIH
Single-Ended High Input Voltage
1.8
VIL
Single-Ended Low Input Voltage(2)
IIH
High Input Current(1)
VID = 1.5V
-100
IIL
Low Input Current(1)
VID = 1.5V
-100
(2)
(2)
V
1.2
V
20
+100
µA
20
+100
µA
Power Down and Mode Control Inputs (Single-Ended)
High Input Voltage(2)
2.0
AVcc
V
Low Input Voltage(2)
0
1.0
V
Max Input Current Low
(1)
Max Input Current High <4.0V(1)
-100
10
+100
µA
-100
10
+100
µA
Digital Outputs
Logic “1“ Voltage(1)
IOH = -0.5mA
Logic “0“ Voltage(1)
IOL = +1.6mA
0.13
OVDD = 3V, 10pF load
3.5
ns
OVDD = 5V, 10pF load
2.0
ns
OVDD = 3V, 10pF load
1.3
ns
OVDD = 5V, 10pF load
0.7
ns
TR/TF DCLK
V
0.2
V
REV 1A
TR/TF Data
OVDD-2.0 OVDD-0.06
Notes:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
©2008 CADEKA Microcircuits LLC www.cadeka.com
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
AVcc
5
Data Sheet
Typical Performance Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
AC Performance vs. Temperature
SFDR, SNR, –THD, SINAD (dB)
in = 70MHz
55
50
SFDR
45
–THD
SNR
40
SINAD
35
30
-40
-20
0
20
40
60
80
60
in = 70MHz
55
50
SFDR
45
SNR
–THD
40
SINAD
35
30
100
0
50
Temperature (°C)
70
2.8
65
AVcc (mA)
AVCC Current (mA)
75
60
55
200
250
300
2.6
2.4
2.2
50
-20
0
20
40
60
80
2.0
100
-40
-20
4.0
1.05
2.0
1.04
Gain (%)
1.06
0
1.02
-4.0
1.01
20
40
60
Temperature (°C)
©2008 CADEKA Microcircuits LLC 60
80
100
1.03
-2.0
0
40
Percent Gain Error vs. Temperature
6.0
-20
20
Temperature (°C)
Voltage Offset Error vs. Temperature
-40
0
REV 1A
-40
Temperature (°C)
mV
150
AVcc Current Power Down vs. Temp.
3.0
-6.0
100
Sample Rate (MSPS)
AVcc Current vs. Temperature
45
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
SFDR, SNR, –THD, SINAD (dB)
AC Performance vs. Temperature
60
80
100
1.00
-40
-20
0
20
40
60
80
100
Temperature (°C)
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6
Data Sheet
Typical Performance Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, ƒclk = 250MHz, 50% duty cycle,
ƒIN = 70MHz, dual channel mode; unless otherwise noted)
Input Bandwidth
Common-Mode Ref. Voltage vs. VCC
-2.50
0
-2.48
VCMOUT (V)
dB
-1
-2
-3
-2.46
-2.44
-2.42
-4
-5
0
100
200
300
400
500
600
-2.40
5.1
5.3
5.5
5.7
OVDD Current vs. Clk. Freq., Single Mode
60
50
OVDD = 5V
mA
60
OVDD = 3V
30
OVDD = 3V
40
20
20
10
50
100
150
200
250
0
300
0
25
50
75
100
125
150
REV 1A
0
OVDD = 5V
40
Clock Frequency (MHz)
Clock Frequency (MHz)
Total Power vs. Clock Frequency
Diff. Input Common-Mode Oper. Range
1000
6
800
5
OVDD = 5V
700
600
Volts (V)
Power Dissipation (mW)
4.9
OVDD Current vs. Clk. Freq., Dual Mode
80
OVDD = 3V
4
3
500
2
400
1
300
4.7
VCC (V)
100
mA
4.5
Input Frequency (MHz)
120
0
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
1
0
50
100
150
200
Clock Frequency (MHz)
©2008 CADEKA Microcircuits LLC 250
300
0
-50 -40
Common-Mode Operationg Range
-20
0
20
40
60
80
100
Temperature (°C)
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7
Data Sheet
Theory of Operation
The analog decode functions are the input buffer, input
THAs, three-bit folder, folding interpolators, and pipelining
THAs. The input buffer enables the part to withstand railtorail input signals without latchup or excessive currents
and also performs single-ended to differential conversion.
All of the THAs have the same basic architecture. Each
has a differential pair buffer followed by switched emitter
followers driving the hold capacitors. The input THA also
has hold mode feedthrough cancellation devices.
The digital decode consists of comparators, exclusive of
n
n
n
All data on bank A with clock rate limited to one-half maximum
Interleaved mode with data alternately on banks A and
B on alternate clock cycles
Parallel mode with bank A delayed one cycle to be synchronous with bank B every other clock cycle
If necessary, the input clock is divided by two. The divided clock selects the correct output bank. The user can
synchronize with the divided clock to select the desired
output bank via the differential RESET input.
The output logic family is CMOS with output OVDD supply
adjustable from 2.7V to 5.25V. There are also differential
clock output pins that can be used to latch the output data
in single bank mode or to indicate the current output bank
in demux mode.
Finally, a power-down mode is available, which causes the
outputs to become tri-state, and overall power is reduced
to about 24mW. There is a 2V reference to supply common mode for single-ended inputs that is not shut down
in powerdown mode.
Figure 1. Single Mode Timing Diagram
©2008 CADEKA Microcircuits LLC www.cadeka.com
8
REV 1A
The three MSBs of the ADC are generated in the first
threebit folder block, the output of which drives a differential reference ladder which also sets the full-scale
input range. Differential pairs at the ladder taps generate midscale, quarter and three-quarter scale, overrange,
and underrange. Every other differential pair collector is
cross-coupled to generate the eighth scale zero crossings.
The middle ADC block generates two bits from the folded
signals of the previous stages after pipeline THAs. Its outputs drive more pipeline THAs to push the decoding of the
three LSBs to the next half clock cycle. The three LSBs are
generated in interpolators that are latched one full clock
cycle after the MSBs.
The output data mode is controlled by the state of the
demux mode inputs. There are three output modes:
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
The CDK1300 is a three-step subranger. It consists of
two THAs in series at the input, followed by three ADC
blocks. The first block is a three-bit folder with over/under
range detection. The second block consists of two singlebit folding interpolator stages. There are pipelining THAs
between each ADC block.
cells for gray to binary decoding, and/or cells used for
mostly over/under range logic. There is a total of 2.5 clock
cycles latency before the output bank selection. In order to reduce sparkle codes and maintain sample rate,
no more than three bits at a time are decoded in any half
clock cycle.
Data Sheet
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
REV 1A
Figure 2. Dual Mode Timing Diagram
©2008 CADEKA Microcircuits LLC www.cadeka.com
9
Data Sheet
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
CDK1300
Figure 3. Typical Interface Circuit
REV 1A
Figure 4. CLK and Reset Equivalent Circuit
(without ESD Diodes)
Figure 5. Analog Input Equivalent Circuit
Typical Interface Circuit
Analog Input
Very few external components are required to achieve
the stated device performance. Figure 3 shows the typical
interface requirements when using the CDK1300 in normal circuit operation. The following sections provide
descriptions of the major functions and outline performance
criteria to consider for achieving the optimal device
performance.
The input of the CDK1300 can be configured in various
ways depending on whether a single-ended or differential
input is desired.
©2008 CADEKA Microcircuits LLC The AC-coupled input is most conveniently implemented
using a transformer with a center-tapped secondary winding.
The center tap is connected to the VCM pin as shown in
Figure 3. To obtain low distortion, it is important that the
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10
Data Sheet
selected transformer does not exhibit core saturation at
the full-scale voltage. Proper termination of the input is
important for input signal purity. A small capacitor across
the input attenuates kickback noise from the internal trackand-hold.
The CDK1300 has an on-board common-mode voltage reference circuit (VCM). It is 2.5V and is capable of driving
50μA loads typically. The circuit is commonly used to drive
the center tap of the RF transformer in fully differential
applications. For single-ended applications, this output
can be used to provide the level shifting required for the
single-to-differential converter conversion circuit. Bypass
VCM to AGND by external 0.01μF capacitor, as shown in
Figure 3 on the previous page.
Clock Input
The clock input on the CDK1300 can be driven by either a
single-ended or double-ended clock circuit and can handle
TTL, PECL, and CMOS signals. When operating at high
sample rates it is important to keep the pulse width of the
clock signal as close to 50% as possible. For TTL/CMOS
single- ended clock inputs, the rise time of the signal
also becomes an important consideration.
Figure 6. DC-Coupled Single-Ended to Differential
Conversion (power supplies and bypassing are not shown)
Input Protection
All I/O pads are protected with an on-chip protection circuit.
This circuit provides ESD robustness and prevents latchup
under severe discharge conditions without degrading analog transmission times.
The CDK1300 is operated from a single power supply in
the range of 4.75V to 5.25V. Normal operation is suggested to be 5.0V. All power supply pins should be bypassed
as close to the package as possible. The analog and digital
grounds should be connected together with a ferrite bead
as shown in the typical interface circuit and as close to the
ADC as possible.
Power-Down Mode
To save on power, the CDK1300 incorporates a powerdown function. This function is controlled by the signal on
pin PD. When pin PD is set high, the CDK1300 enters the
power-down mode. All outputs are set to high impedance.
In the powerdown mode the CDK1300 dissipates 24mW
typically.
©2008 CADEKA Microcircuits LLC The output circuitry of the CDK1300 has been designed
to be able to support three separate output modes. The
demuxed (double-wide) mode supports either parallel
aligned or interleaved data output. The single-channel mode
is not demuxed and can support direct output at speeds up
to 125 MSPS. The output format is straight binary (Table 1).
Table 1. Output Data Format
Analog Input
Output Code D7–D0
+FS
1111 1111
+FS - 1 LSB
1111 111Ø
+1 FS
1000 000Ø
-FS + 1 LSB
0000 000Ø
-FS
0000 0000
REV 1A
Power Supplies and Grounding
Digital Outputs
Ø indicates the flickering bit between logic 0 and 1
The data output mode is set using the DMODE1 and
DMODE2 inputs (pins 32 & 31 respectively). Table 2 describes
the mode switching options.
Table 2. Output Data Modes
Output Mode
DMODE1
DMODE2
Parallel Dual Channel Output
0
0
Interleaved Dual Channel Output
0
1
Single Channel Data Output
(Bank A only 125 MSPS max)
1
X
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CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
Figure 6 illustrates a solution (based on operational amplifiers) that can be used if a DC-coupled single-ended input
is desired.
Common-Mode Voltage Reference Circuit
11
Data Sheet
Evaluation Board
transformer (1:1). An application note (TBD) describing
the operation of this board, as well as information on the
testing of the CDK1300, is also available. Contact the
factory for price and availability of the TBD.
Mechanical Dimensions
TQFP-44 Package
TQFP-44
A
B
INCHES
PIN1
Index
C D
E
SYMBOL
A
B
C
D
E
F
G
H
I
J
K
MIN
TYP
0.472
0.394
0.394
0.472
0.031
0.012
0.053
0.002
0.018
0.039
0-7°
MILLIMETERS
MAX
MIN
0.018
0.057
0.006
0.030
0.300
1.35
0.05
0.45
TYP MAX
12.00
10.00
10.00
12.00
0.80
0.45
1.45
0.15
0.75
1.00
0-7°
F
G
H
I
K
J
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
The TBD evaluation board is available to aid designers
in demonstrating the full performance of the CDK1300.
This board includes a clock driver and reset circuit, adjustable references and common mode, a single-ended to
differential input buffer and a single-ended to differential
REV 1A
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
A m p l i fy t h e H u m a n E x p e r i e n c e
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