OBSOLETE CLC404 www.ti.com SNOS851F – MAY 1999 – REVISED APRIL 2013 CLC404 Wideband, High Slew Rate, Monolithic Op Amp Check for Samples: CLC404 FEATURES DESCRIPTION • • • • • • The CLC404 is a high speed, monolithic op amp that combines low power consumption (110mW typical, 120mW maximum) with superior large signal performance. Operating off of ±5V supplies, the CLC404 demonstrates a large signal bandwidth (5VPP output) of 165MHz. The bandwidth performance, along with other speed characteristics such as rise and fall time (2.1ns for a 5V step), is nearly identical to the small signal performance since slew rate is not limiting factor in the CLC404 design. 1 2 165MHz Large Signal Bandwidth (5VPP) 2600V/µs Slew Rate Low Power: 110mW Low Distortion: −53dBc at 20MHz 10ns Settling to 0.2% 0.07% Diff. Gain, 0.03° Diff. Phase APPLICATIONS • • • • • Fast A/D Conversion Line Drivers Video Distribution High Speed Communications Radar, IF Processors Large Signal Pulse Response With its 175MHz bandwidth and 10ns settling (0.2%), the CLC404 is ideal for driving ultra fast flash A/D converters. The 0.5° deviation from linear phase, coupled with -53dBc 2nd harmonic distortion and 60dBc 3rd harmonic distortion (both at 20MHz), is well suited for many digital and analog communication applications. These same characteristics, along with 70mA output current, differential gain of 0.07%, and differential phase at 0.03°, make the CLC404 an appropriate high performance solution for video distribution and line driving applications. Constructed using an advanced, complementary bipolar process and proven current feedback topologies, the CLC404 provides performance far beyond that of other monolithic op amps. The CLC404 is available in several versions to meet a variety of requirements. Enhanced Solutions (Military/Aerospace) SMD Number: 5962-90994 Space level versions also available. CONNECTION DIAGRAM Figure 1. PDIP & SOIC Pinout See Package Numbers P and D Figure 2. SOT-23 Pinout See Package Number DBV 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated OBSOLETE CLC404 SNOS851F – MAY 1999 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (VCC) IOUT ±7V Output is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed... 60mA Common Mode Input Voltage ±VCC Differential Input Voltage 10V Junction Temperature +150°C −40°C to +85°C Operating Temperature Range −65°C to +150°C Storage Temperature Range Lead Solder Duration +300°C ESD rating human body model (1) (2) 10 sec 500V Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of ELECTRICAL CHARACTERISTICS specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. OPERATING RATINGS Thermal Resistance Package (θJC) (θJA) PDIP 65°C/W 120°C/W SOIC 60°C/W 140°C/W 2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC404 OBSOLETE CLC404 www.ti.com SNOS851F – MAY 1999 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS AV= +6, VCC = ±5V, Rg & RL =100Ω, Rf = 500Ω; unless specified Symbol Parameter Conditions Ambient Temperature Typ Max/Min Ratings (1) CLC404AJ +25°C −40°C +25°C +85°C Units Frequency Domain Response SSBW -3dB Bandwidth VOUT <2VPP 175 >150 >140 >120 MHz LSBW -3dB Large Signal VOUT<5VPP 165 >140 >140 >110 MHz Gain Flatness VOUT<2VPP GFPL Peaking <40MHz 0 <0.4 <0.3 <0.4 dB GFPH Peaking >40MHz 0 <0.7 <0.5 <0.7 dB Rolloff <75MHz 0.2 <1.0 <1.1 <1.3 dB DC to 75MHz 0.5 <1.0 <1.0 <1.2 deg 2V Step 2.0 <2.4 <2.4 <2.9 ns 5V Step 2.1 <2.6 <2.6 <3.2 ns GFR LPD Linear Phase Deviation Time Domain Response TRS Rise and Fall Time TRL TS Settling Time to ±0.2% 2V Step 10 <15 <15 <15 ns OS Overshoot 2V Step 5 <15 <12 <15 % 2600 >2000 >2000 >2000 V/µs SR Slew Rate (Measured at AV +2) (2) Distortion And Noise Response HD2 2nd Harmonic Distortion 2VPP,20MHz −53 <−40 <−45 <−45 dBc HD3 3rd Harmonic Distortion 2VPP,20MHz −60 <−50 <−50 <−50 dBc >1MHz −159 <−157 <−157 <−156 dBm (1Hz) 1MHz to 200MHz 40 <45 <45 <50 µV 0.07 - - - % 0.03 - - - ° 2 <±9.0 <±5.0 <±10.0 mV 30 <±50 - <±50 µV/°C 15 <±44 <±22 <±22 µA 150 <±275 - <±200 nA/°C 15 <±40 <±18 <±22 µA 150 <±275 - <±200 nA/C° Equivalent Input Noise SNF Noise Floor INV Integrated Noise DG Differential Gain DP Differential Phase (3) (3) Static, DC Performance VIO Input Offset Voltage DVIO IBN Average Temperature Coefficient Input Bias Current DIBN IBI (4) Non Inverting Average Temperature Coefficient Input Bias Current DIBI (4) (4) Inverting Average Temperature Coefficient PSRR Power Supply Rejection Ratio 52 >45 >48 >45 dB CMRR Common Mode Rejection Ration 50 >44 >46 >44 dB ICC Supply Current No Load, Quiescent 11 <12 <12 <12 mA Resistance 1000 >250 >500 >1000 kΩ Capacitance 1 <2 <2 <2 pF (4) Miscellaneous Performance RIN Non-Inverting Input CIN RO Output Impedence At DC 0.1 <0.3 <0.2 <0.2 Ω VO Output Voltage Range No Load ±3.3 >±2.8 >±3.0 >±3.0 V CMIR Common Mode Input Range For Rated Performance ±2.2 >±1.4 >±1.8 >±2.0 V IO Output Current ±60 >±35 >±50 >±50 mA (1) (2) (3) (4) Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. See the text on the back of the data sheet. Differential gain and phase measured at AV+2, Rf500Ω,RL 150Ω 1Vpp equivalent video signal, 0-100 IRE, 40 IREpp, 0IRE = 0 volts, at 75Ω load and 3.58MHz. See text. AJ-level: spec. is 100% tested at +25°C, sample at 85°C. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC404 3 OBSOLETE CLC404 SNOS851F – MAY 1999 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS 4 Frequency Response AV = +2V/V Frequency Response AV = +6V/V Figure 3. Figure 4. Frequency Response AV = +20V/V Inverting Frequency Response Figure 5. Figure 6. Bandwidth vs Load Capacitance Recommended RS vs Load Capacitance Figure 7. Figure 8. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC404 OBSOLETE CLC404 www.ti.com SNOS851F – MAY 1999 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Large Signal Pulse Response 2nd Harmonic Dist. vs. Amplitude Figure 9. Figure 10. 3rd Harmonic Dist. vs. Amplitude Settling Time Figure 11. Figure 12. 2nd Harmonic Distortion CL = 25pF 3rd Harmonic Distortion CL = 25pF Figure 13. Figure 14. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC404 5 OBSOLETE CLC404 SNOS851F – MAY 1999 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Equivalent Input Noise Differential Gain and Phase vs. Load Figure 15. Figure 16. CMRR and PSRR Figure 17. 6 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC404 OBSOLETE CLC404 www.ti.com SNOS851F – MAY 1999 – REVISED APRIL 2013 APPLICATION DIVISION Figure 18. Recommended Non-Inverting Gain Circuit Figure 19. Recommended Inverting Gain Circuit Slew Rate Slew rate limiting is a nonlinear response which occurs in amplifiers when the output voltage swing approaches hard, abrupt limits in the speed at which it can change. In most applications, this results in an easily identifiable “slew rate” as well as a dramatic increase in distortion for large signal levels. The CLC404 has been designed to provide enough slew rate to avoid slew rate limiting in almost all circuit configurations. The large signal bandwidth of 165MHz, therefore, is nearly the same as the 175MHz small signal bandwidth. The result is a lowdistortion, linear system for both small signals and large signals. Slew rate and large signal performance in the CLC404 can best be understood by first comparing the small and large signal performance plots at a gain of +6. In the CLC404, there is almost no difference between large and small signal performance at this gain. Large signal performance in the CLC404 at a gain of +6 is not slew rate limited. (In an amplifier which is slew limiting, the large signal response rolloff has an abrupt break indicating the onset of slew rate limitation.) Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC404 7 OBSOLETE CLC404 SNOS851F – MAY 1999 – REVISED APRIL 2013 www.ti.com The CLC404 reaches slew rate limits only for low non-inverting gains. In other words, slew rate limiting is constrained by common mode voltage swings at the input. (This is different from traditional slew rate constraints.) The large-signal frequency response plot at a gain of +2 shows a break in the response, which shows that slew rate limit has been reached. Note also that the frequency response plots at gain of +21 show that the large signal and small signal responses are nearly identical. Differential Gain and Phase Differential gain and phase are measurements useful primarily in composite video channels. Differential gain and phase are measured by monitoring the gain and phase of a high frequency carrier (3.58MHz for NTSC composite video) as the output of the amplifier is swept over a range of DC voltages. Any changes in gain and phase at the carrier frequency are the desired measurement, differential gain and phase. Specifications for the CLC404 include differential gain and phase. The test signals used are based on a 1VPP video level. Test conditions used are the following. DC sweep range: 0 to 100 IRE units (black to white) Carrier: 3.58MHz at 40 IRE units peak to peak The amplifier is specified for a gain of +2, and 150Ω load (for a backmatched 75Ω system.) IRE amplitudes are referred to 75Ω at the load of a video system. This is a different condition from the rest of the specifications (AV = +6, Rf = 100Ω). Source Impedance For best results, source impedance in the non-inverting circuit configuration (see Figure 18) should be kept below 3kΩ Above 3kΩ it is possible for oscillation to occur, depending on other circuit parasitics. Depending on the signal source, a resistor with a value of less than 3kΩ may be used to terminate the non-inverting input to ground. Feedback Resistor In current-feedback op amps, the value of the feedback resistor plays a major role in determining amplifier dynamics. It is important to select the correct value resistor. The CLC404 provides optimum performance with a 500Ω feedback resistor. Furthermore, the specifications shown on the previous pages are valid only when a 500Ω feedback resistor is used. Selection of an incorrect value can lead to severe rolloff in frequency-response (if the resistor value is too large) or peaking or oscillation (if the value is too low). Printed Circuit Layout As with any high frequency device, a good PCB layout will enhance performance. Ground plane construction and good power supply bypassing close to the package are critical to achieving full performance. In the non-inverting configuration, the amplifier is sensitive to stray capacitance to ground at the inverting input. Hence, the inverting node connections should be small with minimal coupling to the ground plane. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. Parasitic or load capacitance directly on the output will introduce additional phase shift in the loop degrading the loop phase margin and leading to frequency response peaking. A small series resistor before the capacitance effectively decouples this effect. The graphs on the preceding page illustrate the required resistor value and resulting performance vs. capacitance. Precision buffed resistors (PRP8351 series from Precision Resistive Products) with low parasitic reactances were used to develop the data sheet specifications. Precision carbon composition resistors will also yield excellent results. Standard spirally-trimmed RN55D metal film resistors will work with a slight decrease in bandwidth due to their reactive nature at high frequencies. Evaluation PC boards (part numbers CLC730013 for through-hole and CLC 730027 for SOIC) for the CLC404 are available. 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC404 OBSOLETE CLC404 www.ti.com SNOS851F – MAY 1999 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision E (April 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC404 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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