AD AD5024BRUZ-REEL7 Fully accurate, 12-/14-/16-bit vout nanodac, quad, spi interface, 4.5 v to 5.5 v in tssop Datasheet

Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC,
Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5024/AD5044/AD5064
FEATURES
GENERAL DESCRIPTION
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero-scale or midscale
3 power-down functions
Per-channel power-down
Low glitch on power-up
Hardware LDAC with LDAC override function
CLR function to programmable code
16-lead TSSOP
Internal reference buffer and internal output amplifier
The AD5024/AD5044/AD5064 are low power, quad 12-/14-/
16-bit buffered voltage output nanoDAC® DACs that offer relative
accuracy specifications of 1 LSB INL with individual reference
pins and can operate from a single 4.5 V to 5.5 V supply. The
AD5024/AD5044/AD5064 parts also offer a differential accuracy
specification of ±1 LSB. The parts use a versatile 3-wire, low
power Schmitt trigger serial interface that operates at clock rates
up to 50 MHz and is compatible with standard SPI, QSPI™,
MICROWIRE™, and DSP interface standards. A reference buffer
is also provided on-chip. The AD5024/AD5044/AD5064 incorporate a power-on reset circuit that ensures the DAC output
powers up to zero scale or midscale and remains there until a
valid write takes place to the device. The AD5024/AD5044/
AD5064 contain a power-down feature that reduces the current
consumption of the device to typically 400 nA at 5 V and provides
software selectable output loads while in power-down mode.
Total unadjusted error for the parts is <2 mV.
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Table 1. Related Devices
Part No.
AD5666
AD5063/AD5062
AD5061
AD5060/AD5040
Description
Quad,16-bit buffered DAC,16 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL
16-/14-bit nanoDAC, 4 LSB INL, SOT-23
16-/14-bit nanoDAC, 1 LSB INL, SOT-23
Quad channel available in 16-lead TSSOP package.
16-bit accurate, 1 LSB INL.
Low glitch on power-up.
High speed serial interface with clock speeds up to 50 MHz.
Reset to known output voltage (zero scale or midscale).
FUNCTIONAL BLOCK DIAGRAM
VREF A VREF B
VDD
LDAC
INPUT
REGISTER
DAC
REGISTER
DAC A
INPUT
REGISTER
DAC
REGISTER
DAC B
INPUT
REGISTER
DAC
REGISTER
DAC C
INPUT
REGISTER
DAC
REGISTER
DAC D
SCLK
SYNC
INTERFACE
LOGIC
DIN
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
POWER-DOWN
LOGIC
POWER-ON
RESET
LDAC CLR
BUFFER
POR
VREF C VREF D
GND
06803-001
AD5024/
AD5044/
AD5064
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD5024/AD5044/AD5064
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 18
Applications ....................................................................................... 1
Serial Interface ............................................................................ 18
General Description ......................................................................... 1
Standalone Mode ........................................................................ 18
Product Highlights ........................................................................... 1
Input Shift Register .................................................................... 19
Functional Block Diagram .............................................................. 1
SYNC Interrupt .......................................................................... 19
Revision History ............................................................................... 2
Power-On Reset .......................................................................... 20
Specifications..................................................................................... 3
Power-Down Modes .................................................................. 20
AC Characteristics........................................................................ 5
Clear Code Register ................................................................... 21
Timing Characteristics ................................................................ 6
LDAC Function .......................................................................... 21
Absolute Maximum Ratings............................................................ 7
Power Supply Bypassing and Grounding ................................ 21
ESD Caution .................................................................................. 7
Microprocessor Interfacing ....................................................... 23
Pin Configuration and Function Descriptions ............................. 8
Applications..................................................................................... 24
Typical Performance Characteristics ............................................. 9
Using a Reference as a Power Supply ....................................... 24
Terminology .................................................................................... 16
Bipolar Operation....................................................................... 24
Theory of Operation ...................................................................... 18
DAC Section ................................................................................ 18
Using the AD5024/AD5044/AD5064 with a
Galvanically Isolated Interface ................................................. 24
DAC Architecture ....................................................................... 18
Outline Dimensions ....................................................................... 25
Reference Buffer ......................................................................... 18
Ordering Guide .......................................................................... 25
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5024/AD5044/AD5064
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 3
Resolution
B Grade 1
Min Typ
Max
A Grade1, 2
Min Typ
Max
Unit
Conditions/Comments
16
14
12
16
Bits
AD5064
AD5044
AD5024
AD5064; TA = −40°C to +105°C
AD5064; TA = −40°C to +125°C
AD5044; TA = −40°C to +105°C
AD5044; TA = −40°C to +125°C
AD5024; TA = −40°C to +105°C
AD5024; TA = −40°C to +125°C
Relative Accuracy
Differential Nonlinearity
Offset Error
±0.5
+0.5
±0.25
±0.25
±0.12
±0.12
±0.2
±0.2
Offset Error Drift 4
Full-Scale Error
Gain Error
Gain Temperature Coefficient4
DC Crosstalk
±2
±0.01
±0.005
±1
40
±1
±2
±0.5
±1
±0.25
±0.5
±1
±1.8
±0.5
±0.5
0
LSB
±0.2
±0.2
±2
±0.01
±0.005
±1
40
±0.07
±0.05
Power-Up Time
DC PSRR
REFERENCE INPUTS
Reference Input Range
Reference Current
Reference Input Impedance
LOGIC INPUTS
Input Current 5
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance4
±1
±1.8
±0.07
±0.05
40
40
VDD
LSB
LSB
40
0.5
OUTPUT CHARACTERISTICS4
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Normal Mode
Power-Down Mode
Output Connected to
100 kΩ Network
Output Connected to
1 kΩ Network
Short-Circuit Current
±4
±4
All 1s loaded to DAC register. VREF < VDD
μV/mA
μV
Of FSR/°C
Due to single channel full-scale output
change, RL = 5 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
RL = 5 kΩ, RL =100 kΩ, and RL = ∞
1
V
nF
0.5
0.5
Ω
100
100
kΩ
Output impedance tolerance ± 400 Ω
1
1
kΩ
Output impedance tolerance ± 20 Ω
60
45
4.5
60
45
4.5
mA
mA
μs
−92
−92
dB
DAC = full scale, output shorted to GND
DAC = zero-scale, output shorted to VDD
Time to exit power-down mode to normal
mode of AD5024/AD5044/AD5064, 32nd
clock edge to 90% of DAC midscale value,
output unloaded
VDD ± 10%, DAC = full scale. VREF < VDD
VDD
50
V
μA
kΩ
Per DAC channel
Individual reference option
±1
0.8
μA
V
V
pF
35
120
VDD
50
VDD
μV/°C
% FSR
% FSR
ppm
μV
Code 512 (AD5064), Code 128 (AD5044),
Code 32 (AD5024) loaded to DAC register
1
2.5
0
LSB
mV
2.5
35
120
±1
0.8
2.2
2.2
4
4
Rev. 0 | Page 3 of 28
AD5024/AD5044/AD5064
Parameter
POWER REQUIREMENTS
VDD
IDD 6
Normal Mode
All Power-Down Modes 7
B Grade 1
Min Typ
Max
A Grade1, 2
Min Typ
Max
Unit
Conditions/Comments
4.5
4.5
5.5
V
DAC active, excludes load current
VIH = VDD and VIL = GND
6
2
30
mA
μA
μA
5.5
3
0.4
6
2
30
3
0.4
1
TA = −40°C to +105°C
TA = −40°C to +125°C
Temperature range is −40°C to +125°C, typical at 25°C.
A grade offered in AD5064 only.
Linearity calculated using a reduced code range—AD5064: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output
unloaded.
4
Guaranteed by design and characterization; not production tested.
5
Current flowing into individual digital pins.
6
Interface inactive. All DACs active. DAC outputs unloaded.
7
All four DACs powered down.
2
3
Rev. 0 | Page 4 of 28
AD5024/AD5044/AD5064
AC CHARACTERISTICS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD. All specifications TMIN to TMAX, unless otherwise
noted.
Table 3.
Parameter 1, 2
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Reference Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
AC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
Min
Typ
5.8
Max
8
Unit
μs
10.7
13
μs
1.5
3
−90
0.1
1.9
2
3.5
6
340
−80
64
60
6
V/μs
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
nV/√Hz
nV/√Hz
μV p-p
Conditions/Comments 3
¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ,
single channel update including DAC calibration sequence
¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, all channel
update including DAC calibration sequence
1 LSB change around major carry
VREF = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz
VREF = 3 V ± 0.86 V p-p
VREF = 3 V ± 0.2 V p-p, frequency = 10 kHz
DAC code = 0x8400, 1 kHz
DAC code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
1
Guaranteed by design and characterization; not production tested.
See the Terminology section.
3
Temperature range is −40°C to +125°C, typical at 25°C.
2
Rev. 0 | Page 5 of 28
AD5024/AD5044/AD5064
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX;
VDD = 4.5 V to 5.5 V
20
10
10
16.5
5
5
0
1.9
10.5
17
20
20
10
10
10.6
Parameter 1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time (all channel update)
SYNC rising edge to SCLK fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
Guaranteed by design and characterization; not production tested.
t1
t9
SCLK
t8
t3
t4
t2
t7
SYNC
t5
DIN
t6
DB23
DB0
t13
t10
LDAC1
t11
LDAC2
CLR
VOUT
t12
t14
06803-003
1
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
μs min
ns min
ns min
ns min
ns min
ns min
μs min
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. 0 | Page 6 of 28
AD5024/AD5044/AD5064
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUT to GND
VREF to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
Reflow Soldering Peak Temperature
Pb Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
(TJ MAX − TA)/θJA
113°C/W
260°C
Rev. 0 | Page 7 of 28
AD5024/AD5044/AD5064
LDAC
1
16
SCLK
SYNC
2
15
DIN
VDD
3
14
GND
VREF B
4
13
VOUTB
VREF A
5
VOUTA
6
VOUTC
POR
AD5024/
AD5044/
AD5064
12
VOUTD
11
VREF D
7
10
CLR
8
9
TOP VIEW
(Not to Scale)
VREF C
06803-005
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. 16-Lead TSSOP (RU-16) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
LDAC
2
SYNC
3
VDD
4
5
6
7
8
VREFB
VREFA
VOUTA
VOUTC
POR
9
10
VREFC
CLR
11
12
13
14
15
VREFD
VOUTD
VOUTB
GND
DIN
16
SCLK
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on
the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
DAC B Reference Input. This is the reference voltage input pin for DAC B.
DAC A Reference Input. This is the reference voltage input pin for DAC A.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up the
part to midscale.
DAC C Reference Input .This is the reference voltage input pin for DAC C.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
DAC D Reference Input .This is the reference voltage input pin for DAC D.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. 0 | Page 8 of 28
AD5024/AD5044/AD5064
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–1.0
512
16,640
32,768
48,896
06803-022
DNL (LSB)
1.0
06803-019
INL (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
–0.8
–1.0
512
65,024
16,640
DAC CODE
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
–0.2
–0.4
–0.6
–0.8
1536
2048
2560
16,384
12,288
16,384
–0.2
–0.4
1024
12,288
0
–0.6
512
65,024
3072
3584
06803-023
DNL (LSB)
1.0
0.8
06803-020
INL (LSB)
1.0
0
48,896
Figure 7. AD5064 DNL
Figure 4. AD5064 INL
–1.0
32,768
DAC CODE
–0.8
–1.0
4096
0
4096
8192
DAC CODE
DAC CODE
Figure 8. AD5044 DNL
Figure 5. AD5044 INL
1.0
1.00
0.8
0.75
0.6
0.50
0.25
DNL (LSB)
0.2
0
–0.2
0
–0.25
–0.4
–0.50
–0.6
0
512
1024
1536
2048
2560
3072
3584
–1.00
4096
06803-024
–0.8
–1.0
–0.75
06803-021
INL (LSB)
0.4
0
4096
8192
DAC CODE
DAC CODE
Figure 9. AD5024 DNL
Figure 6. AD5024 INL
Rev. 0 | Page 9 of 28
AD5024/AD5044/AD5064
0.20
1.2
1.0
0.15
TA = 25°C
0.8
0.10
TUE (mV)
0.05
0
–0.05
0.4
0
–0.4
–0.15
–0.8
06803-025
–0.6
16,640
32,768
48,896
MIN TUE ERROR @ VDD = 5.5V
–0.2
–0.10
–0.20
512
MAX TUE ERROR @ VDD = 5.5V
0.2
06803-028
TUE ERROR (mV)
0.6
–1.0
–1.2
2.0
65,024
2.5
3.0
DAC CODE
Figure 10. Total Unadjusted Error (TUE)
1.6
1.4
4.0
4.5
5.0
5.5
Figure 13. TUE vs. Reference Input Voltage
0.015
TA = 25°C
1.2
1.0
0.010
DAC A
0.6
GAIN ERROR (%FSR)
0.8
INL ERROR (LSB)
3.5
REFERENCE VOLTAGE (V)
MAX INL ERROR @ VDD = 5.5V
0.4
0.2
0
–0.2
MIN INL ERROR @ VDD = 5.5V
–0.4
–0.6
0.005
0
DAC B
DAC D
DAC C
–0.005
–0.8
–1.0
06803-026
–1.4
–1.6
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD = 5.5V
VREF = 4.096V
–0.015
–60 –40 –20
5.5
06803-029
–0.010
–1.2
0
20
40
60
100
80
120
140
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
Figure 11. INL vs. Reference Input Voltage
Figure 14. Gain Error vs. Temperature
1.6
0.6
1.4 TA = 25°C
VDD = 5.5V
VREF = 4.096V
0.5
1.2
1.0
DAC C
0.4
OFFSET ERROR (mV)
0.6
0.4
MAX DNL ERROR @ VDD = 5.5V
0.2
0
–0.2
MIN DNL ERROR @ VDD = 5.5V
–0.4
–0.6
–0.8
0.2
0.1
DAC D
0
–0.1
DAC A
–1.4
2.5
3.0
3.5
4.0
4.5
5.0
5.5
DAC B
06803-030
–1.2
–1.6
2.0
0.3
–0.2
–1.0
06803-027
DNL ERROR (LSB)
0.8
–0.3
–0.4
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (ºC)
REFERENCE VOLTAGE (V)
Figure 12. DNL vs. Reference Input Voltage
Figure 15. Offset Error vs. Temperature
Rev. 0 | Page 10 of 28
120
140
AD5024/AD5044/AD5064
0.010
0.2
0.009
0.008
0.007
IDD (mA)
ERROR (%FSR)
0.1
GAIN ERROR
0
0.006
0.005
0.004
FULL-SCALE ERROR
0.003
–0.1
0.001
06803-031
–0.2
4.50
4.75
5.00
5.25
06803-034
0.002
0
512
5.50
16,640
48,896
65,024
Figure 19. Supply Current vs. Code
Figure 16. Gain Error and Full-Scale Error vs. Supply Voltage
0.12
10.0
0.09
7.5
IDD (mA)
0.06
5.0
2.5
06803-032
0.03
0
4.50
4.75
5.00
5.25
06803-035
OFFSET ERROR (mV)
32,768
DAC CODE
VDD (V)
0
–40
5.50
10
60
110 125
TEMPERATURE (°C)
VDD (V)
Figure 17. Offset Error Voltage vs. Supply Voltage
Figure 20. Supply Current vs. Temperature
10.0
7
6
7.5
IDD (mA)
4
3
2
5.0
2.5
0
2.80
2.85
2.90
2.95
3.00
IDD (mA)
3.05
3.10
0
4.50
06803-036
1
06803-033
FREQUENCY
5
4.75
5.00
5.25
VDD (V)
Figure 21. Supply Current vs. Supply Voltage
Figure 18. IDD Histogram, VDD = 5.0 V
Rev. 0 | Page 11 of 28
5.50
AD5024/AD5044/AD5064
10.0
1
2.5
3
0
06803-040
5.0
06803-037
IDD (mA)
7.5
1
0
3
2
4
DIGITAL INPUT VOLTAGE (V)
CH1 2V
5
Figure 22. Supply Current vs. Digital Input Voltage
CH3 2V
M2ms
T
20.4%
A CH1
2.52V
Figure 25. Power-On Reset to Midscale
5.0
CH1 = SCLK
4.5
OUTPUT VOLTAGE (V)
4.0
1
3.5
VDD = 5V, VREF = 4.096V
TA = 25ºC
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
3.0
2.5
2.0
CH2 = VOUT
1.5
VDD = 5V
POWER-UP TO MIDSCALE
2
06803-038
0.5
0
06803-041
1.0
0
2
4
6
8
10
12
CH1 5V
14
CH2 500mV
TIME (µs)
M2µs
T 55%
A CH2
1.2V
Figure 26. Exiting Power-Down to Midscale
Figure 23. Settling Time
6
GLITCH AMPLITUDE (mV)
5
CH1 2V
CH3 2V
M2ms
T
20.4%
A CH1
2
1
0
–1
–2
06803-039
3
3
–3
2.52V
06803-042
1
4
0
2.5
5.0
7.5
TIME (μs)
Figure 27. Digital-to-Analog Glitch Impulse
Figure 24. Power-On Reset to 0 V
Rev. 0 | Page 12 of 28
10.0
AD5024/AD5044/AD5064
7
0
VDD = 5V, VREF = 4.096V
TA = 25ºC
6
–20
4
VOUT LEVEL (dB)
–30
3
2
1
0
–40
–50
–60
–70
–1
–80
06803-043
–2
–3
0
2.5
5.0
7.5
06803-046
GLITCH AMPLITUDE (mV)
5
–4
VDD = 5V,
TA = 25ºC
DAC LOADED WITH MIDSCALE
VREF = 3.0V ± 200mV p-p
–10
–90
–100
10.0
5
20
10
TIME (μs)
Figure 28. Analog Crosstalk
24
VDD = 5V, VREF = 4.096V
TA = 25°C
9
10
20
4
18
SETTLING TIME (μs)
3
2
1
0
–1
16
14
12
10
8
06803-044
–2
–3
0
2.5
5.0
7.5
06803-047
GLITCH AMPLITUDE (mV)
55
VDD = 5V, VREF = 3.0V
TA = 25°C
22
5
–4
50
Figure 31. Total Harmonic Distortion
7
6
30
40
FREQUENCY (kHz)
6
4
10.0
0
1
2
3
TIME (μs)
4
5
6
7
8
CAPACITANCE (nF)
Figure 29. DAC-to-DAC Crosstalk
Figure 32. Settling Time vs. Capacitive Load
VDD = 5V, VREF = 4.096V
TA = 25ºC
DAC LOADED WITH MIDSCALE
1μV/DIV
1
06803-045
06803-048
2
4s/DIV
CH1 5V
Figure 30. 0.1 Hz to 10 Hz Output Noise Plot
CH2 2V
M2µs
T 11%
Figure 33. Hardware CLR
Rev. 0 | Page 13 of 28
A CH1
2.5V
AD5024/AD5044/AD5064
10
0.10
0.08
0
CODE = MIDSCALE
VDD = 5V, VREF = 4.096V
0.06
0.04
ΔVOUT (V)
–20
–30
0.02
0
–0.02
–0.04
–40
CH A
CH B
CH C
CH D
3dB POINT
–0.06
06803-049
–50
–60
10
100
1000
06803-052
ATTENUATION (dB)
–10
–0.08
–0.10
–25
10000
–20
–15
–10
FREQUENCY (kHz)
–5
0
5
10
15
20
25
30
IOUT (mA)
Figure 37. Typical Current Limiting Plot
Figure 34. Multiplying Bandwidth
5.0
4.5
CH1 295mV p-p
OUTPUT VOLTAGE (V)
4.0
3.5
3.0
VDD = 5V, VREF = 4.096V
TA = 25°C
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
2.5
2.0
1.5
06803-050
0.5
0
06803-053
1.0
0
2
4
6
8
10
12
14
CH1 50mV
CH2 5V
TIME (µs)
M4µs
T 8.6%
A CH2
1.2V
Figure 38. Glitch on Entering Power-Down to Zero Scale, No Load
Figure 35. Typical Output Slew Rate
0.0010
0.0008
CODE = MIDSCALE
VDD = 5V, VREF = 4.096V
CH1 200mV p-p
0.0006
0.0002
0
–0.0002 VDD = 5.5V
–0.0006
–0.0008
–25
06803-054
–0.0004
06803-051
ΔVOLTAGE (V)
0.0004
–20
–15
–10
–5
0
5
10
15
20
25
CH1 50mV
30
CURRENT (mA)
Figure 36. Typical Output Load Regulation
CH2 5V
M4µs
T 8.6%
A CH2
1.2V
Figure 39. Glitch on Entering Power-Down to Zero Scale, 5 kΩ/200 pF Load
Rev. 0 | Page 14 of 28
AD5024/AD5044/AD5064
CH1 170mV p-p
CH1 20mV
CH2 5V
M4µs
T 8.6%
A CH2
06803-056
06803-055
CH1 129mV p-p
1.2V
CH1 20mV
Figure 40. Glitch on Exiting Power-Down from Zero Scale, No load
CH2 5V
M4µs
T 8.6%
A CH2
1.2V
Figure 41. Glitch on Exiting Power-Down from Zero Scale,
5 kΩ/200 pF Load
Rev. 0 | Page 15 of 28
AD5024/AD5044/AD5064
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer function.
Figure 4, Figure 5, and Figure 6 show plots of typical INL vs. code.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 7,
Figure 8 and Figure 9 show plots of typical DNL vs. code.
Offset Error
Offset error is a measure of the difference between the actual
VOUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
part with Code 512 (AD5064), Code 128 (AD5044), and Code 32
(AD5024) loaded into the DAC register. It can be negative or
positive and is expressed in millivolts.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Offset Error Drift
Offset error drift is a measure of the change in offset error with
a change in temperature. It is expressed in microvolts per degree
Celsius.
Gain Temperature Coefficient
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in parts per million of
full-scale range per degree Celsius.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VREF − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Measured with VREF < VDD.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nanovoltseconds and is measured when the digital input code is changed
by 1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 27.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2.5 V, and VDD is varied by ±10%.
Measured with VREF < VDD.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is, LDAC is high). It is expressed in
decibels.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but it is measured when the DAC is not being written
to (SYNC held high). It is specified in nanovolt-seconds and
measured with one simultaneous data and clock pulse loaded
to the DAC.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nanovolt-seconds.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high, and then pulsing LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nanovolt-seconds.
Rev. 0 | Page 16 of 28
AD5024/AD5044/AD5064
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nanovolt-seconds.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
Rev. 0 | Page 17 of 28
AD5024/AD5044/AD5064
THEORY OF OPERATION
DAC SECTION
SERIAL INTERFACE
The AD5024/AD5044/AD5064 are single 12-/14-/16-bit, serial
input, voltage output DACs. The parts operate from supply voltages
of 4.5 V to 5.5 V. Data is written to the AD5024/AD5044/AD5064
in a 32-bit word format via a 3-wire serial interface. The AD5024/
AD5044/AD5064 incorporate a power-on reset circuit that ensures
that the DAC output powers up to a known output state. The
devices also have a software power-down mode that reduces the
typical current consumption to less than 2 μA.
The AD5024/AD5044/AD5064 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI,
and MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
D
VOUT = VREFIN × ⎛⎜ N ⎞⎟
⎝2 ⎠
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535 for the 16-bit AD5064).
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture of the AD5064 consists of two matched
DAC sections. A simplified circuit diagram is shown in Figure 42.
The four MSBs of the 16-bit data word are decoded to drive 15
switches, E1 to E15. Each of these switches connects one of 15
matched resistors to either GND or the VREF buffer output. The
remaining 12 bits of the data-word drive the S0 to S11 switches
of a 12-bit voltage mode R-2R ladder network.
VOUT
2R
2R
2R
2R
2R
2R
2R
S0
S1
S11
E1
E2
E15
STANDALONE MODE
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5024/AD5044/AD5064 compatible
with high speed DSPs. On the 32nd falling clock edge, the last
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
the mode of operation. At this stage, the SYNC line can be kept
low or be brought high. In either case, it must be brought high
for a minimum of 1.9 μs (single channel) before the next write
sequence so that a falling edge of SYNC can initiate the next
write sequence. Because the SYNC buffer draws more current
when VIN = 2.2 V than it does when VIN = 0.8 V, SYNC should
be idled low between write sequences for even lower power
operation of the part. As mentioned previously, however, SYNC
must be brought high again just before the next write sequence.
Table 7. Command Definitions
Command
C3 C2 C1
0
0
0
0
0
0
0
0
1
C0
0
1
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
1
12-BIT R-2R LADDER
06803-006
VREF
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 42. DAC Ladder Structure
REFERENCE BUFFER
The AD5024/AD5044/AD5064 operate with an external reference.
Each DAC has a dedicated voltage reference pin. The reference
input pin has an input range of 2.5 V to VDD. This input voltage
is then used to provide a buffered reference for the DAC core.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages
on its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 5 kΩ in parallel with
200 pF to GND. The slew rate is 1.5 V/μs with a ¼ to ¾ scale
settling time of 13 μs.
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
Description
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Reserved
Reserved
Reserved
Table 8. Address Commands
A3
0
0
0
0
1
Rev. 0 | Page 18 of 28
A2
0
0
0
0
1
Address (n)
A1
0
0
1
1
1
A0
0
1
0
1
1
Selected DAC
Channel
DAC A
DAC B
DAC C
DAC D
All DACs
AD5024/AD5044/AD5064
INPUT SHIFT REGISTER
SYNC INTERRUPT
The AD5024/AD5044/AD5064 input shift register is 32 bits wide.
The first four bits are don’t cares. The next four bits are the command bits, C3 to C0 (see Table 7), followed by the 4-bit DAC
address bits, A3 to A0 (see Table 8), and finally the bit data-word.
The data-word comprises 12-, 14-, or 16-bit input code followed
by 8, 6, or 4 don’t care bits for the AD5024/AD5044/AD5064
(see Figure 43, Figure 44, and Figure 45). These data bits are
transferred to the DAC register on the 32nd falling edge of SCLK.
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 46).
DB31 (MSB)
X
X
DB0 (LSB)
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
COMMAND BITS
06803-009
DATA BITS
ADDRESS BITS
Figure 43. AD5024 Input Register Content
DB31 (MSB)
X
X
DB0 (LSB)
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
COMMAND BITS
06803-008
DATA BITS
ADDRESS BITS
Figure 44. AD5044 Input Register Content
DB31 (MSB)
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND BITS
06803-007
DATA BITS
ADDRESS BITS
Figure 45. AD5064 Input Register Content
SCLK
SYNC
DIN
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
DB31
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
Figure 46. SYNC Interrupt Facility
Rev. 0 | Page 19 of 28
06803-010
X
DB0 (LSB)
AD5024/AD5044/AD5064
POWER-ON RESET
The AD5024/AD5044/AD5064 contains a power-on reset
circuit that controls the output voltage during power-up. By
connecting the POR pin low, the AD5024/AD5044/AD5064
output powers up to zero scale. Note that this is outside the
linear region of the DAC; by connecting the POR pin high, the
AD5024/AD5044/AD5064 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the
DAC while it is in the process of powering up. There is also a
software executable reset function that resets the DAC to the
power-on reset code. Command 0111 is designated for this
reset function (see Table 7). Any events on LDAC or CLR
during power-on reset are ignored.
POWER-DOWN MODES
The AD5024/AD5044/AD5064 contain four separate modes of
operation. Command 0100 is designated for the power-down
function (see Table 7). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register
(Table 9). Table 9 shows how the state of the bits corresponds to
the mode of operation of the device. Any or all DACs (DAC D
to DAC A) can be powered down to the selected mode by
setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1.
See Table 10 for the contents of the input shift register during
power-down/power-up operation.
When both Bit DB9 and Bit D8 in the control register are set to
0, the part works normally with its normal power consumption
of 3 mA at 5 V. However, for the three power-down modes, the
supply current falls to 0.4 μA at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different options. The output is connected internally to GND
through either a 1 kΩ or a 100 kΩ resistor, or it is left opencircuited (three-state). The output stage is illustrated in Figure 47.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 4.5 μs for VDD = 5 V (see Figure 26).
Table 9. Modes of Operation
DB9
0
DB8
0
0
1
1
1
0
1
Operating Mode
Normal operation
Power-down modes:
1 kΩ to GND
100 kΩ to GND
Three-state
Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
LSB
DB27 DB26 DB25 DB24
0
1
0
0
Command bits (C2 to C0)
DB23 DB22 DB21 DB20
X
X
X
X
Address bits (A3 to A0)—
don’t cares
DAC
DB10
to
DB19
X
Don’t
cares
DB9 DB8
PD1
PD0
Powerdown mode
AMPLIFIER
POWER-DOWN
CIRCUITRY
VOUT
RESISTOR
NETWORK
Figure 47. Output Stage During Power-Down
Rev. 0 | Page 20 of 28
06803-011
MSB
DB31
to
DB28
X
Don’t
cares
DB4
to
DB7
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D DAC C DAC B DAC A
Power-down/power-up channel
selection—set bit to 1 to select
AD5024/AD5044/AD5064
CLEAR CODE REGISTER
The AD5024/AD5044/AD5064 have a hardware CLR pin that
is an asynchronous clear input. The CLR input is falling edge
sensitive. Bringing the CLR line low clears the contents of the
input register and the DAC registers to the data contained in
the user-configurable CLR register and sets the analog outputs
accordingly (see Table 11). This function can be used in system
calibration to load zero scale, midscale, or full scale to all channels
together. Note that zero scale and full scale are outside the linear
region of the DAC. These clear code values are user-programmable
by setting two bits, Bit DB1 and Bit DB0, in the control register
(see Table 11). The default setting clears the outputs to 0 V.
Command 0101 is designated for loading the clear code register
(see Table 7).
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If CLR is activated during a write
sequence, the write is aborted.
The CLR pulse activation time, which is the falling edge of CLR
to when the output starts to change, is typically 10.6 μs. If outside
the DAC linear region, it typically takes 10.6 μs after executing
CLR for the output to start changing (see Figure 33).
See Table 12 for contents of the input shift register during the
loading clear code register operation.
LDAC FUNCTION
Hardware LDAC Pin
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin, as shown in Figure 2.
Synchronous LDAC: After new data is read, the DAC registers
are updated on the falling edge of the 32nd SCLK pulse. LDAC
can be permanently low or pulsed.
Asynchronous LDAC: The outputs are not updated at the same
time that the input registers are written to. When LDAC goes
low, the DAC registers are updated with the contents of the
input register.
Software LDAC Function
Alternatively, the outputs of all DACs can be updated simultaneously using the software LDAC function by writing to Input
Register n and updating all DAC registers. Command 0010 is
reserved for this software LDAC function.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 14). Setting the LDAC
bit register (DB0 to DB3) to 0 for a DAC channel means that
this channel’s update is controlled by the hardware LDAC pin.
If this bit is set to 1, this channel updates synchronously; that is,
the DAC register is updated after new data is read, regardless of
the state of the hardware LDAC pin.
It effectively sees the hardware LDAC pin as being tied low.
(See Table 13 for the LDAC register mode of operation.) This
flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels
are synchronously updating.
Writing to the DAC using Command 0110 loads the 4-bit
LDAC register (DB3 to DB0). The default for each channel is 0;
that is, the LDAC pin works normally. Setting the bits to 1 means
that the DAC channel is updated regardless of the state of the
LDAC pin.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5024/AD5044/
AD5064 should have separate analog and digital sections. If the
AD5024/AD5044/AD5064 is in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5024/AD5044/AD5064.
The power supply to the AD5024/AD5044/AD5064 should
be bypassed with 10 μF and 0.1 μF capacitors. The capacitors
should physically be as close as possible to the device, with the
0.1 μF capacitor ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. It is important that the
0.1 μF capacitor have low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of common
ceramic types of capacitors. This 0.1 μF capacitor provides a low
impedance path to ground for high frequencies caused by
transient currents due to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals, if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the
ground plane only and the signal traces are placed on the solder
side. However, this is not always possible with a 2-layer board.
Rev. 0 | Page 21 of 28
AD5024/AD5044/AD5064
Table 11. Clear Code Register
DB1
CR1
0
0
1
1
Clear Code Register
DB0
CR0
0
1
0
1
Clears to Code
0x0000
0x8000
0xFFFF
No operation
Table 12. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
DB31 to DB28
X
Don’t cares
DB27
DB26
DB25
DB24
0
1
0
1
Command bits (C3 to C0)
DB23
X
DB22
DB21
DB20
X
X
X
Address bits (A3 to A0)
DB2 to DB19
X
Don’t cares
LSB
DB1
DB0
1/0
1/0
Clear code register
(CR1 to CR0)
Table 13. LDAC Overwrite Definition
Load DAC Register
LDAC Bits (DB3 to DB0)
LDAC Pin
LDAC Operation
0
1
Determined by the LDAC pin
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
1 or 0
X—don’t care
Table 14. 32-Bit Input Shift Register Contents for LDAC Overwrite Function
MSB
DB31 to
DB28
X
Don’t
cares
LSB
DB27 DB26 DB25 DB24
0
1
1
0
Command bits (C3 to C0)
DB23 DB22 DB21 DB20
X
X
X
X
Address bits (A3 to A0)—
don’t cares
Rev. 0 | Page 22 of 28
DB4 to
DB19
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D
DAC C
DAC B
DAC A
Setting LDAC bits to 1 overrides LDAC pin
AD5024/AD5044/AD5064
MICROPROCESSOR INTERFACING
AD5024/AD5044/AD5064 to 80C51/80L51 Interface
AD5024/AD5044/AD5064 to Blackfin ADSP-BF53x
Interface
Figure 50 shows a serial interface between the AD5024/AD5044/
AD5064 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5024/AD5044/AD5064, and RxD drives the serial
data line of the part. The SYNC signal is again derived from a
bit-programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5024/AD5044/
AD5064, P3.3 is taken low. The 80C51/80L51 transmit data in
8-bit bytes only; thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left low after the
first eight bits are transmitted, and a second write cycle is initiated
to transmit the second byte of data. P3.3 is taken high following
the completion of this cycle. The 80C51/80L51 output the serial
data in a format that has the LSB first. The AD5024/AD5044/
AD5064 must receive data with the MSB first. The 80C51/80L51
transmit routine should take this into account.
DT0PRI
TSCLK0
SYNC
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51*
AD5024/
AD5044/
AD5064*
P3.3
SYNC
AD5024/AD5044/AD5064 to 68HC11/68L11 Interface
TxD
SCLK
Figure 49 shows a serial interface between the AD5024/AD5044/
AD5064 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5024/AD5044/AD5064,
and the MOSI output drives the serial data line of the DAC.
RxD
DIN
Figure 48. AD5024/AD5044/AD5064 to Blackfin ADSP-BF53x Interface
AD5024/
AD5044/
AD5064*
PC7
SYNC
SCK
SCLK
MOSI
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5024/AD5044/AD5064 to MICROWIRE Interface
Figure 51 shows an interface between the AD5024/AD5044/
AD5064 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked into
the AD5024/AD5044/AD5064 on the rising edge of the SCLK.
MICROWIRE*
06803-013
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 50. AD5024/AD5044/AD5064 to 80C512/80L51 Interface
AD5024/
AD5044/
AD5064*
Figure 49. AD5024/AD5044/AD5064 to 68HC11/68L11 Interface
CS
SYNC
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5024/AD5044/
AD5064, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
SK
DIN
SO
SCLK
Rev. 0 | Page 23 of 28
*ADDITIONAL PINS OMITTED FOR CLARITY.
06803-015
TFS0
AD5024/
AD5044/
AD5064*
06803-012
ADSP-BF53x*
06803-014
Figure 48 shows a serial interface between the AD5024/AD5044/
AD5064 and the Blackfin® ADSP-BF53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5024/AD5044/AD5064, the setup for the interface is as
follows: DT0PRI drives the DIN pin of the AD5024/AD5044/
AD5064, and TSCLK0 drives the SCLK of the parts. The SYNC
pin is driven from TFS0.
Figure 51. AD5024/AD5044/AD5064 to MICROWIRE Interface
AD5024/AD5044/AD5064
APPLICATIONS
Because the supply current required by the AD5024/AD5044/
AD5064 is extremely low, an alternative option is to use a voltage
reference to supply the required voltage to the parts (see Figure 52).
This is especially useful if the power supply is quite noisy or if
the system supply voltages are at some value other than 5 V (for
example, 15 V). The voltage reference outputs a steady supply
voltage for the AD5024/AD5044/AD5064. If the low dropout
REF195 is used, it must supply 3 mA of current to the AD5024/
AD5044/AD5064, with no load on the output of the DAC. When
the DAC output is loaded, the REF195 also needs to supply the
current to the load. The total current required (with a 5 kΩ
load on the DAC output) is
This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
AD820/
OP295
VDD
10µF
USING THE AD5024/AD5044/AD5064 WITH A
GALVANICALLY ISOLATED INTERFACE
15V
SCLK
DIN
5V
VDD
AD5024/
AD5044/
AD5064
VOUT = 0V TO 5V
06803-016
3-WIRE
SERIAL
INTERFACE
–5V
Figure 53. Bipolar Operation
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 μV) error for the 4 mA current
drawn from it. This corresponds to a 0.196 LSB error.
SYNC
AD5024/
AD5044/
AD5064
3-WIRE
SERIAL INTERFACE
3 mA + (5 V/5 kΩ) = 4 mA
REF195
0.1µF
±5V
VOUT
06803-017
USING A REFERENCE AS A POWER SUPPLY
Figure 52. REF195 as Power Supply to the AD5024/AD5044/AD5064
BIPOLAR OPERATION
The AD5024/AD5044/AD5064 have been designed for singlesupply operation, but a bipolar output range is also possible using
the circuit shown in Figure 53. The circuit gives an output voltage
range of ±5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or an OP295 as the output amplifier.
Assuming VDD = VREF, the output voltage for any input code can
be calculated as follows:
⎡
⎛ D ⎞ ⎛ R1 + R2 ⎞
⎛ R2 ⎞⎤
VOUT = ⎢VDD × ⎜
⎟×⎜
⎟ − VDD × ⎜
⎟⎥
R1
65
,
536
⎝
⎠
⎝ R1 ⎠⎦
⎝
⎠
⎣
In process control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of
2.5 kV. The AD5024/AD5044/AD5064 use a 3-wire serial logic
interface, so the ADuM1300 three-channel digital isolator
provides the required isolation (see Figure 54). The power
supply to the part also needs to be isolated, which is done by
using a transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5024/
AD5044/AD5064.
5V
REGULATOR
10µF
POWER
0.1µF
VDD
SCLK
VIA
VOA
SCLK
ADuM1300
SDI
VIB
VOB
SYNC
DATA
VIC
VOC
DIN
AD5024/
AD5044/
AD5064
VOUT
where D represents the input code in decimal (0 to 65,535).
VOUT
⎛ 10 × D ⎞
=⎜
⎟ −5V
⎝ 65,536 ⎠
GND
06803-018
With VDD = 5 V, R1 = R2 = 10 kΩ,
Figure 54. AD5024/AD5044/AD5064 with a Galvanically Isolated Interface
Rev. 0 | Page 24 of 28
AD5024/AD5044/AD5064
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5064BRUZ 1
AD5064BRUZ-REEL71
AD5044BRUZ1
AD5044BRUZ-REEL71
AD5024BRUZ1
AD5024BRUZ-REEL71
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
Resolution
16 Bits
16 Bits
14 Bits
14 Bits
12 Bits
12 Bits
Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
AD5024/AD5044/AD5064
NOTES
Rev. 0 | Page 26 of 28
AD5024/AD5044/AD5064
NOTES
Rev. 0 | Page 27 of 28
AD5024/AD5044/AD5064
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06803-0-8/08(0)
Rev. 0 | Page 28 of 28
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