TI CDC305DR Octal divide-by-2 circuit/clock driver Datasheet

CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
D
D
D
D
D
D
D OR N PACKAGE
(TOP VIEW)
Replaces SN74AS305
Maximum Output Skew of 1 ns
Maximum Pulse Skew of 1 ns
TTL-Compatible Inputs and Outputs
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
Q3
Q4
GND
GND
GND
Q5
Q6
Q7
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Q2
Q1
CLR
VCC
VCC
CLK
PRE
Q8
description
The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four
in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC305 has output and pulse-skew parameters tsk(o) and tsk(p) to ensure performance as a clock driver
when a divide-by-two function is required.
The CDC305 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
PRE
CLK
Q1– Q4
Q5– Q8
L
H
X
L
H
H
L
X
L
L
X
H
L†
L
L†
H
H
L
Q0
Q0
H
H
↑
Q0
Q0
† This configuration does not persist when
PRE or CLR returns to its inactive (high)
level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
logic symbol†
CLR
14
S
10
PRE
CLK
R
11
C1
15
16
1
2
6
7
8
9
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
15
16
1
PRE
CLK
CLR
10
S
11
14
2
Q1
Q2
Q3
Q4
C1
6
R
1D
7
8
9
Q5
Q6
Q7
Q8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Maximum power dissipation at TA = 55°C (in still air) (see Note 1): D package . . . . . . . . . . . . . . . . . . 0.77 W
N package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
2
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CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
recommended operating conditions
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
TA
High-level input voltage
MIN
NOM
MAX
4.5
5
5.5
2
UNIT
V
V
0.8
V
High-level output current
– 24
mA
Low-level output current
48
mA
70
°C
Operating free-air temperature
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
II
IIH
IIL
IO‡
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = – 18 mA
IOH = – 2 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOH = – 24 mA
IOL = 48 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
MIN
VCC – 2
2
TYP†
MAX
UNIT
– 1.2
V
V
2.8
0.3
– 50
0.5
V
0.1
mA
20
µA
– 0.5
mA
– 150
mA
ICC
VCC = 5.5 V,
See Note 2
40
70
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 2: ICC is measured with CLK and PRE grounded, then with CLK and CLR grounded.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time before CLK↑
POST OFFICE BOX 655303
MIN
MAX
UNIT
0
80
MHz
CLR or PRE low
5
CLK high
4
CLK low
6
CLR or PRE inactive
6
• DALLAS, TEXAS 75265
ns
ns
3
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
fmax‡
tPLH
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
TYP†
MAX
2
6
9
2
6
9
3
7
12
3
7
12
MIN
80
tPHL
tPLH
tPHL
CLK
Q Q
Q,
RL = 500 Ω
Ω,
CL = 50 pF
PRE or CLR
Q Q
Q,
RL = 500 Ω
Ω,
CL = 50 pF
RL = 500 Ω
Ω,
See Figure 2
CL = 10 pF
F to
t 30 pF,
F
Q
tsk(o)
( )
CLK
Q
MHz
Q1, Q8
CLK
Q2 – Q7
1
RL = 500 Ω
Ω,
1.5
CL = 10 pF to 30 pF
2
From Output
Under Test
3.5
ns
Test Point
RL
CL
(see Note A)
LOAD CIRCUIT
3.5 V
1.3 V
0.3 V
tsu
tw
3.5 V
1.3 V
1.3 V
0.3 V
tPLH
tPHL
VOH
1.3 V
1.3 V
VOL
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = 2.5 ns, tf = 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
4
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ns
ns
PARAMETER MEASUREMENT INFORMATION
Q
ns
4.5
† All typical values are at VCC = 5 V, TA = 25°C.
‡ fmax minimum values are at CL = 0 to 30 pF.
CLK
ns
1.5
tr
tf
CLR
or
PRE
ns
1
Q1– Q8
tsk(p)
k( )
UNIT
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
CLR, PRE
0
CLK
tPHL1
tPLH1
Q1
tPLH2
tPHL2
tPLH3
tPHL3
tPLH4
tPHL4
Q2
Q3
Q4
tPHL5
tPLH5
Q5
tPHL6
tPLH6
Q6
tPHL7
tPLH7
Q7
tPHL8
tPLH8
Q8
NOTES: A. tsk(o) CLK to Q are calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4)
– The difference between the fastest and slowest of tPHLn (n = 1, 2, 3, 4)
B. tsk(o) CLK to Q are calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 5, 6, 7, 8)
– The difference between the fastest and slowest of tPHLn (n = 5, 6, 7, 8)
C. tsk(o) CLK to Q and Q are calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4), tPHLn (n = 5, 6, 7, 8)
– The difference between the fastest and slowest of tPHLn (n = 1, 2, 3, 4), tPLHn (n = 5, 6, 7, 8)
D. tsk(p) is calculated as the greater of | tPLHn – tPHLn | (n = 1, 2, 3, . . . , 8).
Figure 2. Waveforms for Calculation of tsk(o) and tsk(p)
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5
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
CDC305-1N
CDC305D
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
Package
Type
Package
Drawing
OBSOLETE
PDIP
N
16
TBD
Call TI
Call TI
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
CDC305DR
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
CDC305N
OBSOLETE
PDIP
N
16
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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