TMPN3120FE3MG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TMPN3120FE3MG Neuron® Chip for Distributed Intelligent Control Networks (LONW ORKS®) The TMPN3120FE3MG features extra single-chip memory in the form of a 2 Kbyte EEPROM, a 2 Kbyte SRAM, and a 16 Kbyte ROM. Neuron Chips have all the built-in communications and control functions ® required to implement LONWORKS nodes. These nodes may then be easily integrated into highly reliable distributed intelligent control networks. The typical functions for this chip are described below. Features Main features of the 20 MHz Neuron Chip (compared with the TMPN3120E1M) • Increased communication speed The maximum transmission speed has been increased twofold: 1.25 Mbps → 2.5 Mbps (This value applies to Single-Ended Mode only.) Weight: 1.1 g (typ.) • Shortened response time The amount of time required from I/O input to I/O output has been greatly reduced. Maximum speed: 7 ms → 3 to 4 ms • Increased I/O object speed The execution time for all objects has been halved. Example) Serial I/O 9600 bps Parallel I/O 1.2 µs/byte 1 2005-11-29 TMPN3120FE3MG I/O functions • Eleven programmable I/O pins • Two programmable 16-bit timers and counters built in • More than thirty different types of I/O functions to handle a wide range of input and output • ROM firmware image containing preprogrammed I/O drivers, greatly simplifying application programs Network functions • Two CPUs for communication protocol processing built in The communications and application CPUs execute in parallel. • Equipped with a built-in LonTalk protocol supporting all seven levels of the ISO OSI reference model • The ROM firmware image contains a complete network operating system, greatly simplifying application programs. • Built-in twisted-pair wire transceiver • Equipped with communications modes and communication speeds to support various types of external transceivers • Communication port transceiver modes and logical addresses are stored within the EEPROM. Can be amended via the network. Other functions • Application programs are also stored within the EEPROM. Can be updated by downloading over the network. • Built-in watchdog timer • Each chip has a unique ID number. Effective during the logical installation of networks • Low electrical consumption mode supported through a sleep mode • Reset time Prolongs the power-on reset time for at least 50 ms and keeps the operation stable during that time. • High-impedance communication port (CP0 to CP3) when powered down The communication port pins (CP0 to CP3) attain high impedance when the Neuron Chip is powered down. This feature eliminates the need for an external relay. • Built-in low-voltage detection circuit Prevents incorrect operations and writing errors in the EEPROM during drops in power voltage. An external LVD must be used to assert reset at a power supply voltage below 4.5 V if the Neuron Chip is operated at 20 MHz. • The package is SOP32-P-525-1.27 (lead-free type). 2 2005-11-29 TMPN3120FE3MG Timing for the main I/O objects during 20 MHz Neuron Chip operations I/O Model 10 MHz Timing 20 MHz Timing Parallel 2.4 µs/byte 1.2 µs/byte Bitshift 1, 10 or 15 kbps 2, 20 or 30 kbps Magcard Up to 8334 bps Up to 16668 bps Magtrack1 Up to 7246 bps Up to 14492 bps Neurowire master 1, 10 or 20 kbps 2, 20 or 40 kbps Neurowire slave Up to 18 kbps Up to 36 kbps Serial 600, 1200, 2400 or 4800 bps 1200, 2400, 4800 or 9600 bps Touch Supported Not supported Resolution: 0.4 to 51.2 µs Resolution: 0.2 to 25.6 µs Max range: 26.21 to 3355 ms Max range: 13.1 to 1678 ms Resolution: 0.2 to 25.6 µs Resolution: 0.1 to 12.8 µs Max range: 13.1 to 1678 ms Max range: 6.55 to 839 ms Frequency output Other timer/counter The specifications for the main timers during 20 MHz operations are as follows: Watchdog timer 420 ms Millisecond timers 1 to 32000 ms Second timers 1 to 65000 s Delay ( ) function 1 to 32767 counts Get_tick_count ( ) function 409.6 µs per count 3 2005-11-29 TMPN3120FE3MG Block Diagram Network communications port • Application I/O • General-purpose I/O • Parallel I/O • Serial I/O • Two timer/counters Etc. Clock and control 50 ms reset (min) Low-voltage detector reset circuit Item TMPN3120FE3MG CPU 8-bit CPU × 3 RAM 2,048 bytes ROM 16,384 bytes EEPROM 2,048 bytes 16-bit timer/counter 2 channels External memory interface Not available Package 32-pin SOP 4 2005-11-29 TMPN3120FE3MG Pin Connections TMPN3120FE3MG Note: All NC pins should be open. Pin Functions Pin No. Pin Name I/O Pin Function 15 CLK1 Input 14 CLK2 Output 1 ~RESET I/O (built-in pull-up) 8 ~SERVICE I/O (built-in configurable pull-up) 7 to 4 IO0 to IO3 I/O 3, 30 to 28 IO4 to IO7 I/O (built-in configurable pull-up) General I/O port. One of IO4 to IO7 can be specified as the No.1 timer/counter input. Output signals can be output to IO0. IO4 can be used as the No.2 timer/counter input with IO1 as output. 27, 26, 24 IO8 to IO10 I/O General I/O port. Can be used for serial communication with other devices. 2, 11, 12, 18, 25, 32 VDD Input Power input (5.0 V typ.) 9, 10, 13, 16, 23, 31 VSS Input Power input (0 V GND) 19, 20, 17, 21, 22 CP0 to CP4 I/O Bidirectional port for communications. Supports several communications protocols through specifying of mode. ― NC ― Do not connect anything. Leave pins open. Oscillator connection, or external clock input Oscillator connection. Leave open when the external clock is input to CLK1. Reset pin (active low) Service pin. Indicator output during operation. Large current sink capacity (20 mA) General I/O port. Note: ● The ~SERVICE and IO4 to IO7 terminals are programmable pull-ups. ● All VDD terminals must be externally connected. ● All VSS terminals must be externally connected. 5 2005-11-29 TMPN3120FE3MG Maximum Ratings (VSS = 0 V, VSS typ.) Item Symbol Rating Unit Power supply voltage VDD −0.3 to 7.0 V Input voltage VIN −0.3 to VDD + 0.3 V V Power dissipation PD 800 mW Storage temperature Tstg −65 to 150 °C Operating Conditions Symbol Min Typ. VDD 4.5 5.0 5.5 V VIH 2.0 ― VDD V VIL VSS ― 0.8 V VIH VDD − 0.8 V ― VDD V VIL VSS ― 0.8 V Operating frequency fosc 0.625 ― 20 MHz Operating temperature Topr −40 ― 85 °C Item Operating voltage Input voltage (TTL) Input voltage (CMOS) Max Unit Electrical Characteristics DC characteristic (VDD = 5.0 V ± 10%, VSS = 0 V, Ta = −40 to 85°C) (The above operating conditions apply unless otherwise stated.) Item Symbol Pins Test Condition Min Max Unit LOW level input voltage (1) VIL (1) IO0 to IO10 CP0, CP3, CP4, ~SERVICE ― 0 0.8 V LOW level input voltage (2) VIL (2) ~RESET ― 0 VDD× 0.3 V HIGH level input voltage (1) VIH (1) IO0 to IO10 CP0, CP3, CP4, ~SERVICE ― 2.0 VDD V HIGH level input voltage (2) VIH (2) ~RESET ― VDD− 0.7 V VDD V LOW output voltage (1) VOL (1) IO0 to IO3 ~SERVICE, ~RESET IOL = 20 mA 0 0.8 IOL = 10 mA 0 0.4 LOW output voltage (2) VOL (2) CP2, CP3 IOL = 40 mA 0 1.0 V LOW output voltage (3) VOL (3) Others (Note 1) IOL =1.4 mA 0 0.4 V HIGH output voltage (1) VOH (1) IO0 to IO3 IOH = −1.4 mA VDD− 0.4 V VDD V HIGH output voltage (2) VOH (2) ~SERVICE IOH = −1.4 mA VDD− 0.4 V VDD V HIGH output voltage (3) VOH (3) CP2, CP3 IOH = −40 mA VDD− 1.0 V VDD V HIGH output voltage (4) VOH (4) Others (Note 1) IOH = −1.4 mA VDD− 0.4 V VDD V VIN = VSS to VDD −10 10 µA VIN = 0 V −30 −300 µA 3.8 4.5 V Input current Pull-up current Low-voltage detection level IIN (Note 2) IPU (Note 3) IO4 to IO7 ~SERVICE, ~RESET VLVD VDD ― V Note 1: Output voltage characteristics exclude the CLK2 pin. Note 2: Excludes pull-up input pins. Note 3: The IO4 to IO7 and ~SERVICE pins have programmable pull-ups. ~RESET has a fixed pull-up. 6 2005-11-29 TMPN3120FE3MG Item Operating mode current consumption Symbol Typ. Max 20 MHz clock 35 55 10 MHz clock 17 30 9 15 6 8 1.25 MHz clock 4 5 0.625 MHz clock 2 3 16 100 5 MHz clock 2.5 MHz clock Sleep mode current consumption Note: IDD (OP) IDD (SLP) Unit mA µA Test conditions for current dissipation: VDD = 5 V; all output = with no load; all input = 0.2 V or below or VDD − 0.2 V; programmable pull-up = off; crystal oscillator clock input; differential receiver disabled. The current value (typ.) is a typical value when Ta = 25°C. The current value (max) applies to the rated temperature range at VDD = 5.5 V. 200 µA (typ.) to 600 µA (max) is added to the current of the differential receiver when the receiver is enabled. The differential receiver is enabled by either of the following conditions: ● When the Neuron Chip is in Run mode and the communication ports are in Differential mode. ● When the Neuron Chip is in Sleep mode, the communication ports are in Differential mode, and the Comm Port Wakeup is not masked. 7 2005-11-29 TMPN3120FE3MG Echelon, Neuron, LON, LonTalk, NodeBuilder, LONW ORKS, 3150 and 3120 are trademarks of Echelon Corporation (“Echelon”) registered in the United States and other countries. The Neuron Chip is manufactured by Toshiba under license from Echelon. A licensing agreement between the customer and Echelon must be concluded before purchase of any of the Neuron Chip products. 2 2 The Neuron Chip itself does not include the I C object function. You need the “I C Library” supplied by Echelon. 2 2 The Neuron Chip and the I C Library neither convey nor imply a right under any I C patent rights of Philips Electronics N.V. (“Philips”) to make, use or sell any product employing such patent rights. Please refer all questions 2 regarding I C patents and licenses to Philips at the following: Mr. Gert-Jan Hesselmann Corporate Intellectual Property Philips International B.V. Prof. Holstlaan 6 Building WAH 1-100 P.O. Box 220 5600 AE, Eindhoven, The Netherlands Phone : +31 40 274 32 61 Fax : +31 40 274 34 89 E-mail : [email protected] 8 2005-11-29 TMPN3120FE3MG Package Dimensions Weight : 1.1g (typ.) Lead-free type 9 2005-11-29 TMPN3120FE3MG About solderability, following conditions were confirmed Solderability (1) Use of Sn-63Pb solder Bath ⋅ solder bath temperature = 230°C ⋅ dipping time = 5 seconds ⋅ the number of times = once ⋅ use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath ⋅ solder bath temperature = 245°C ⋅ dipping time = 5 seconds ⋅ the number of times = once ⋅ use of R-type flux 10 2005-11-29