AD ADAV801 Audio codec for recordable dvd Datasheet

Audio Codec for Recordable DVD
ADAV801
PLL
VINL
VINR
ANALOG-TO-DIGITAL
CONVERTER
VREF
REFERENCE
VOUTL
VOUTR
CLATCH
CCLK
CIN
COUT
SYSCLK3
SYSCLK2
SYSCLK1
MCLKO
MCLKI
FUNCTIONAL BLOCK DIAGRAM
XOUT
CONTROL
REGISTERS
RECORD
DATA
OUTPUT
DIGITAL
INPUT/OUTPUT
SWITCHING MATRIX
(DATAPATH)
SRC
DIGITAL-TO-ANALOG
CONVERTER
AUX DATA
OUTPUT
DIT
OLRCLK
OBCLK
OSDATA
OAUXLRCLK
OAUXBCLK
OAUXSDATA
DITOUT
FILTD
ZEROL/INT
ZEROR
04577-001
DIR
DIRIN
IAUXBCLK
IAUXSDATA
AUX DATA
INPUT
IAUXLRCLK
IBCLK
PLAYBACK
DATA INPUT
ISDATA
ADAV801
ILRCLK
Stereo analog-to-digital converter (ADC)
Supports 48 kHz/96 kHz sample rates
102 dB dynamic range
Single-ended input
Automatic level control
Stereo digital-to-analog converter (DAC)
Supports 32 kHz/44.1 kHz/48 kHz/96 kHz/192 kHz
sample rates
101 dB dynamic range
Single-ended output
Asynchronous operation of ADC and DAC
Stereo sample rate converter (SRC)
Input/output range: 8 kHz to 192 kHz
140 dB dynamic range
Digital interfaces
Record
Playback
Auxiliary record
Auxiliary playback
S/PDIF (IEC 60958) input and output
Digital interface receiver (DIR)
Digital interface transmitter (DIT)
PLL-based audio MCLK generators
Generates required DVDR system MCLKs
Device control via SPI-compatible serial port
64-lead LQFP package
XIN
FEATURES
Figure 1.
APPLICATIONS
DVD-recordable
All formats
CD-R/W
GENERAL DESCRIPTION
The ADAV801 is a stereo audio codec intended for applications
such as DVD or CD recorders that require high performance
and flexible, cost-effective playback and record functionality.
The ADAV801 features Analog Devices, Inc. proprietary, high
performance converter cores to provide record (ADC), playback
(DAC), and format conversion (SRC) on a single chip. The
ADAV801 record channel features variable input gain to allow
for adjustment of recorded input levels and automatic level
control, followed by a high performance stereo ADC whose
digital output is sent to the record interface. The record channel
also features level detectors that can be used in feedback loops
to adjust input levels for optimum recording. The playback
channel features a high performance stereo DAC with
independent digital volume control.
The sample rate converter (SRC) provides high performance
sample rate conversion to allow inputs and outputs that require
different sample rates to be matched. The SRC input can be
selected from playback, auxiliary, DIR, or ADC (record). The
SRC output can be applied to the playback DAC, both main and
auxiliary record channels, and a DIT.
Operation of the ADAV801 is controlled via an SPI-compatible
serial interface, which allows the programming of individual
control register settings. The ADAV801 operates from a single
analog 3.3 V power supply and a digital power supply of 3.3 V
with an optional digital interface range of 3.0 V to 3.6 V.
The part is housed in a 64-lead LQFP package and is characterized for operation over the commercial temperature range of
−40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.
ADAV801* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
DESIGN RESOURCES
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• ADAV801 Material Declaration
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EVALUATION KITS
• Quality And Reliability
• ADAV801 Evaluation Board
• Symbols and Footprints
DOCUMENTATION
DISCUSSIONS
Application Notes
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• AN-910: Recovering the DIR PLL Operation on the
ADAV801 and ADAV803
SAMPLE AND BUY
Data Sheet
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• ADAV801: Audio Codec for Recordable DVD Data Sheet
SOFTWARE AND SYSTEMS REQUIREMENTS
TECHNICAL SUPPORT
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• Benchmarking Integrated Audio: Why CPU Usage Alone
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ADAV801
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Section................................................................................ 18
Functional Block Diagram .............................................................. 1
Sample Rate Converter (SRC) Functional Overview ............ 19
Applications....................................................................................... 1
PLL Section ................................................................................. 22
General Description ......................................................................... 1
S/PDIF Transmitter and Receiver ............................................ 23
Revision History ............................................................................... 2
Serial Data Ports ......................................................................... 27
Specifications..................................................................................... 3
Interface Control ............................................................................ 30
Test Conditions............................................................................. 3
SPI Interface ................................................................................ 30
ADAV801 Specifications ............................................................. 3
Block Reads and Writes ............................................................. 30
Timing Specifications .................................................................. 7
Register Descriptions ..................................................................... 31
Temperature Range ...................................................................... 7
Layout Considerations................................................................... 58
Absolute Maximum Ratings............................................................ 8
ADC ............................................................................................. 58
ESD Caution.................................................................................. 8
DAC.............................................................................................. 58
Pin Configuration and Function Descriptions............................. 9
PLL ............................................................................................... 58
Typical Performance Characteristics ........................................... 11
Reset and Power-Down Considerations ................................. 58
Functional Description .................................................................. 15
Outline Dimensions ....................................................................... 59
ADC Section ............................................................................... 15
Ordering Guide .......................................................................... 59
REVISION HISTORY
7/07—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to ADC Section............................................................... 15
Changes to Figure 25...................................................................... 15
Changes to Figure 33...................................................................... 21
Changes to SRC Architecture Section ......................................... 21
Changes to Table 7.......................................................................... 22
Changes to Figure 36...................................................................... 22
Changes to Figure 39 and Figure 42............................................. 23
Changes to Transmitter Operation Section ................................ 27
Changes to Interrupts Section ...................................................... 27
Changes to Figure 50...................................................................... 28
Changes to Table 97........................................................................ 46
Changes to Table 101...................................................................... 47
Changes to Table 136 and Table 137 ............................................ 55
Updated Outline Dimensions ....................................................... 59
Changes to Ordering Guide .......................................................... 59
7/04—Revision 0: Initial Version
Rev. A | Page 2 of 60
ADAV801
SPECIFICATIONS
TEST CONDITIONS
Test conditions, unless otherwise noted.
Table 1.
Test Parameter
Supply Voltage
Analog
Digital
Ambient Temperature
Master Clock (MCLKI)
Measurement Bandwidth
Word Width (All Converters)
Load Capacitance on Digital Outputs
ADC Input Frequency
DAC Output Frequency
Digital Input
Digital Output
Condition
3.3 V
3.3 V
25°C
12.288 MHz
20 Hz to 20 kHz
24 bits
100 pF
1007.8125 Hz at −1 dBFS
960.9673 Hz at 0 dBFS
Slave mode, I2S justified format
Slave mode, I2S justified format
ADAV801 SPECIFICATIONS
Table 2.
Parameter
PGA SECTION
Input Impedance
Minimum Gain
Maximum Gain
Gain Step
REFERENCE SECTION
Absolute Voltage, VREF
VREF Temperature Coefficient
ADC SECTION
Number of Channels
Resolution
Dynamic Range
Unweighted
A-Weighted
Min
98
Typ
Max
Unit
4
0
24
0.5
kΩ
dB
dB
dB
1.5
80
V
ppm/°C
2
24
Bits
99
98
102
101
dB
dB
dB
dB
−60 dB input
fS = 48 kHz
fS = 96 kHz
fS = 48 kHz
fS = 96 kHz
Input = −1.0 dBFS
−88
−87
dB
dB
fS = 48 kHz
fS = 96 kHz
1.0
V rms
−0.8
0.05
1
−10
dB
dB
mdB/°C
mV
Total Harmonic Distortion + Noise
Analog Input
Input Range (± Full Scale)
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Offset
−1.5
Comments
Rev. A | Page 3 of 60
ADAV801
Parameter
Crosstalk (EIAJ Method)
Volume Control Step Size (256 Steps)
Maximum Volume Attenuation
Mute Attenuation
Group Delay
fS = 48 kHz
fS = 96 kHz
ADC LOW-PASS DIGITAL DECIMATION FILTER
CHARACTERISTICS1
Pass-Band Frequency
Min
Typ
−110
0.39
−48
∞
Stop-Band Frequency
Stop-Band Attenuation
Pass-Band Ripple
ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS
Cutoff Frequency
SRC SECTION
Resolution
Sample Rate
SRC MCLK
Max
Unit
dB
% per step
dB
dB
μs
μs
22
44
26
52
120
120
±0.01
±0.01
kHz
kHz
kHz
kHz
dB
dB
dB
dB
fS = 48 kHz
fS = 96 kHz
fS = 48 kHz
fS = 96 kHz
fS = 48 kHz
fS = 96 kHz
fS = 48 kHz
fS = 96 kHz
0.9
Hz
fS = 48 kHz
24
8
138 × fS-
192
33
Bits
kHz
MHz
MAX
140
Total Harmonic Distortion + Noise
120
dB
2
24
Bits
99
98
101
100
dB
dB
dB
dB
−91
−90
dB
dB
1.0
60
1.5
V rms
Ω
V
−0.8
0.05
1
dB
dB
mdB/°C
mV
XIN = 27 MHz
fS-MAX is the greater of the input or
output sample rate
1:8
7.75:1
DAC SECTION
Number of Channels
Resolution
Dynamic Range
Unweighted
97
Total Harmonic Distortion + Noise
Analog Outputs
Output Range (± Full Scale)
Output Resistance
Common-Mode Output Voltage
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
DC Offset
ADC outputs all zero codes
910
460
Maximum Sample Rate Ratios
Upsampling
Downsampling
Dynamic Range
A-Weighted
Comments
−2
−30
+30
Rev. A | Page 4 of 60
20 Hz to fS/2, 1 kHz, −60 dBFS input,
fIN = 44.1 kHz, fOUT = 48 kHz
20 Hz to fS/2, 1 kHz, 0 dBFS input,
fIN = 44.1 kHz, fOUT = 48 kHz
20 Hz to 20 kHz, −60 dB input
fS = 48 kHz
fS = 96 kHz
fS = 48 kHz
fS = 96 kHz
Referenced to 1 V rms
fS = 48 kHz
fS = 96 kHz
ADAV801
Parameter
Crosstalk (EIAJ Method)
Phase Deviation
Mute Attenuation
Volume Control Step Size (256 Steps)
Group Delay
48 kHz
96 kHz
192 kHz
DAC LOW-PASS DIGITAL INTERPOLATION FILTER
CHARACTERISTICS
Pass-Band Frequency
Min
Stop-Band Frequency
Stop-Band Attenuation
Pass-Band Ripple
PLL SECTION
Master Clock Input Frequency
Generated System Clocks
MCLKO
SYSCLK1
Typ
−110
0.05
−95.625
0.375
Max
Unit
dB
Degrees
dB
dB
630
155
66
μs
μs
μs
20
22
42
24
26
60
70
70
70
±0.002
±0.002
±0.005
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
27/54
MHz
256
768
MHz
× fS
SYSCLK2
256
768
× fS
SYSCLK3
256
Jitter
SYSCLK1
SYSCLK2
SYSCLK3
DIR SECTION
Input Sample Frequency
Differential Input Voltage
DIT SECTION
Output Sample Frequency
DIGITAL I/O
Input Voltage High, VIH
Input Voltage Low, VIL
Input Leakage, IIH @ VIH = 3.3 V
Input Leakage, IIL @ VIL = 0 V
Output Voltage High, VOH @ IOH = 0.4 mA
Output Voltage Low, VOL @ IOL = −2 mA
Input Capacitance
27/54
512
× fS
65
75
75
ps rms
ps rms
ps rms
27.2
200
200
kHz
mV
27.2
200
kHz
2.0
DVDD
0.8
10
10
V
V
μA
μA
V
V
pF
2.4
0.4
15
Rev. A | Page 5 of 60
Comments
fS = 44.1 kHz
fS = 48 kHz
fS = 96 kHz
fS = 44.1 kHz
fS = 48 kHz
fS = 96 kHz
fS = 44.1 kHz
fS = 48 kHz
fS = 96 kHz
fS = 44.1 kHz
fS = 48 kHz
fS = 96 kHz
256/384/512/768 × 32 kHz/
44.1 kHz/48 kHz
256/384/512/768 × 32 kHz/
44.1 kHz/48 kHz
256/512 × 32 kHz/44.1 kHz/
48 kHz
ADAV801
Parameter
POWER
Supplies
Voltage, AVDD
Voltage, DVDD
Voltage, ODVDD
Operating Current
Analog Current
Digital Current
Digital Interface Current
DIRIN/DIROUT Current
PLL Current
Power-Down Current
Analog Current
Digital Current
Digital Interface Current
DIRIN/DIROUT Current
PLL Current
Power Supply Rejection
Signal at Analog Supply Pins
1
Min
Typ
Max
Unit
3.0
3.0
3.0
3.3
3.3
3.3
3.6
3.6
3.6
V
V
V
60
38
13
mA
mA
mA
mA
mA
Comments
All supplies at 3.3 V
5
18
RESET low, no MCLK
18
2.5
700
3.5
900
mA
mA
μA
mA
μA
−70
−70
dB
dB
Guaranteed by design.
Rev. A | Page 6 of 60
1 kHz, 300 mV p-p
20 kHz, 300 mV p-p
ADAV801
TIMING SPECIFICATIONS
Timing specifications are guaranteed over the full temperature and supply range.
Table 3.
Parameter
MASTER CLOCK AND RESET
MCLKI Frequency
XIN Frequency
RESET Low
SPI PORT
CCLK High
CCLK Low
CIN Setup
CIN Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
SERIAL PORTS 1
Slave Mode
xBCLK High
xBCLK Low
xBCLK Frequency
xLRCLK Setup
xLRCLK Hold
xSDATA Setup
xSDATA Hold
xSDATA Delay
Master Mode
xLRCLK Delay
xSDATA Delay
xSDATA Setup
xSDATA Hold
1
Symbol
fMCLK
fXIN
tRESET
Min
Max
Unit
12.288
27.0
54
54
MHz
MHz
ns
20
tCCH
tCCL
tCIS
tCIH
tCLS
tCLH
tCOE
tCOD
tCOTS
40
40
10
10
10
10
tSBH
tSBL
fSBF
tSLS
tSLH
tSDS
tSDH
tSDD
40
40
64 × fS
10
10
10
10
10
tMLD
tMDD
tMDS
tMDH
Typ
15
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
To CCLK rising edge
From CCLK rising edge
To CCLK rising edge
From CCLK rising edge
From CLATCH falling edge
From CCLK falling edge
From CLATCH rising edge
ns
ns
5
10
10
10
ns
ns
ns
ns
ns
To xBCLK rising edge
From xBCLK rising edge
To xBCLK rising edge
From xBCLK rising edge
From xBCLK falling edge
ns
ns
ns
ns
From xBCLK falling edge
From xBCLK falling edge
From xBCLK rising edge
From xBCLK rising edge
The prefix x refers to I-, O-, IAUX-, or OAUX- for the full pin name.
TEMPERATURE RANGE
Table 4.
Heading
Specifications Guaranteed
Functionality Guaranteed
Storage
Min
Typ
25
−40
−65
Rev. A | Page 7 of 60
Max
+85
+150
Unit
°C
°C
°C
ADAV801
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
DVDD to DGND and ODVDD to
DGND
AVDD to AGND
Digital Inputs
Analog Inputs
AGND to DGND
Reference Voltage
Soldering (10 sec)
Rating
0 V to 4.6 V
0 V to 4.6 V
DGND − 0.3 V to DVDD + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
−0.3 V to +0.3 V
Indefinite short circuit to ground
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 8 of 60
ADAV801
VOUTR
NC
VOUTL
NC
AVDD
AGND
FILTD
AGND
VREF
AGND
AVDD
CAPRN
CAPRP
AGND
CAPLP
CAPLN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VINR 1
VINL 2
48 ADVDD
PIN 1
INDICATOR
47 ADGND
AGND 3
46 PLL_LF2
AVDD 4
45 PLL_LF1
DIR_LF 5
44 PLL_GND
DIR_GND 6
43 PLL_VDD
DIR_VDD 7
42 DGND
ADAV801
RESET 8
41 SYSCLK1
TOP VIEW
(Not to Scale)
CLATCH 9
CIN 10
40 SYSCLK2
39 SYSCLK3
CCLK 11
38 XIN
COUT 12
37 XOUT
ZEROL/INT 13
36 MCLKO
ZEROR 14
35 MCLKI
DVDD 15
34 DVDD
DGND 16
33 DGND
04577-002
IAUXSDATA
IAUXBCLK
IAUXLRCLK
OAUXSDATA
OAUXBCLK
DITOUT
ODGND
ODVDD
DIRIN
OSDATA
OBCLK
OLRCLK
OAUXLRCLK
NC = NO CONNECT
ISDATA
IBCLK
ILRCLK
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 2. ADAV801 Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
VINR
VINL
AGND
AVDD
DIR_LF
DIR_GND
DIR_VDD
RESET
CLATCH
CIN
CCLK
COUT
ZEROL/INT
I/O
I
I
14
15
16
17
18
19
20
21
22
23
24
25
26
ZEROR
DVDD
DGND
ILRCLK
IBCLK
ISDATA
OLRCLK
OBCLK
OSDATA
DIRIN
ODVDD
ODGND
DITOUT
O
I
I
I
I
O
O
I/O
I/O
I
I/O
I/O
O
I
O
Description
Analog Audio Input, Right Channel.
Analog Audio Input, Left Channel.
Analog Ground.
Analog Voltage Supply.
DIR Phase-Locked Loop (PLL) Filter Pin.
Supply Ground for DIR Analog Section. This pin should be connected to AGND.
Supply for DIR Analog Section. This pin should be connected to AVDD.
Asynchronous Reset Input (Active Low).
Chip Select (Control Latch) Pin of SPI-Compatible Control Interface.
Data Input of SPI-Compatible Control Interface.
Clock Input of SPI-Compatible Control Interface.
Data Output of SPI-Compatible Control Interface.
Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined
by the INTRPT bit in DAC Control Register 4.
Right Channel (Output) Zero Flag.
Digital Voltage Supply.
Digital Ground.
Sampling Clock (LRCLK) of Playback Digital Input Port.
Serial Clock (BCLK) of Playback Digital Input Port.
Data Input of Playback Digital Input Port.
Sampling Clock (LRCLK) of Record Digital Output Port.
Serial Clock (BCLK) of Record Digital Output Port.
Data Output of Record Digital Output Port.
Input to Digital Input Receiver (S/PDIF).
Interface Digital Voltage Supply.
Interface Digital Ground.
S/PDIF Output from DIT.
Rev. A | Page 9 of 60
ADAV801
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Mnemonic
OAUXLRCLK
OAUXBCLK
OAUXSDATA
IAUXLRCLK
IAUXBCLK
IAUXSDATA
DGND
DVDD
MCLKI
MCLKO
XOUT
XIN
SYSCLK3
SYSCLK2
SYSCLK1
DGND
PLL_VDD
PLL_GND
PLL_LF1
PLL_LF2
ADGND
ADVDD
VOUTR
NC
VOUTL
NC
AVDD
AGND
FILTD
AGND
VREF
AGND
AVDD
CAPRN
CAPRP
AGND
CAPLP
CAPLN
I/O
I/O
I/O
O
I/O
I/O
I
I
O
I
I
O
O
O
O
O
Description
Sampling Clock (LRCLK) of Auxiliary Digital Output Port.
Serial Clock (BCLK) of Auxiliary Digital Output Port.
Data Output of Auxiliary Digital Output Port.
Sampling Clock (LRCLK) of Auxiliary Digital Input Port.
Serial Clock (BCLK) of Auxiliary Digital Input Port.
Data Input of Auxiliary Digital Input Port.
Digital Ground.
Digital Supply Voltage.
External MCLK Input.
Oscillator Output.
Crystal Input.
Crystal or External MCLK Input.
System Clock 3 (from PLL2).
System Clock 2 (from PLL2).
System Clock 1 (from PLL1).
Digital Ground.
Supply for PLL Analog Section. This pin should be connected to AVDD.
Ground for PLL Analog Section. This pin should be connected to AGND.
Loop Filter for PLL1.
Loop Filter for PLL2.
Analog Ground (Mixed Signal). This pin should be connected to AGND.
Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD.
Right Channel Analog Output.
No Connect.
Left Channel Analog Output.
No Connect.
Analog Voltage Supply.
Analog Ground.
Output DAC Reference Decoupling.
Analog Ground.
Voltage Reference Voltage.
Analog Ground.
Analog Voltage Supply.
ADC Modulator Input Filter Capacitor (Right Channel, Negative).
ADC Modulator Input Filter Capacitor (Right Channel, Positive).
Analog Ground.
ADC Modulator Input Filter Capacitor (Left Channel, Positive).
ADC Modulator Input Filter Capacitor (Left Channel, Negative).
Rev. A | Page 10 of 60
ADAV801
TYPICAL PERFORMANCE CHARACTERISTICS
–50
–100
–150
0
0.5
1.0
1.5
FREQUENCY (Normalized to fS)
–50
–100
–150
2.0
04577-040
MAGNITUDE (dB)
0
04577-037
MAGNITUDE (dB)
0
0
96
192
FREQUENCY (kHz)
288
384
Figure 6. DAC Composite Filter Response, 48 kHz
Figure 3. ADC Composite Filter Response
5
0
0
–10
–15
–20
–30
04577-038
–25
0
5
10
FREQUENCY (Hz)
15
–50
–100
–150
20
04577-041
MAGNITUDE (dB)
MAGNITUDE (dB)
–5
0
Figure 4. ADC High-Pass Filter Response, fS = 48 kHz
12
24
FREQUENCY (kHz)
36
48
Figure 7. DAC Pass-Band Filter Response, 48 kHz
5
0.06
0
0.04
MAGNITUDE (dB)
–10
–15
0.02
0
–0.02
–20
–30
0
5
10
FREQUENCY (Hz)
15
20
–0.06
04577-042
–0.04
–25
04577-039
MAGNITUDE (dB)
–5
0
8
16
FREQUENCY (kHz)
Figure 8. DAC Filter Ripple, 48 kHz
Figure 5. ADC High-Pass Filter Response, fS = 96 kHz
Rev. A | Page 11 of 60
24
ADAV801
0
0
MAGNITUDE (dB)
MAGNITUDE (dB)
–50
–50
–100
–100
0
192
384
FREQUENCY (kHz)
576
–200
768
Figure 9. DAC Composite Filter Response, 96 kHz
04577-046
–150
04577-043
–150
0
384
768
FREQUENCY (kHz)
1152
1536
Figure 12. DAC Composite Filter Response, 192 kHz
0
0
MAGNITUDE (dB)
MAGNITUDE (dB)
–2
–50
–100
–4
–6
0
24
48
FREQUENCY (kHz)
72
04577-047
–150
04577-044
–8
–10
48
96
Figure 10. DAC Pass-Band Filter Response, 96 kHz
64
80
FREQUENCY (kHz)
96
Figure 13. DAC Pass-Band Filter Response, 192 kHz
0.50
0.10
0.40
0.30
0.05
MAGNITUDE (dB)
0
0.10
0.00
–0.10
–0.20
–0.05
0
24
48
FREQUENCY (kHz)
72
96
Figure 11. DAC Filter Ripple, 96 kHz
04577-048
–0.10
–0.30
04577-045
MAGNITUDE (dB)
0.20
–0.40
–0.50
0
8
16
32
FREQUENCY (kHz)
Figure 14. DAC Filter Ripple, 192 kHz
Rev. A | Page 12 of 60
64
ADAV801
0
0
DNR = 102dB
(A-WEIGHTED)
–20
THD+N = 95dB
–20
–40
MAGNITUDE (dB)
–60
–80
–100
–140
–160
–80
–100
–120
04577-0-049
–120
–60
0
2
4
6
8
10
12
14
FREQUENCY (kHz)
16
18
–140
–160
20
04577-052
MAGNITUDE (dB)
–40
0
Figure 15. DAC Dynamic Range, fS = 48 kHz
0
–20
–20
THD+N = 96dB
MAGNITUDE (dB)
20
25
30
FREQUENCY (kHz)
35
40
45 48
DNR = 102dB
(A-Weighted)
–80
–100
–60
–80
–100
–120
04577-0-050
–140
0
2
4
6
8
10
12
14
FREQUENCY (kHz)
16
18
–140
–160
20
04577-053
MAGNITUDE (dB)
–60
–120
0
0
10
FREQUENCY (kHz)
15
0
DNR = 102dB
(A-WEIGHTED)
–20
5
20
Figure 19. ADC Dynamic Range, fS = 48 kHz
Figure 16. DAC THD + N, fS = 48 kHz
THD+N = 92dB
(VIN = –3dB)
–20
–40
–60
–80
–100
–60
–80
–100
–120
–140
–140
04577-051
–120
0
5
10
15
20
25
30
FREQUENCY (kHz)
35
40
45 48
–160
04577-054
MAGNITUDE (dB)
–40
MAGNITUDE (dB)
15
–40
–40
–160
10
Figure 18. DAC THD + N, fS = 96 kHz
0
–160
5
0
5
10
FREQUENCY (kHz)
15
Figure 20. DAC THD + N, fS = 48 kHz
Figure 17. DAC Dynamic Range, fS = 96 kHz
Rev. A | Page 13 of 60
20
ADAV801
0
0
DNR = 102dB
(A-WEIGHTED)
–20
–60
–80
–100
–60
–80
–100
–120
–120
–140
–140
0
8
16
24
32
FREQUENCY (kHz)
40
48
Figure 21. ADC Dynamic Range, fS = 96 kHz
–160
04577-056
MAGNITUDE (dB)
–40
04577-055
MAGNITUDE (dB)
–40
–160
THD+N = 92dB
(VIN = –3dB)
–20
0
8
16
24
32
FREQUENCY (kHz)
Figure 22. ADC THD + N, fS = 96 kHz
Rev. A | Page 14 of 60
40
48
ADAV801
FUNCTIONAL DESCRIPTION
ADC SECTION
Programmable Gain Amplifier (PGA)
The ADAV801’s ADC section is implemented using a secondorder multibit (5 bits) Σ-Δ modulator. The modulator is
sampled at either half of the ADC MCLK rate (modulator clock
= 128 × fS) or one-quarter of the ADC MCLK rate (modulator
clock = 64 × fS). The digital decimator consists of a Sinc^5 filter
followed by a cascade of three half-band FIR filters. The Sinc
decimates by a factor of 16 at 48 kHz and by a factor of 8 at
96 kHz. Each of the half-band filters decimates by a factor of 2.
The input of the record channel features a PGA that converts
the single-ended signal to a differential signal, which is applied
to the analog Σ-Δ modulator of the ADC. The PGA can be
programmed to amplify a signal by up to 24 dB in 0.5 dB
increments. Figure 24 shows the structure of the PGA circuit.
4kΩ TO 64kΩ
XIN
PLL1 INTERNAL
MCLKI
PLL2 INTERNAL
DIR PLL (512 × fS)
DIR PLL (256 × fS)
REG 0x76
BITS[4:2]
CAPxN
125Ω
VREF
EXTERNAL
CAPACITOR
(1nF NPO)
125Ω
8kΩ
8kΩ
EXTERNAL
CAPACITOR
(1nF NPO)
TO
MODULATOR
CAPxP
04577-004
Figure 23 shows the details of the ADC section. By default, the
ADC assumes that the MCLK rate is 256 times the sample rate.
The ADC can be clocked by a number of different clock sources
to control the sample rate. MCLK selection for the ADC is set
by Internal Clocking Control Register 1 (Address 0x76). The
ADC provides an output word of up to 24 bits in resolution in
twos complement format. The output word can be routed to
either the output ports, the sample rate converter, or the S/PDIF
digital transmitter.
ADC MCLK
DIVIDER
EXTERNAL
CAPACITOR
(1nF NPO)
4kΩ
Figure 24. PGA Block Diagram
Analog Σ-Δ Modulator
The ADC features a second-order, multibit, Σ-Δ modulator. The
input features two integrators in cascade followed by a flash
converter. This multibit output is directed to a scrambler,
followed by a DAC for loop feedback. The flash ADC output is
also converted from thermometer coding to binary coding for
input as a 5-bit word to the decimator. Figure 25 shows the
ADC block diagram.
The ADC also features independent digital volume control for
the left and right channels. The volume control consists of
256 linear steps, with each step reducing the digital output
codes by 0.39%. Each channel also has a peak detector that
records the peak level of the input signal. The peak detector
register is cleared by reading it.
REG 0x6F
BITS[1:0]
ADC
MCLK
04577-003
ADC
Figure 23. Clock Path Control on the ADC
HPF
MULTIBIT
Σ-Δ
MODULATOR
AMC
(REG 0x6E
BIT 7)
÷2
÷4
MODULATOR
CLOCK
(6.144MHz MAX)
SINC^5
384kHz
768kHz
VOLUME
CONTROL
HALF-BAND 192kHz
FILTER
384kHz
96kHz
SINC
COMPENSATION 192kHz
HALF-BAND
FILTER
48kHz
96kHz
04577-005
ADC MCLK
DECIMATOR
PEAK
DETECT
Figure 25. ADC Block Diagram
Rev. A | Page 15 of 60
ADAV801
Automatic Level Control (ALC)
No Recovery Mode
The ADC record channel features a programmable automatic
level control block. This block monitors the level of the ADC
output signal and automatically reduces the gain, if the signal at
the input pins causes the ADC output to exceed a preset limit.
This function can be useful to maximize the signal dynamic
range when the input level is not well defined. The PGA can be
used to amplify the unknown signal, and the ALC reduces the
gain until the ADC output is within the preset limits. This
results in maximum front end gain.
By default, there is no gain recovery. Once the gain has been
reduced, it is not recovered until the ALC is reset, either by
toggling the ALCEN bit in ALC Control Register 1 or by
writing any value to ALC Control Register 3. The latter option
is more efficient because it requires only one write operation to
reset the ALC function. No recovery mode prevents volume
modulation of the signal caused by adjusting the gain, which
can create undesirable artifacts in the signal. The gain can be
reduced but not recovered. Therefore, care should be taken that
spurious signals do not interfere with the input signal because
these might trigger a gain reduction unnecessarily.
Because the ALC block monitors the output of the ADC, the
volume control function should not be used. The ADC volume
control scales the results from the ADC, and any distortion
caused by the input signal exceeding the input range of the
ADC is still present at the output of the ADC, but scaled by a
value determined by the volume control register.
The ALC block has two functions, attack mode and recovery
mode. Recovery mode consists of three settings: no recovery,
normal recovery, and limited recovery. These modes are
discussed in the following sections. Figure 26 is a flow diagram
of the ALC block. When the ALC has been enabled, any
changes made to the PGA or ALC settings are ignored. To
change the functionality of the ALC, it must first be disabled.
The settings can then be changed and the ALC re-enabled.
Attack Mode
When the absolute value of the ADC output exceeds the level
set by the attack threshold bits in ALC Control Register 2, attack
mode is initiated. The PGA gain for both channels is reduced by
one step (0.5 dB). The ALC then waits for a time determined by
the attack timer bits before sampling the ADC output value
again. If the ADC output is still above the threshold, the PGA
gain is reduced by a further step. This procedure continues until
the ADC output is below the limit set by the attack threshold
bits. The initial gains of the PGAs are defined by the ADC left
PGA gain register and the ADC right PGA gain register, and
they can have different values. The ALC subtracts a common
gain offset to these values. The ALC preserves any gain difference in dB as defined by these registers. At no time do the PGA
gains exceed their initial values. The initial gain setting,
therefore, also serves as a maximum value.
The limit detection mode bit in ALC Control Register 1 determines how the ALC responds to an ADC output that exceeds
the set limits. If this bit is a 1, both channels must exceed the
threshold before the gain is reduced. This mode can be used to
prevent unnecessary gain reduction due to spurious noise on a
single channel. If the limit detection mode bit is a 0, the gain is
reduced when either channel exceeds the threshold.
Normal Recovery Mode
Normal recovery mode allows for the PGA gain to be recovered,
provided that the input signal meets certain criteria. First, the
ALC must not be in attack mode, that is, the PGA gain has been
reduced sufficiently such that the input signal is below the level
set by the attack threshold bits. Second, the output result from
the ADC must be below the level set by the recovery threshold
bits in the ALC control register. If both of these criteria are met,
the gain is recovered by one step (0.5 dB). The gain is incrementally restored to its original value, assuming that the ADC
output level is below the recovery threshold at intervals
determined by the recovery time bits.
If the ADC output level exceeds the recovery threshold while
the PGA gain is being restored, the PGA gain value is held and
does not continue restoration until the ADC output level is
again below the recovery threshold. Once the PGA gain is
restored to its original value, it is not changed again unless the
ADC output value exceeds the attack threshold and the ALC
then enters attack mode. Care should be taken when using this
mode to choose values for the attack and recovery thresholds
that prevent excessive volume modulation caused by continuous
gain adjustments.
Limited Recovery Mode
Limited recovery mode offers a compromise between no recovery and normal recovery modes. If the output level of the ADC
exceeds the attack threshold, attack mode is initiated. When
attack mode has reduced the PGA gain to suitable levels, the
ALC attempts to recover the gain to its original level. If the
ADC output level exceeds the level set by the recovery threshold
bits, a counter is incremented (GAINCNTR). This counter is
incremented at intervals equal to the recovery time selection, if
the ADC has any excursion above the recovery threshold. If the
counter reaches its maximum value, determined by the
GAINCNTR bits in ALC Control Register 1, the PGA gain is
deemed suitable and no further gain recovery is attempted.
Whenever the ADC output level exceeds the attack threshold,
attack mode is reinitiated and the counter is reset.
Rev. A | Page 16 of 60
ADAV801
Selecting a Sample Rate
selecting the lower modulator rate reduces the amount of digital
noise, improving THD + N, but also reduces the oversampling
ratio, therefore reducing the dynamic range by a corresponding
amount.
The output sample rate of the ADC is always ADC MCLK/256,
as shown in Figure 23. By default, the ADC modulator runs at
ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz,
the ADC modulator should be set to run at ADC MCLK/4. This
is achieved by setting the AMC (ADC Modulator Clock) bit in
the ADC Control Register 1. To compensate for the reduced
modulator clock speed, a different set of filters are used in the
decimator section, ensuring that the sample rate remains
the same.
For best performance of the ADC, avoid using similar frequency
clocks from separate sources in the ADAV801. For example,
running the ADC from a 12.288 MHz clock connected to
MCLKI and using the PLL to generate a separate 12.288 MHz
clock for the DAC can reduce the performance of the ADC.
This is due to the interaction of the clocks, which generate beat
frequencies that can affect the charge on the switch capacitors of
the analog inputs.
The AMC bit can also be used to boost the THD + N performance of the ADC at the expense of dynamic range. The
improvement is typically 0.5 dB to 1.0 dB and works because
ATTACK MODE
WAIT FOR SAMPLE
NO
IS SAMPLE
GREATER THAN ATTACK
THRESHOLD?
NO
IS A RECOVERY
MODE ENABLED?
YES
YES
DECREASE GAIN BY 0.5dB
AND WAIT ATTACK TIME
NORMAL RECOVERY
LIMITED RECOVERY
WAIT FOR SAMPLE
WAIT FOR SAMPLE
IS SAMPLE
ABOVE ATTACK
THRESHOLD?
IS SAMPLE
ABOVE ATTACK
THRESHOLD?
NO
NO
HAS RECOVERY
TIME BEEN
REACHED?
NO
HAS RECOVERY
TIME BEEN
REACHED?
NO
YES
YES
ARE ALL
SAMPLES BELOW
RECOVERY
THRESHOLD?
ARE ALL
SAMPLES BELOW
RECOVERY
THRESHOLD?
NO
NO
YES
YES
INCREASE GAIN BY 0.5dB
INCREASE GAIN BY 0.5dB
WAIT RECOVERY TIME
INCREMENT
GAINCNTR
HAS GAIN BEEN
FULLY RESTORED?
YES
YES
IS GAINCNTR
AT MAXIMUM?
NO
NO
Figure 26. ALC Flow Diagram
Rev. A | Page 17 of 60
HAS GAIN BEEN
FULLY RESTORED?
YES
04577-006
NO
ADAV801
DAC SECTION
Selecting a Sample Rate
The ADAV801 has two DAC channels arranged as a stereo pair
with single-ended analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 128 steps
of 0.375 dB per step. The DAC can receive data from the
playback or auxiliary input ports, the SRC, the ADC, or the
DIR. Each analog output pin sits at a dc level of VREF, and
swings 1.0 V rms for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high frequency noise present on the output pins. Note that the
use of op amps with low slew rate or low bandwidth can cause
high frequency noise and tones to fold down into the audio
band. Care should be taken in selecting these components.
Correct operation of the DAC is dependent upon the data rate
provided to the DAC, the master clock applied to the DAC, and
the selected interpolation rate. By default, the DAC assumes
that the MCLK rate is 256 times the sample rate, which requires
an 8× oversampling rate. This combination is suitable for
sample rates of up to 48 kHz.
XIN
MCLKI
PLL1 INTERNAL
PLL2 INTERNAL
DIR PLL (512 × fS)
DIR PLL (256 × fS)
The FILTD and VREF pins should be bypassed by external
capacitors to AGND. The FILTD pin is used to reduce the noise
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the VREF pin can be used to bias
external op amps used to filter the output signals. For
applications in which the VREF is required to drive external
op amps, which might draw more than 50 μA or have dynamic
load changes, extra buffering should be used to preserve the
quality of the ADAV801 reference.
For a 96 kHz data rate that has a 24.576 MHz MCLK (256 × fS)
associated with it, the DAC MCLK divider should be set to
divide the MCLK by 2. This prevents the DAC engine from
running too fast. To compensate for the reduced MCLK rate,
the interpolator should be selected to operate in 4 × (DAC
MCLK = 128 × fS). Similar combinations can be selected for
different sample rates.
REG 0x76
BITS[7:5]
TO CONTROL
REGISTERS
REG 0x65
BITS[3:2]
DAC
MCLK
DAC
AUXILIARY IN
PLAYBACK
DAC
INPUT
DIR
ADC
REG 0x63
BITS[5:3]
Figure 27. Clock and Datapath Control on the DAC
PEAK
DETECTOR
DAC
MULTIBIT
Σ-Δ
MODULATOR
ANALOG
OUTPUT
INTERPOLATOR
VOLUME/MUTE
CONTROL
TO ZERO FLAG PINS
ZERO DETECT
FROM DAC
DATAPATH
MULTIPLEXER
Figure 28. DAC Block Diagram
04577-008
DAC
Rev. A | Page 18 of 60
04577-007
MCLK
DIVIDER
The digital input data source for the DAC can be selected from
a number of available sources by programming the appropriate
bits in the datapath control register. Figure 27 shows how the
digital data source and the MCLK source for the DAC are
selected. Each DAC has an independent volume register giving
256 steps of control, with each step giving approximately
0.375 dB of attenuation. Note that the DACs are muted by
default to prevent unwanted pops, clicks, and other noises
from appearing on the outputs while the ADAV801 is being
configured. Each DAC also has a peak-level register that records
the peak value of the digital audio data. Reading the register
clears the peak.
ADAV801
The frequency domain shows the wide side lobes that result
from this error when the sampling of fS_OUT is convolved with
the attenuated images from the sin(x)/x nature of the zero-order
hold. The images at fS_IN (dc signal images) of the zero-order
hold are infinitely attenuated. Because the ratio of T2 to T1 is an
irrational number, the error resulting from the resampling at
fS_OUT can never be eliminated. The error can be significantly
reduced, however, through interpolation of the input data at
fS_IN. Therefore, the sample rate converter in the ADAV801 is
conceptually interpolated by a factor of 220.
ZERO-ORDER
HOLD
fS_IN = 1/T1
OUT
fS_OUT = 1/T2
ORIGINAL SIGNAL
fS_OUT
TIME DOMAIN OF fS_OUT RESAMPLING
TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT
Figure 30. SRC Time Domain
In the frequency domain shown in Figure 31, the interpolation
expands the frequency axis of the zero-order hold. The images
from the interpolation can be sufficiently attenuated by a good
low-pass filter. The images from the zero-order hold are now
pushed by a factor of 220 closer to the infinite attenuation point
of the zero-order hold, which is fS_IN × 220. The images at the
zero-order hold are the determining factor for the fidelity of the
output at fS_OUT.
SIN(X)/X OF ZERO-ORDER HOLD
INTERPOLATE
BY N
LOW-PASS
FILTER
ZERO-ORDER
HOLD
fS_IN
SPECTRUM OF ZERO-ORDER HOLD OUTPUT
04577-009
OUT
fS_OUT
FREQUENCY DOMAIN OF SAMPLES AT fS_IN
SPECTRUM OF fS_OUT SAMPLING
2 × fS_OUT
OUT
TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER
IN
fS_OUT
ZERO-ORDER
HOLD
TIME DOMAIN OF fS_IN SAMPLES
SAMPLED AT fS_IN
FREQUENCY RESPONSE OF fS_OUT CONVOLVED
WITH ZERO-ORDER HOLD SPECTRUM
LOW-PASS
FILTER
fS_IN
During asynchronous sample rate conversion, data can be
converted at the same sample rate or at different sample rates.
The simplest approach to an asynchronous sample rate
conversion is to use a zero-order hold between the two
samplers, as shown in Figure 29. In an asynchronous system, T2
is never equal to T1, nor is the ratio between T2 and T1
rational. As a result, samples at fS_OUT are repeated or dropped,
producing an error in the resampling process.
IN
INTERPOLATE
BY N
IN
04577-010
SAMPLE RATE CONVERTER (SRC) FUNCTIONAL
OVERVIEW
FREQUENCY DOMAIN OF THE INTERPOLATION
fS_IN
220 × fS_IN
Figure 29. Zero-Order Hold Used by fS_ OUT to Resample Data from fS_IN
Conceptual High Interpolation Model
Rev. A | Page 19 of 60
SIN(X)/X OF ZERO-ORDER HOLD
FREQUENCY DOMAIN OF fS_OUT RESAMPLING
FREQUENCY DOMAIN
AFTER RESAMPLING
220 × fS_IN
220 × fS_IN
Figure 31. Frequency Domain of the Interpolation and Resampling
04577-011
Interpolation of the input data by a factor of 220 involves placing
(220 − 1) samples between each fS_IN sample. Figure 30 shows
both the time domain and the frequency domain of interpolation
by a factor of 220. Conceptually, interpolation by 220 involves the
steps of zero-stuffing (220 − 1) number of samples between each
fS_IN sample and convolving this interpolated signal with a
digital low-pass filter to suppress the images. In the time
domain, it can be seen that fS_OUT selects the closest fS_IN × 220
sample from the zero-order hold, as opposed to the nearest fS_IN
sample in the case of no interpolation. This significantly
reduces the resampling error.
ADAV801
The worst-case images can be computed from the zero-order
hold frequency response:
Maximum Image = sin(π × F/fS_INTERP)/(π × F/fS_INTERP)
This technique is supported by the Fourier transform property
that, if f(t) is F(ω), then f(k × t) is F(ω/k). Thus, the range of
decimation is limited by the size of the RAM.
SRC Architecture
The following worst-case images would appear for fS_IN equal to
192 kHz:
Image at fS_INTERP − 96 kHz = −125.1 dB
Image at fS_INTERP + 96 kHz = −125.1 dB
Hardware Model
The output rate of the low-pass filter in Figure 30 is the
interpolation rate:
220 × 192,000 kHz = 201.3 GHz
The architecture of the sample rate converter is shown in
Figure 32. The sample rate converter’s FIFO block adjusts the
left and right input samples and stores them for the FIR filter’s
convolution cycle. The fS_IN counter provides the write address
to the FIFO block and the ramp input to the digital servo loop.
The ROM stores the coefficients for the FIR filter convolution
and performs a high order interpolation between the stored
coefficients. The sample rate ratio block measures the sample
rate for dynamically altering the ROM coefficients and scaling
of the FIR filter length as well as the input data. The digital
servo loop automatically tracks the fS_IN and fS_OUT sample rates
and provides the RAM and ROM start addresses for the start of
the FIR filter convolution.
RIGHT DATA IN
LEFT DATA IN
Sampling at a rate of 201.3 GHz is clearly impractical, in
addition to the number of taps required to calculate each
interpolated sample. However, because interpolation by 220
involves zero-stuffing 220 − 1 samples between each fS_IN sample,
most of the multiplies in the low-pass FIR filter are by zero. A
further reduction can be realized because only one interpolated
sample is taken at the output at the fS_OUT rate, so only one
convolution needs to be performed per fS_OUT period instead of
220 convolutions. A 64-tap FIR filter for each fS_OUT sample is
sufficient to suppress the images caused by the interpolation.
One difficulty with the preceding approach is that the correct
interpolated sample must be selected upon the arrival of fS_OUT.
Because there are 220 possible convolutions per fS_OUT period, the
arrival of the fS_OUT clock must be measured with an accuracy of
1/201.3 GHz = 4.96 ps. Measuring the fS_OUT period with a clock
of 201.3 GHz frequency is clearly impossible; instead, several
coarse measurements of the fS_OUT clock period are made and
averaged over time.
Another difficulty with the preceding approach is the number
of coefficients required. Because there are 220 possible convolutions with a 64-tap FIR filter, there must be 220 polyphase
coefficients for each tap, which requires a total of 226 coefficients. To reduce the number of coefficients in ROM, the SRC
stores a small subset of coefficients and performs a high order
interpolation between the stored coefficients.
The preceding approach works when fS_OUT > fS_IN. However,
when the output sample rate, fS_OUT, is less than the input sample
rate, fS_IN, the ROM starting address, input data, and length of
the convolution must be scaled. As the input sample rate rises
over the output sample rate, the antialiasing filter’s cutoff
frequency must be lowered because the Nyquist frequency of
the output samples is less than the Nyquist frequency of the
input samples. To move the cutoff frequency of the antialiasing
filter, the coefficients are dynamically altered and the length of
the convolution is increased by a factor of (fS_IN/fS_OUT).
FIFO
ROM A
HIGH
ORDER
INTERP
ROM B
ROM C
ROM D
fS_IN
COUNTER
DIGITAL
SERVO LOOP
SAMPLE RATE RATIO
FIR FILTER
L/R DATA OUT
fS_IN
fS_OUT
SAMPLE
RATE RATIO
EXTERNAL
RATIO
04577-012
where:
F is the frequency of the worst-case image that would be
220 × fS_IN ± fS_IN/2.
fS_INTERP = fS_IN × 220.
Figure 32. Architecture of the Sample Rate Converter
The FIFO receives the left and right input data and adjusts the
amplitude of the data for both the soft muting of the sample rate
converter and the scaling of the input data by the sample rate
ratio before storing the samples in the RAM. The input data is
scaled by the sample rate ratio because, as the FIR filter length
of the convolution increases, so does the amplitude of the
convolution output. To keep the output of the FIR filter from
saturating, the input data is scaled down by multiplying it by
(fS_OUT/fS_IN) when fS_OUT < fS_IN. The FIFO also scales the input
data for muting and unmuting of the SRC.
The RAM in the FIFO is 512 words deep for both left and right
channels. An offset to the write address provided by the fS_IN
counter is added to prevent the RAM read pointer from
overlapping the write address. The minimum offset on the SRC
is 16 samples. However, the group delay and mute-in register
can be used to increase this offset.
The number of input samples added to the write pointer of the
FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay
register. This feature is useful in varispeed applications to
prevent the read pointer to the FIFO from running ahead of the
write pointer. When set, Bit 7 of the group delay and mute-in
register soft-mutes the sample rate. Increasing the offset of the
Rev. A | Page 20 of 60
ADAV801
write address pointer is useful for applications in which small
changes in the sample rate ratio between fS_IN and fS_OUT are
expected. The maximum decimation rate can be calculated
from the RAM word depth and the group delay as
(512 − 16)/64 taps = 7.75
for short group delay and
(512 − 64)/64 taps = 7
for long group delay.
FAST MODE
–40
MAGNITUDE (dB)
MCLKI
XIN
PLLINT2
PLLINT1
0
–20
SLOW MODE
–80
–100
–120
–140
–160
–180
–220
0.01
REG 0x00
BITS[1:0]
SRC
MCLK
SRC
OUTPUT
AUXILIARY IN
PLAYBACK
SRC
INPUT
1
10
100
FREQUENCY (Hz)
1k
10k
100k
Figure 34. Frequency Response of the Digital Servo Loop;
fS_IN is the X-Axis, fS_OUT = 192 kHz, Master Clock is 30 MHz
DIR
ADC
REG 0x62
BITS[7:6]
04577-013
SRC
0.1
04577-014
–200
ICLK1
DIR PLL (256 × fS)
MCLKI
The frequency responses of the digital servo loop for fast mode
and slow mode are shown in Figure 34. The FIR filter is a 64-tap
filter when fS_OUT ≥ fS_IN and is (fS_IN/fS_OUT) × 64 taps when fS_IN >
fS_OUT. The FIR filter performs its convolution by loading in the
starting address of the RAM address pointer and the ROM
address pointer from the digital servo loop at the start of the
fS_OUT period. The FIR filter then steps through the RAM by
decrementing its address by 1 for each tap, and the ROM
pointer increments its address by the (fS_OUT/fS_IN) × 220 ratio for
fS_IN > fS_OUT or 220 for fS_OUT ≥ fS_IN. Once the ROM address rolls
over, the convolution is completed.
–60
REG 0x77
BIT[4:3]
ICLK2
REG 0x76
BIT[1:0]
DIR PLL (512 × fS)
XIN
PLLINT2
PLLINT1
The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is the integer output
of the ramp filter, and the ROM is the fractional part. The
digital servo loop must provide excellent rejection of jitter on
the fS_IN and fS_OUT clocks, as well as measure the arrival of the
fS_OUT clock within 4.97 ps. The digital servo loop also divides
the fractional part of the ramp output by the ratio of fS_IN/fS_OUT
to dynamically alter the ROM coefficients when fS_IN > fS_OUT.
Delay and Mute register until the SRC has changed to slow
mode. The MUTE_IND bit can be set to generate an interrupt
when the SRC changes to slow mode, indicating that the data is
being sample rate converted accurately.
Figure 33. Clock and Datapath Control on the SRC
The digital servo loop is implemented with a multirate filter. To
settle the digital servo loop filter more quickly upon startup or a
change in the sample rate, a fast mode has been added to the
filter. When the digital servo loop starts up or the sample rate is
changed, the digital servo loop enters fast mode to adjust and
settle on the new sample rate. Upon sensing that the digital
servo loop is settling down to a reasonable value, the digital
servo loop returns to normal (or slow) mode.
During fast mode, the MUTE_IND bit in the Sample Rate
Converter Error register is asserted to let the user know that
clicks or pops might be present in the digital audio data. The
output of the SRC can be muted by asserting Bit 7 of the Group
The convolution is performed for both the left and right
channels, and the multiply accumulate circuit used for the
convolution is shared between the channels. The fS_IN/fS_OUT
sample rate ratio circuit is used to dynamically alter the
coefficients in the ROM when fS_IN > fS_OUT. The ratio is
calculated by comparing the output of an fS_OUT counter to the
output of an fS_IN counter. If fS_OUT > fS_IN, the ratio is held at one.
If fS_IN > fS_OUT, the sample rate ratio is updated, if it is different
by more than two fS_OUT periods from the previous fS_OUT to fS_IN
comparison. This is done to provide some hysteresis to prevent
the filter length from oscillating and causing distortion.
Figure 33 shows the detail of the SRC section. The SRC master
clock is expected to be equal to 256 times the output sample
rate. This master clock can be provided by four different clock
sources. The selection is set by the SRC and Clock Control
register (Address 0x00), and the selected clock source can be
divided using the same register.
Rev. A | Page 21 of 60
ADAV801
Table 7. PLL Frequency Selection Options
The ADAV801 features a dual PLL configuration to generate
independent system clocks for asynchronous operation.
Figure 37 shows the block diagram of the PLL section. The PLL
generates the internal and system clocks from a 27 MHz clock.
This clock is generated either by a crystal connected between
XIN and XOUT, as shown in Figure 35, or from an external
clock source connected directly to XIN. A 54 MHz clock can
also be used, if the internal clock divider is used.
XTAL
C
04577-015
XOUT
XIN
C
Figure 35. Crystal Connection
Both PLLs (PLL1 and PLL2) can be programmed independently
and can accommodate a range of sampling rates (32 kHz/
44.1 kHz/48 kHz) with selectable system clock oversampling
rates of 256 and 384. Higher oversampling rates can also be
selected by enabling the doubling of the sampling rate to give
512 or 768 × fS ratios. Note that this option also allows
oversampling ratios of 256 or 384 at double sample rates of
64 kHz/88.2 kHz/96 kHz.
PLL
1
2A
2B
Sample Rate, fS
(kHz)
32/44.1/48
64/88.2/96
32/44.1/48
64/88.2/96
Same as fS selected
for PLL2A
MCLK Selection
Normal fS
Double fS
256/384 × fS
512/768 × fS
256/384 × fS
256/384 × fS
512/768 × fS
256/384 × fS
256/512 × fS
The PLLs require some external components to operate
correctly. These components, shown in Figure 36, form a loop
filter that integrates the current pulses from a charge pump and
produces a voltage that is used to tune the VCO. Good quality
capacitors, such as PPS film, are recommended. Figure 37
shows a block diagram of the PLL section, including the master
clock selection. Figure 38 shows how the clock frequencies at
the clock output pins, SYSCLK1 to SYSCLK3, and the internal
PLL clock values, PLL1 and PLL2, are selected.
The clock nodes, PLL1 and PLL2, can be used as master clocks
for the other blocks in the ADAV801, such as the DAC or ADC.
The PLL has separate supply and ground pins, which should be
as clean as possible to prevent electrical noise from being
converted into clock jitter by coupling onto the loop filter pins.
AVDD
The PLL outputs can be routed internally to act as clock sources
for the other component blocks such as the ADC and DAC. The
outputs of the PLLs are also available on the three SYSCLK pins.
Figure 38 shows how the PLLs can be configured to provide the
sampling clocks.
732Ω
10nF
PLL BLOCK
1.2µF
04577-016
PLL SECTION
PLL_LFx
Figure 36. PLL Loop Filter
PLL_LF1
REG 0x78
BIT 6
÷2
XOUT
MCLKO
REG 0x74
BIT 5
REG 0x74
BIT 4
VCO
OUTPUT
SCALER N1
SYSCLK1
PLL1
÷N
÷2
MCLKI
PHASE
DETECTOR
AND LOOP
FILTER
REG 0x78
BIT 7
PHASE
DETECTOR
AND LOOP
FILTER
VCO
SYSCLK2
PLL2
÷N
PLL_LF2
Figure 37. PLL Section Block Diagram
Rev. A | Page 22 of 60
OUTPUT
SCALER N2
OUTPUT
SCALER N3
SYSCLK3
04577-017
XIN
ADAV801
PLL1 MCLK
PLL2 MCLK
256
384
256
384
48kHz
32kHz
44.1kHz
256
512
REG 0x75
BITS[3:2]
PLL1
REG 0x75
BIT 0
×2
FS1
SYSCLK1
REG 0x77
BIT 0
REG 0x75
BIT 1
÷2
PLLINT1
PLL2
REG 0x75
BIT 4
REG 0x75
BIT 5
×2
FS2
SYSCLK2
REG 0x77
BITS[2:1]
REG 0x75
BITS[7:6]
÷2
REG 0x74
BIT 0
FS3
PLLINT2
÷2
SYSCLK3
04577-018
48kHz
32kHz
44.1kHz
Figure 38. PLL Clocking Scheme
S/PDIF TRANSMITTER AND RECEIVER
CHANNEL STATUS
AND USER BITS
The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts
the S/PDIF input data stream. The DIRIN pin can be configured
to accept a digital input level, as defined in the Specifications
section, or an input signal with a peak-to-peak level of 200 mV
minimum, as defined by the IEC 60958-3 specification. DIR_LF
is a loop filter pin, required by the internal PLL, which is used
to recover the clock from the S/PDIF data stream.
The components shown in Figure 42 form a loop filter, which
integrates the current pulses from a charge pump and produces
a voltage that is used to tune the VCO of the clock recovery
PLL. The recovered audio data and audio clock can be routed to
the different blocks of the ADAV801, as required. Figure 39
shows a conceptual diagram of the DIRIN block.
DIT
DIR
DIT
INPUT
PLAYBACK
DITOUT
AUXILIARY IN
04577-020
SRC
REG 0x63
BITS[2:0]
Figure 40. Digital Output Transmitter Block Diagram
AUDIO
DATA
DIRIN
RECOVERED
CLOCK
DIR
CHANNEL STATUS/
USER BITS
Figure 41. Digital Input Receiver Block Diagram
AVDD
3.3kΩ
6.8nF
100nF
DIR_LF
DIRIN
S/PDIF
SPDIF
RECEIVER
COMPARATOR
*EXTERNAL CAPACITOR IS REQUIRED ONLY
FOR VARIABLE LEVEL SPDIF INPUTS.
04577-019
DC
LEVEL
Figure 42. DIR Loop Filter Components
Figure 39. DIRIN Block
Rev. A | Page 23 of 60
04577-022
DIR BLOCK
REG 0x7A
BIT 4
C*
ADC
04577-021
The ADAV801 contains an integrated S/PDIF transmitter and
receiver. The transmitter consists of a single output pin,
DITOUT, on which the biphase encoded data appears. The
S/PDIF transmitter source can be selected from the different
blocks making up the ADAV801. Additionally, the clock source
for the S/PDIF transmitter can be selected from the various
clock sources available in the ADAV801.
ADAV801
Serial Digital Audio Transmission Standards
The ADAV801 can receive and transmit S/PDIF, AES/EBU, and
IEC-958 serial streams. S/PDIF is a consumer audio standard,
and AES/EBU is a professional audio standard. IEC-958 has
both consumer and professional definitions. This data sheet is
not intended to fully define or to provide a tutorial for these
standards. Contact the international standards-setting bodies
for the full specifications.
CLOCK
(2 TIMES BIT RATE)
0
1
1
1
0
0
DATA
04577-023
BIPHASE-MARK
DATA
Figure 43. Biphase-Mark Encoding
Digital audio-communication schemes use preambles to
distinguish among channels (called subframes) and among
longer-term control information blocks (called frames). Preambles are particular biphase-mark patterns, which contain encoding
violations that allow the receiver to uniquely recognize them.
These patterns and their relationship to frames and subframes
are shown in Table 8 and Figure 44.
Biphase Patterns
11100010 or 00011101
11100100 or 00011011
11101000 or 00010111
Channel
Left
Right
Left and CS block start
X LEFT CH Y RIGHT CH Z LEFT CH Y RIGHT CH X LEFT CH Y RIGHT CH
FRAME 191
FRAME 0
FRAME 1
0
0
1
0
1
1
1
0
0
1
0
0
1
1
1
0
1
0
0
0
PREAMBLE Z
Figure 45. Preambles
The serial digital audio communication scheme is organized
using a frame and subframe construction. There are two
subframes per frame (ordinarily the left and right channel).
Each subframe includes the appropriate 4-bit preamble, up to
24 bits of audio data, a validity (V) bit, a user (U) bit, a channel
status (C) bit, and an even parity (P) bit. The channel status bits
and the user bits accumulate over many frames to convey
control information. The channel status bits accumulate over a
192 frame period (called a channel status block). The user bits
accumulate over 1176 frames when the interconnect is implementing the so-called subcode scheme (EIAJ CP-2401). The
organization of the channel status block, frames, and subframes
is shown in Table 9 and Table 10. Note that the ADAV801
supports the professional audio standard from a software
point of view only. The digital interface supports only
consumer mode.
Table 9. Consumer Audio Standard
Data Bits
4
3
2
Emphasis
Copyright
Address 1
N
7
6
Channel
Status
N+1
N+2
N+3
Category Code
Channel Number
Source Number
Reserved
Sampling Frequency
Clock
Accuracy
Reserved
Word Length
Reserved
1
SUBFRAME
04577-024
SUBFRAME
0
PREAMBLE Y
N+4
N + 5 to
(N + 23)
PREAMBLES
1
PREAMBLE X
Table 8. Biphase-Mark Encode Preamble
X
Y
Z
1
04577-025
All these digital audio communication schemes encode audio
data and audio control information using the biphase-mark
method. This encoding method minimizes the dc content of the
transmitted signal. As can be seen from Figure 43, 1s in the
original data end up with midcell transitions in the biphasemark encoded data, while 0s in the original data do not. Note
that the biphase-mark encoded data always has a transition
between bit boundaries.
1
5
N = 0x20 for receiver channel status buffer.
N = 0x38 for transmitter channel status buffer.
Figure 44. Preambles, Frames, and Subframes
The biphase-mark encoding violations are shown in Figure 45.
Note that all three preambles include encoding violations.
Ordinarily, the biphase-mark encoding method results in a
polarity transition between bit boundaries.
Rev. A | Page 24 of 60
1
NonAudio
0
Pro/
Con
=0
ADAV801
Address1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
6
5
Lock
4
Data Bits
3 2
Emphasis
1
0
Sample
NonPro/Con
Frequency
Audio = 1
User Bit Management
Channel Mode
Alignment
Source Word
Use of Auxiliary Mode
Level
Length
Sample Bits
Channel Identification
Reserved Digital Audio
fS
Sample
Scaling
Frequency (fS)
Reference
Signal
Reserved
Alphanumeric Channel Origin Data—First Character
Alphanumeric Channel Origin Data
Alphanumeric Channel Origin Data
Alphanumeric Channel Origin Data—Last Character
Alphanumeric Channel Destination Data—First Character
Alphanumeric Channel Destination Data
Alphanumeric Channel Destination Data
Alphanumeric Channel Destination Data—Last Character
Local Sample Address Code—LSW
Local Sample Address Code
Local Sample Address Code
Local Sample Address Code—MSW
Time of Day Code—LSW
Time of Day Code
Time of Day Code
Time of Day Code—MSW
Reliability Flags
Reserved
Cyclic Redundancy Check Character (CRCC)
CHANNEL
STATUS A
(24 × 8 BITS)
DIRIN
CHANNEL
STATUS B
(24 × 8 BITS)
S/PDIF
RECEIVE
BUFFER
SECOND BUFFER
RECEIVE
CS BUFFER
(0x20 TO 0x37)
RxCSSWITCH
FIRST BUFFER
Figure 46. Channel Status Buffer
S/PDIF
0...7
0...7
8...15
8...15
16...23
16...23
ADDRESS = 0x50
RECEIVER USER BIT
INDIRECT ADDRESS
REGISTER
FIRST
BUFFER
USER-BIT
BUFFER
ADDRESS = 0x51
RECEIVER USER BIT
DATA REGISTER
N = 0x20 for receiver channel status buffer.
N = 0x38 for transmitter channel status buffer.
04577-027
1
7
bits are available as a memory buffer, taking up 24 consecutive
register locations. The user bits are read using an indirect
memory addressing scheme, where the receiver user bit
indirect-address register is programmed with an offset to the
user bit buffer, and the receiver user bit data register can be read
to determine the user bits at that location. Reading the receiver
user bit data register automatically updates the indirect address
register to the next location in the buffer. Typically, the receiver
user bit indirect-address register is programmed to zero (the
start of the buffer), and the receiver user bit data register is read
repeatedly until all the buffer’s data has been read. Figure 46
and Figure 47 show how receiving the channel status bits and
user bits is implemented.
04577-026
Table 10. Professional Audio Standard
The standards allow the channel status bits in each subframe to
be independent, but ordinarily the channel status bits in the two
subframes of each frame are the same. The channel status bits
are defined differently for the consumer audio standards and
the professional audio standards. The 192 channel status bits are
organized into 24 bytes and have the interpretations shown in
Table 9 and Table 10.
The S/PDIF transmitter and receiver have a comprehensive
register set. The registers give the user full access to the
functions of the S/PDIF block, such as detecting nonaudio and
validity bits, Q subcodes, and preambles. The channel status bits
as defined by the IEC60958 and AES3 specifications are stored
in register buffers for ease of use. An autobuffering function
allows channel status bits and user bits read by the receiver to be
copied directly to the transmitter block, removing the need for
user intervention.
Receiver Section
The ADAV801 uses a double-buffering scheme to handle reading channel status and user bit information. The channel status
Figure 47. Receiver User Bit Buffer
The S/PDIF receive buffer is updated continuously by the
incoming S/PDIF stream. Once all the channel status bits for
the block (192 for Channel A and 192 for Channel B) are
received, the bits are copied into the receiver channel status
buffer. This buffer stores all 384 bits of channel status
information, and the RxCSSWITCH bit in the channel status
switch buffer register determines whether the Channel A or the
Channel B status bits are required to be read. The receive
channel status bit buffer is 24 bytes long and spans the address
range from 0x20 to 0x37.
Because the channel status bits of an S/PDIF stream rarely
change, a software interrupt/flag bit, RxCSBINT, is provided to
notify the host control either that a new block of channel status
bits is available or that the first five bytes of channel status
information have changed from a previous block. The function
of the RxCSBINT is controlled by the RxBCONF3 bit in the
Receiver Buffer Configuration register.
Rev. A | Page 25 of 60
ADAV801
The size of the user bit buffer can be set by programming the
RxBCONF0 bit in the receiver buffer configuration register, as
shown in Table 11.
the CRC check of the Q subcode, the QCRCERROR bit is set.
This is a sticky bit that remains high until the register is read.
Table 11. RxBCONF3 Functionality
The S/PDIF transmitter has a similar buffer structure to the
receive section. The transmitter channel status buffer occupies
24 bytes of the register map. This buffer is long enough to store
the 192 bits required for one channel of channel status information. Setting the TxCSSWITCH bit determines if the data
loaded to the transmitter channel status buffer is intended for
Channel A or Channel B. In most cases, the channel status bits
for Channel A and Channel B are the same, in which case
setting the Tx_A/B_Same bit reads the data from the transmitter channel status buffer and transmits it on both channels.
Receiver User Bit Buffer Size
384 bits with Preamble Z as the start of the block.
768 bits with Preamble Z as the start of the block.
The updating of the user bit buffer is controlled by Bits
RxBCONF[2:1] and Bit 7 to Bit 4 of the channel status register,
as shown in Table 12 and Table 13.
Table 12. RxBCONF[2:1] Functionality
RxBCONF
Bit 2
Bit 1
0
0
0
1
1
0
Receiver User Bit Buffer Configuration
User bits are ignored.
Update second buffer when first buffer is full.
Format according to Byte 1, Bit 4 to Bit 7, if
PRO bit is set. Format according to IEC60958-3,
if PRO bit is clear.
Table 13. Automatic User Bit Configuration
7
0
0
Bits
6 5
0 0
1 0
4
0
0
1
0
0
1
1
0
0
0
Automatic Receiver User Bit Buffer
Configuration
User bits are ignored.
AES-18 format: the user bit buffer is treated in
the same way as when RxBCONF[2:1] = 0b01.
User bit buffer is updated in the same way as
when RxBCONF[2:1] = 0b01 and RxBCONF0 =
0b00.
User-defined format: the user bit buffer is
treated in the same way as when
RxBCONF[2:1] = 0b01.
Because the channel status information is rarely changed during
transmission, the information contained in the buffer is transmitted repeatedly. The Disable_Tx_Copy bit can be used to
prevent the channel status bits from being copied from the
transmitter CS buffer into the S/PDIF transmitter buffer until
the user has finished loading the buffers. This feature is
typically used, if the Channel A data and Channel B data are
different. Setting the bit prevents the data from being copied.
Clearing the bit allows the data to be copied and then
transmitted. Figure 48 shows how the buffers are organized.
DITOUT
TRANSMIT
CS BUFFER
(0x38 TO 0x4F)
TxCSSWITCH
CHANNEL
STATUS A
(24 × 8 BITS)
CHANNEL
STATUS B
(24 × 8 BITS)
S/PDIF
TRANSMIT
BUFFER
04577-028
RxBCONF0
0
1
Transmitter Operation
Figure 48. Transmitter Channel Status Buffer
When the user bit buffer has been filled, the RxUBINT
interrupt bit in the interrupt status register is set, provided that
the RxUBINT mask bit is set, to indicate that the buffer has new
information and can be read.
For the special case when the user data is formatted according
to the IEC 60958-3 standard into messages made of information
units, called IUs, the zeros stuffed between each IU and each
message are removed and only the IUs are stored. Once the end
of the message is sensed by more that eight zeros between IUs,
the user bit buffer is updated with the complete message and
the first buffer begins looking for the start of the next message.
Each IU is stored as a byte consisting of 1, Q, R, S, T, U, V, and
W bits (see the IEC 60958-3 specification for more information).
When 96 IUs are received, the Q subcode of the IUs is stored in
the Q subcode buffer, consisting of 10 bytes. The Q subcode is
the Q bits taken from each of the 96 IUs. The first 10 bytes
(80 bits) of the Q subcode contain information sent by CD, MD,
and DAT systems. The last 16 bits of the Q subcode are used to
perform a CRC check of the Q subcode. If an error occurs in
As with the receiver section, the transmitted user bits are also
double-buffered. This is required because, unlike the channel
status bits, the user bits do not necessarily repeat themselves.
The user bits can be buffered in various configurations, as listed
in Table 14. Transmission of the user bits is determined by the
state of the BCONF3 bit. If the bit is 0, the user bits begin
transmitting right away without alignment to the Z preamble. If
this bit is 1, the user bits do not start transmitting until a
Z preamble occurs when the TxBCONF[2:1] bits are 01.
Table 14. Transmitter User Bit Buffer Configurations
TxBCONF[2:1]
Bit 2
Bit 1
0
0
0
1
1
0
1
Rev. A | Page 26 of 60
1
Transmitter User Bit Buffer Configuration
Zeros are transmitted for the user bits.
Host writes user bits to the buffer until it is full.
Writes the user bits to the buffer in IUs
specified by IEC60958-3 and transmits them
according to the standard.
First 10 bytes of the user-bit buffer are
configured to store a Q subcode.
ADAV801
Table 15. Transmitter User Bit Buffer Size
TxBCONF0
0
1
Buffer Size
384 bits with Preamble Z as the start of the block.
768 bits with Preamble Z as the start of the block.
By using sticky bits and interrupts, the transmit buffers can
notify the host or microcontroller about their status. The sticky
bit, TxUBINT, is set when the transmit user bit buffer has been
updated and the second transmit user bit buffer is empty and
ready to accept new user bits. This bit is located in the interrupt
status register. When the host reads the interrupt status register,
this bit is cleared. Interrupts for the TxUBINT sticky bit can be
enabled by setting the TxUBINT Mask bit in the interrupt
status mask register
S/PDIF 0
ADDRESS = 0x52
0...7
0...7
8...15
8...15
16...23
16...23
USER-BIT
BUFFER
SECOND
BUFFER
Interrupts
The ADAV801 provides interrupt bits to indicate the presence
of certain conditions that require attention. Reading the
interrupt status register (Register 0x1C) allows the user to
determine if any of the interrupts have been asserted. The bits
of the Interrupt Status register remain high, if set, until the
register is read. Two bits, SRCError and RxError, indicate
interrupt conditions in the sample rate converter and an S/PDIF
receiver error, respectively. Both these conditions require a read
of the appropriate error register (Register 0x1A and Register
0x18, respectively) to determine the exact cause of the interrupt.
TRANSMITTER USER BIT
INDIRECT ADDRESS
REGISTER
ADDRESS = 0x53
When the user bits are transmitted according to the IEC 60958-3
format, the messages contained in the user bits can still be sent
without dropping or repeating messages. Because zero-stuffing
is allowed between IUs and messages, zeros can be added or
subtracted to preserve the messages. When the transmitter
sample rate is greater than the receiver sample rate, extra zeros
are stuffed between the messages. When the sample rate of the
transmitter is less than the sample rate of the receiver, the zeros
stuffed between the messages are subtracted. If there are not
enough zeros between the messages to be subtracted, the zeros
between IUs are subtracted as well. The Zero_Stuff_IU bit in
the Autobuffer register enables the adding or subtracting of
zeros between messages.
TRANSMITTER USER BIT
DATA REGISTER
04577-029
Each interrupt in the interrupt status register has an associated
mask bit in the interrupt status mask register. The interrupt
mask bit must be set for the corresponding interrupt to be
generated. This feature allows the user to determine which
functions should be responded to.
Figure 49. Transmitter User Bit Buffer
Autobuffering
The ADAV801 S/PDIF receiver and transmitter sections have
an autobuffering mode allowing the channel status and user bits
to be copied automatically from the receiver to the transmitter
without user intervention. The channel status and user bits
can be independently selected for autobuffering using the
Auto_CSBits and Auto_UBits bits, respectively, in the Autobuffer register. When the receiver and transmitter are running
at the same sample rate, the transmitted channel status and user
bits are the same as the received channel-status and user bits.
In many systems, however, it is likely that the receiver and
transmitter are not running at the same frequency. When the
transmitter sample rate is higher than receiver sample rate, the
channel status and user bit blocks are sometimes repeated.
When the transmitter sample rate is lower than the receiver
sample rate, the channel status and user bit blocks might be
dropped. Because the first five bytes of the channel status are
typically constant, they can be repeated or dropped with no
information loss. However, if the PRO bit in the channel status
is set and the local sample address code and time-of-day code
bytes contain information, these bytes might be repeated or
dropped, in which case information can be lost. It is up to the
user to determine how to handle this case.
The dual function pin ZEROL/INT can be set to indicate the
presence of no audio data on the left channel or the presence of
an interrupt set in the interrupt status register. As shown in
Table 16, the function of this pin is selected by the INTRPT bit
in DAC Control Register 4.
Table 16. ZEROL/INT Pin Functionality
INTRPT
0
1
Pin Functionality
Pin functions as a ZEROL flag pin.
Pin functions as an interrupt pin.
SERIAL DATA PORTS
The ADAV801 contains four flexible serial ports (SPORTs) to
allow data transfer to and from the codec. All four SPORTs are
independent and can be configured as master or slave ports. In
slave mode, the xLRCLK and xBCLK signals are inputs to the
serial ports. In master mode, the serial port generates the
xLRCLK and xBCLK signals. The master clock for the SPORT
can be selected from a number of sources, as shown in
Figure 50.
Rev. A | Page 27 of 60
ADAV801
REG 0x76
BITS[4:2]
DIR PLL (512 × fS)
DIR PLL (256 × fS)
PLLINT1
PLLINT2
MCLKI
XIN
ADC
MCLK
ICLK1
ICLK2
PLL CLOCK
REG 0x76
BITS[7:5]
DIR PLL (512 × fS)
DIR PLL (256 × fS)
PLLINT1
PLLINT2
MCLKI
XIN
Care should be taken to ensure that the clock rate is appropriate
for whatever block is connected to the serial port. For example,
if the ADC is running from the MCLKI input at 256 × fS, then
the master clock for the SPORT should also run from the
MCLKI input to ensure that the ADC and serial port are
synchronized.
OLRCLK
OBCLK
OSDATA
OUTPUT
PORT
REG 0x06
BITS[5:4]
DAC
INPUT
PORT
MCLK
ICLK1
ICLK2
PLL CLOCK
The SPORTs can be set to transmit or receive data in I2S, leftjustified or right-justified formats with different word lengths
by programming the appropriate bits in the playback register,
auxiliary input port register, record register, and auxiliary
output port-control register. Figure 51 is a timing diagram of
the serial data port formats.
ILRCLK
IBCLK
ISDATA
REG 0x04
BITS[4:3]
Clocking Scheme
The ADAV801 provides a flexible choice of on-chip and offchip clocking sources. The on-chip oscillator with dual PLLs is
intended to offer complete system clocking requirements for
use with available MPEG encoders, decoders, or a combination
of codecs. The oscillator function is designed for generation of a
27 MHz video clock from a 27 MHz crystal connected between
the XIN and XOUT pins. Capacitors must also be connected
between these pins and DGND, as shown in Figure 35. The
capacitor values should be specified by the crystal manufacturer.
A square wave version of the crystal clock is output on the
MCLKO pin. If the system has a 27 MHz clock available, this
clock can be connected directly to the XIN pin.
04577-0-031
REG 0x77
BITS[4:3]
REG 0x00
SRC
REG 0x00
BITS[1:0]
MCLKI
BITS[3:2]
MCLK
ICLK1
XIN
DIVIDER
PLLINT1
DIR PLL (512 × fS)
PLLINT2
DIVIDER
DIR PLL (256 × fS)
REG 0x00
MCLKI
BITS[7:6]
XIN
DIVIDER
PLLINT1
ICLK2
REG 0x00
PLLINT2
BITS[4:5]
REG 0x76
BITS[1:0]
Figure 50. SPORT Clocking Scheme
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
LSB
MSB
LSB
MSB
LEFT-JUSTIFIED MODE — 16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
RIGHT CHANNEL
BCLK
SDATA
LSB
MSB
LSB
MSB
I2S MODE — 16 BITS TO 24 BITS PER CHANNEL
LRCLK
LEFT CHANNEL
RIGHT CHANNEL
BCLK
MSB
LSB
MSB
RIGHT-JUSTIFIED MODE — SELECT NUMBER OF BITS PER CHANNEL
Figure 51. Serial Data Modes
Rev. A | Page 28 of 60
LSB
04577-030
SDATA
ADAV801
PLL
The ADAV801 features a digital input/output switching/
multiplexing matrix that gives flexibility to the range of possible
input and output connections. Digital input ports include
playback and auxiliary input (both 3-wire digital), and S/PDIF
(single-wire to the on-chip receiver). Output ports include the
record and auxiliary output ports (both 3-wire digital) and the
S/PDIF port (single-wire from the on-chip transmitter).
Internally, the DIR and DIT are interfaced via 3-wire interfaces.
The datapath for each input and output port is selected by
programming Datapath Control Register 1 and Datapath
Control Register 2. Figure 52 shows the internal datapath
structure of the ADAV801.
OSCILLATOR
RECORD
DATA
OUTPUT
ADC
AUX
DATA
OUTPUT
REFERENCE
SRC
DIT
DAC
CONTROL
REGISTERS
PLAYBACK
DATA
INPUT
AUX
DATA
INPUT
Figure 52. Datapath
Rev. A | Page 29 of 60
DIR
04577-032
Datapath
ADAV801
INTERFACE CONTROL
The ADAV801 has a dedicated control port to allow access to
the internal registers of the ADAV801. Each of the internal
registers is eight bits wide. Where bits are described as reserved
(RES), these bits should be programmed as zero.
BLOCK READS AND WRITES
The ADAV801 provides the user with the ability to write to or
read from a block of registers in one continuous operation. In
SPI mode, the CLATCH line should be held low for longer than
the 16 CCLK periods to use the block read/write mode. For a
write operation, once the LSB has been clocked into the
ADAV801 on the 16th CCLK, the register address as specified
by the first seven bits of the write operation is incremented and
the next eight bits are clocked into the next register address.
SPI INTERFACE
Control of the ADAV801 is via an SPI-compatible serial port.
The SPI control port is a 4-wire serial control port with one
cycle of data transfer consisting of 16 bits. Figure 53 shows the
format of an SPI write/read of the ADAV801. The transfer of
data is initiated on the falling edge of CLATCH. The data
presented on the first seven CCLKs represents the register
address read/write bit. If this bit is low, the following eight bits
of data are loaded to the register address provided. If this bit is
high, a read operation is indicated. The contents of the register
address are clocked out on the COUT pin on the following eight
CCLKs. For a read operation, the data bits after the read/write
bits are ignored.
The read operation is similar. Once the LSB of a read register
operation has been clocked out, the register address is
incremented and the data from the next register is clocked out
on the following eight CCLKs. Figure 55 and Figure 56 show the
timing diagrams for the block write and read operations.
CLATCH
D15
D14
COUT
D9
D8
D0
D9
D8
D0
Figure 53. SPI Serial Port Timing Diagram
R/W
ADDRESS [6:0]
15
14
13
12
11
10
9
8
DATA [7:0]
7
6
5
4
3
2
1
0
04577-036
Figure 54. SPI Control Word Format
CIN
REGISTER
R/W = 0
8 BITS
REGISTER DATA
REGISTER + 1 DATA
REGISTER + 2 DATA
8 BITS
8 BITS
8 BITS
04577-034
CLATCH
Figure 55. SPI Block Write Operation
CLATCH
CIN
REGISTER
COUT
8 BITS
DON’T CARE
R/W = 1
REGISTER DATA
REGISTER + 1 DATA
REGISTER + 2 DATA
8 BITS
8 BITS
8 BITS
Figure 56. SPI Block Read Operation
Rev. A | Page 30 of 60
04577-035
CIN
04577-033
CCLK
ADAV801
REGISTER DESCRIPTIONS
SRC and Clock Control—Address 0000000 (0x00)
Table 17. SRC and Clock Control Register Bit Map
7
SRCDIV1
6
SRCDIV0
5
CLK2DIV1
4
CLK2DIV0
3
CLK1DIV1
2
CLK1DIV0
1
MCLKSEL1
0
MCLKSEL0
3
Reserved
2
Reserved
1
Reserved
0
TxMUX
Table 18. SRC and Clock Control Register Bit Descriptions
Bit Name
SRCDIV[1:0]
CLK2DIV[1:0]
CLK1DIV[1:0]
MCLKSEL[1:0]
Description
Divides the SRC master clock.
00 = SRC master clock is not divided.
01 = SRC master clock is divided by 1.5.
10 = SRC master clock is divided by 2.
11 = SRC master clock is divided by 3.
Clock divider for Internal Clock 2 (ICLK2).
00 = Divide by 1.
01 = Divide by 1.5.
10 = Divide by 2.
11 = Divide by 3.
Clock divider for Internal Clock 1 (ICLK1).
00 = Divide by 1.
01 = Divide by 1.5.
10 = Divide by 2.
11 = Divide by 3.
Clock selection for the SRC master clock.
00 = Internal Clock 1.
01 = Internal Clock 2.
10 = PLL recovered clock (512 × fS).
11 = PLL recovered clock (256 × fS).
S/PDIF Loopback Control—Address 0000011 (0x03)
Table 19. S/PDIF Loopback Control Register Bit Map
7
Reserved
6
Reserved
5
Reserved
4
Reserved
Table 20. S/PDIF Loopback Control Register Bit Descriptions
Bit Name
TxMUX
Description
Selects the source for S/PDIF output (DITOUT).
0 = S/PDIF transmitter, normal mode.
1 = DIRIN, loopback mode.
Rev. A | Page 31 of 60
ADAV801
Playback Port Control—Address 0000100 (0x04)
Table 21. Playback Port Control Register Bit Map
7
Reserved
6
Reserved
5
Reserved
4
CLKSRC1
3
CLKSRC0
2
SPMODE2
1
SPMODE1
0
SPMODE0
2
SPMODE2
1
SPMODE1
0
SPMODE0
Table 22. Playback Port Control Register Bit Descriptions
Bit Name
CLKSRC[1:0]
SPMODE[2:0]
Description
Selects the clock source for generating the ILRCLK and IBCLK.
00 = Input port is a slave.
01 = Recovered PLL clock.
10 = Internal Clock 1.
11 = Internal Clock 2.
Selects the serial format of the playback port.
000 = Left-justified.
001 = I2S.
100 = 24-bit, right-justified.
101 = 20-bit, right-justified.
110 = 18-bit, right-justified.
111 = 16-bit, right-justified.
Auxiliary Input Port—Address 0000101 (0x05)
Table 23. Auxiliary Input Port Register Bit Map
7
Reserved
6
Reserved
5
Reserved
4
CLKSRC1
3
CLKSRC0
Table 24. Auxiliary Input Port Register Bit Descriptions
Bit Name
CLKSRC[1:0]
SPMODE[2:0]
Description
Selects the clock source for generating the IAUXLRCLK and IAUXBCLK.
00 = Input port is a slave.
01 = Recovered PLL cock.
10 = Internal Clock 1.
11 = Internal Clock 2.
Selects the serial format of auxiliary input port.
000 = Left-justified.
001 = I2S.
100 = 24-bit, right-justified.
101 = 20-bit, right-justified.
110 = 18-bit, right-justified.
111 = 16-bit, right-justified.
Rev. A | Page 32 of 60
ADAV801
Record Port Control—Address 0000110 (0x06)
Table 25. Record Port Control Register Bit Map
7
Reserved
6
Reserved
5
CLKSRC1
4
CLKSRC0
3
WLEN1
2
WLEN0
1
SPMODE1
0
SPMODE0
2
WLEN0
1
SPMODE1
0
SPMODE0
Table 26. Record Port Control Register Bit Descriptions
Bit Name
CLKSRC[1:0]
WLEN[1:0]
SPMODE[1:0]
Description
Selects the clock source for generating the OLRCLK and OBCLK.
00 = Record port is a slave.
01 = Recovered PLL clock.
10 = Internal Clock 1.
11 = Internal Clock 2.
Selects the serial output word length.
00 = 24 bits.
01 = 20 bits.
10 = 18 bits.
11 = 16 bits.
Selects the serial format of the record port.
00 = Left-justified.
01 = I2S.
10 = Reserved.
11 = Right-justified.
Auxiliary Output Port—Address 0000111 (0x07)
Table 27. Auxiliary Output Port Register Bit Map
7
Reserved
6
Reserved
5
CLKSRC1
4
CLKSRC0
3
WLEN1
Table 28. Auxiliary Output Port Register Bit Descriptions
Bit Name
CLKSRC[1:0]
WLEN[1:0]
SPMODE[1:0]
Description
Selects the clock source for generating the OAUXLRCLK and OAUXBCLK.
00 = Auxiliary record port is a slave.
01 = Recovered PLL clock.
10 = Internal Clock 1.
11 = Internal Clock 2.
Selects the serial output word length.
00 = 24 bits.
01 = 20 bits.
10 = 18 bits.
11 = 16 bits.
Selects the serial format of the auxiliary record port.
00 = Left-justified.
01 = I2S.
10 = Reserved.
11 = Right-justified.
Rev. A | Page 33 of 60
ADAV801
Group Delay and Mute—Address 0001000 (0x08)
Table 29. Group Delay and Mute Register Bit Map
7
MUTE_SRC
6
GRPDLY6
5
GRPDLY5
4
GRPDLY4
3
GRPDLY3
2
GRPDLY2
1
GRPDLY1
0
GRPDLY0
1
LOCK1
0
LOCK0
Table 30. Group Delay and Mute Register Bit Descriptions
Bit Name
MUTE_SRC
Description
Soft-mutes the output of the sample rate converter.
0 = No mute.
1 = Soft mute.
Adds delay to the sample rate converter FIR filter by GRPDLY[6:0] input samples.
0000000 = No delay.
0000001 = 1 sample delay.
0000010 = 2 sample delay.
1111110 = 126 sample delay.
1111111 = 127 sample delay.
GRPDLY[6:0]
Receiver Configuration 1—Address 0001001 (0x09)
Table 31. Receiver Configuration 1 Register Bit Map
7
NOCLOCK
6
RxCLK1
5
RxCLK0
4
AUTO_DEEMPH
3
ERR1
2
ERR0
Table 32. Receiver Configuration 1 Register Bit Descriptions
Bit Name
NOCLOCK
RxCLK[1:0]
AUTO_DEEMPH
ERR[1:0]
LOCK[1:0]
Description
Selects the source of the receiver clock when the PLL is not locked.
0 = Recovered PLL clock is used.
1 = ICLK1 is used.
Determines the oversampling ratio of the recovered receiver clock.
00 = RxCLK is a 128 × fS recovered clock.
01 = RxCLK is a 256 × fS recovered clock.
10 = RxCLK is a 512 × fS recovered clock.
11 = Reserved.
Automatically de-emphasizes the data from the receiver based on the channel status information.
0 = Automatic de-emphasis is disabled.
1 = Automatic de-emphasis is enabled.
Defines what action the receiver should take, if the receiver detects a parity or biphase error.
00 = No action is taken.
01 = Last valid sample is held.
10 = Invalid sample is replaced with zeros.
11 = Reserved.
Defines what action the receiver should take, if the PLL loses lock.
00 = No action is taken.
01 = Last valid sample is held.
10 = Zeros are sent out after the last valid sample.
11 = Soft-mute of the last valid audio sample.
Rev. A | Page 34 of 60
ADAV801
Receiver Configuration 2—Address 0001010 (0x0A)
Table 33. Receiver Configuration 2 Register Bit Map
7
RxMUTE
6
SP_PLL
5
SP_PLL_ SEL1
4
SP_PLL_ SEL0
3
Reserved
2
Reserved
1
NO NONAUDIO
0
NO_VALIDITY
Table 34. Receiver Configuration 2 Register Bit Descriptions
Bit Name
RxMUTE
SP_PLL
SP_PLL_SEL[1:0]
NO NONAUDIO
NO_VALIDITY
Description
Hard-mutes the audio output for the AES3/S/PDIF receiver.
0 = AES3/S/PDIF receiver is not muted.
1 = AES3/S/PDIF receiver is muted.
AES3/S/PDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.
0 = Left/right clock generated from the AES3/S/PDIF preambles is the reference clock to the PLL.
1 = Left/right clock from one of the serial ports is the reference clock to the PLL.
Selects one of the four serial ports as the reference clock to the PLL when SP_PLL is set.
00 = Playback port is selected.
01 = Auxiliary input port is selected.
10 = Record port is selected.
11 = Auxiliary output port is selected.
When the NO NONAUDIO bit is set, data from the AES3/S/PDIF receiver is not allowed into the sample rate converter
(SRC). If the NO NONAUDIO data is due to DTS, AAC, and so on, as defined by the IEC61937 standard, then the data
from the AES3/S/PDIF receiver is not allowed into the SRC regardless of the state of this bit.
0 = AES3/S/PDIF receiver data is sent to the SRC.
1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO NONAUDIO bit is set.
When the NO_VALIDITY bit is set, data from the AES3/S/PDIF receiver is not allowed into the SRC.
0 = AES3/S/PDIF receiver data is sent to the SRC.
1 = Data from the AES3/S/PDIF receiver is not allowed into the SRC, if the NO_VALIDITY bit is set.
Rev. A | Page 35 of 60
ADAV801
Receiver Buffer Configuration—Address 0001011 (0x0B)
Table 35. Receiver Buffer Configuration Register Bit Map
7
Reserved
6
Reserved
5
RxBCONF5
4
RxBCONF4
3
RxBCONF3
2
RxBCONF2
1
RxBCONF1
0
RxBCONF0
Table 36. Receiver Buffer Configuration Register Bit Descriptions
Bit Name
RxBCONF5
RxBCONF4
RxBCONF3
RxBCONF[2:1]
RxBCONF0
Description
If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit
interrupt is enabled only when there is a change in the start (ID) bit.
0 = User bit interrupt is enabled in normal mode.
1 = If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit.
This bit determines whether Channel A and Channel B user bits are stored in the buffer together or separated
between A and B.
0 = User bits are stored together.
1 = User bits are stored separately.
Defines the function of RxCSBINT.
0 = RxCSBINT are set when a new block of receiver channel status is read, which is 192 audio frames.
1 = RxCSBINT is set only if the first five bytes of the receiver channel status block changes from the previous
channel status block.
Defines the user bit buffer.
00 = User bits are ignored.
01 = Updates the second user bit buffer when the first user bit buffer is full.
10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If
the PRO bit is not set, formats the user bits according to the IEC60958-3 standard.
11 = Reserved.
Defines the user bit buffer size, if RxBCONF[2:1] = 01.
0 = 384 bits with Preamble Z as the start of the buffer.
1 = 768 bits with Preamble Z as the start of the buffer.
Transmitter Control—Address 0001100 (0x0C)
Table 37. Transmitter Control Register Bit Map
7
Reserved
6
TxVALIDITY
5
TxRATIO2
4
TxRATIO1
3
TxRATIO0
2
TxCLKSEL1
Table 38. Transmitter Control Register Bit Descriptions
Bit Name
TxVALIDITY
TxRATIO[2:0]
TxCLKSEL[1:0]
TxENABLE
Description
This bit is used to set or clear the VALIDITY bit in the AES3/S/PDIF transmit stream.
0 = Audio is suitable for digital-to-analog conversion.
1 = Audio is not suitable for digital-to-analog conversion.
Determines the AES3/S/PDIF transmitter to AES3/S/PDIF receiver ratio.
000 = Transmitter to receiver ratio is 1:1.
001 = Transmitter to receiver ratio is 1:2.
010 = Transmitter to receiver ratio is 1:4.
101 = Transmitter to receiver ratio is 2:1.
110 = Transmitter to receiver ratio is 4:1.
Selects the clock source for the AES3/S/PDIF transmitter.
00 = Internal Clock 1 is the clock source for the transmitter.
01 = Internal Clock 2 is the clock source for the transmitter.
10 = Recovered PLL clock is the clock source for the transmitter.
11 = Reserved.
Enables the AES3/S/PDIF transmitter.
0 = AES3/S/PDIF transmitter is disabled.
1 = AES3/S/PDIF transmitter is enabled.
Rev. A | Page 36 of 60
1
TxCLKSEL0
0
TxENABLE
ADAV801
Transmitter Buffer Configuration—Address 0001101 (0x0D)
Table 39. Transmitter Buffer Configuration Register Bit Map
7
IU_Zeros3
6
IU_Zeros2
5
IU_Zeros1
4
IU_Zeros0
3
TxBCONF3
2
TxBCONF2
1
TxBCONF1
0
TxBCONF0
Table 40. Transmitter Buffer Configuration Register Bit Descriptions
Bit Name
IU_Zeros[3:0]
TxBCONF3
TxBCONF[2:1]
TxBCONF0
Description
Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8.
0000 = 0.
0001 = 1.
…
0111 = 7.
1000 = 8.
Transmitter user bits can be stored in separate buffers or stored together.
0 = User bits are stored together.
1 = User bits are stored separately.
Configures the transmitter user bit buffer.
00 = Zeros are transmitted for the user bits.
01 = Transmitter user bit buffer size is configured according to TxBCONF0.
10 = User bits are written to the transmit buffer in IUs specified by the IEC60958-3 standard.
11 = Reserved.
Determines the buffer size of the transmitter user bits when TxBCONF[2:1] is 01.
0 = 384 bits with Preamble Z as the start of the buffer.
1 = 768 bits with Preamble Z as the start of the buffer.
Channel Status Switch Buffer and Transmitter—Address 0001110 (0x0E)
Table 41. Channel Status Switch Buffer and Transmitter Register Bit Map
7
Reserved
6
Reserved
5
Tx_A/B_Same
4
Disable_Tx_Copy
3
Reserved
2
Reserved
1
TxCSSWITCH
0
RxCSSWITCH
Table 42. Channel Status Switch Buffer and Transmitter Register Bit Description
Bit Name
Tx_A/B_Same
Disable_Tx_Copy
TxCSSWITCH
RxCSSWITCH
Description
Transmitter Channel Status A and B are the same. The transmitter reads only from the Channel Status A buffer and
places the data into the Channel Status B buffer.
0 = Channel status for A and B are separate.
1 = Channel status for A and B are the same.
Disables the copying of the channel status bits from the transmitter channel status buffer to the S/PDIF transmitter
buffer.
0 = Copying transmitter channel status is enabled.
1 = Copying transmitter channel status is disabled.
Toggle switch for the transmit channel status buffer.
0 = 24-byte Transmitter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F.
1 = 24-byte Transmitter Channel Status B buffer can be accessed at address locations 0x38 through 0x4F.
Toggle switch for the receive channel status buffer.
0 = 24-byte Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37.
1 = 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37.
Rev. A | Page 37 of 60
ADAV801
Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F)
Table 43. Transmitter Message Zeros Most Significant Byte Register Bit Map
7
MSBZeros7
6
MSBZeros6
5
MSBZeros5
4
MSBZeros4
3
MSBZeros3
2
MSBZeros2
1
MSBZeros1
0
MSBZeros0
Table 44. Transmitter Message Zeros Most Significant Byte Register Bit Description
Bit Name
MSBZeros[7:0]
Description
Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets).
Default = 0x00.
Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10)
Table 45. Transmitter Message Zeros Least Significant Byte Register Bit Map
7
LSBZeros7
6
LSBZeros6
5
LSBZeros5
4
LSBZeros4
3
LSBZeros3
2
LSBZeros2
1
LSBZeros1
0
LSBZeros0
Table 46. Transmitter Message Zeros Least Significant Byte Register Bit Descriptions
Bit Name
LSBZeros[7:0]
Description
Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09.
Autobuffer—Address 0010001 (0x11)
Table 47. Autobuffer Register Bit Map
7
Reserved
6
Zero_Stuff_IU
5
Auto_UBits
4
Auto_CSBits
3
IU_Zeros3
2
IU_Zeros2
1
IU_Zeros1
0
IU_Zeros0
Table 48. Autobuffer Register Bit Descriptions
Bit Name
Zero_Stuff_IU
Auto_UBits
Auto_CSBits
IU_Zeros[3:0]
Description
Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format.
0 = No zeros added or subtracted.
1 = Zeros can be added or subtracted between IUs.
Enables the user bits to be autobuffered between the AES3/S/PDIF receiver and transmitter.
0 = User bits are not autobuffered.
1 = User bits are autobuffered.
Enables the channel status bits to be autobuffered between the AES3/S/PDIF receiver and transmitter.
0 = Channel status bits are not autobuffered.
1 = Channel status bits are autobuffered.
Sets the maximum number of zero-stuffing to be added between IUs while autobuffering up to a maximum of 8.
0000 = 0.
0001 = 1.
…
0111 = 7.
1000 = 8.
Sample Rate Ratio MSB—Address 0010010 (0x12)
Table 49. Sample Rate Ratio MSB Register (Read-Only) Bit Map
7
Reserved
6
SRCRATIO14
5
SRCRATIO13
4
SRCRATIO12
3
SRCRATIO11
Table 50. Sample Rate Ratio MSB Register (Read-Only) Bit Descriptions
Bit Name
SRCRATIO[14:8]
Description
Seven most significant bits of the15-bit sample rate ratio.
Rev. A | Page 38 of 60
2
SRCRATIO10
1
SRCRATIO09
0
SRCRATIO08
ADAV801
Sample Rate Ratio LSB—Address 0010011 (0x13)
Table 51. Sample Rate Ratio LSB Register (Read-Only) Bit Map
7
SRCRATIO07
6
SRCRATIO06
5
SRCRATIO05
4
SRCRATIO04
3
SRCRATIO03
2
SRCRATIO02
1
SRCRATIO01
0
SRCRATIO00
2
PRE_C10
1
PRE_C9
0
PRE_C8
Table 52. Sample Rate Ratio LSB Register (Read-Only) Bit Descriptions
Bit Name
SRCRATIO[7:0]
Description
Eight least significant bits of the15-bit sample rate ratio.
Preamble-C MSB—Address 0010100 (0x14)
Table 53. Preamble-C MSB Register (Read-Only) Bit Map
7
PRE_C15
6
PRE_C14
5
PRE_C13
4
PRE_C12
3
PRE_C11
Table 54. Preamble-C MSB Register (Read-Only) Bit Descriptions
Bit Name
PRE_C[15:8]
Description
Eight most significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937
standard; otherwise, bits show zeros.
Preamble-C LSB—Address 0010101 (0x15)
Table 55. Preamble-C LSB Register (Read-Only) Bit Map
7
PRE_C07
6
PRE_C06
5
PRE_C05
4
PRE_C04
3
PRE_C03
2
PRE_C02
1
PRE_C01
0
PRE_C00
Table 56. Preamble-C LSB Register (Read-Only) Bit Descriptions
Bit Name
PRE_C[7:0]
Description
Eight least significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937
standard; otherwise, bits show zeros.
Preamble-D MSB—Address 0010110 (0x16)
Table 57. Preamble-D MSB Register (Read-Only) Bit Map
7
PRE_D15
6
PRE_D14
5
PRE_D13
4
PRE_D12
3
PRE_D11
2
PRE_D10
1
PRE_D9
0
PRE_D8
Table 58. Preamble-D MSB Register (Read-Only) Bit Descriptions
Bit Name
PRE_D[15:8]
Description
Eight most significant bits of the 16-bit Preamble-D, when nonaudio data is detected according to the IEC60937
standard; otherwise, bits show zeros. When subframe nonaudio is used, this becomes the eight most significant bits
of the 16-bit Preamble-C of Channel B.
Preamble-D LSB—Address 0010111 (0x17)
Table 59. Preamble-D LSB Register (Read-Only) Bit Map
7
PRE_D07
6
PRE_D06
5
PRE_D05
4
PRE_D04
3
PRE_D03
2
PRE_D02
1
PRE_D01
0
PRE_D00
Table 60. Preamble-D LSB Register (Read-Only) Bit Descriptions
Bit Name
PRE_D[7:0]
Description
Eight least significant bits of the 16-bit Preamble-D, when nonaudio data is detected according to the IEC60937
standard; otherwise, bits show zeros. When subframe nonaudio is used, this becomes the eight most significant bits
of the 16-bit Preamble-C of Channel B.
Rev. A | Page 39 of 60
ADAV801
Receiver Error—Address 0011000 (0x18)
Table 61. Receiver Error Register (Read-Only) Bit Map
7
RxValidity
6
Emphasis
5
NonAudio
4
NonAudio Preamble
3
CRCError
2
NoStream
1
BiPhase/Parity
0
Lock
Table 62. Receiver Error Register (Read-Only) Bit Descriptions
Bit Name
RxValidity
Emphasis
NonAudio
NonAudio
Preamble
CRCError
NoStream
BiPhase/Parity
Lock
Description
This is the VALIDITY bit in the AES3 received stream.
This bit is set if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an
interrupt unless it changes state.
This bit is set when Channel Status Bit 1 (nonaudio) is set. Once it has been read, it does not generate another interrupt
unless the data becomes audio or the type of nonaudio data changes.
This bit is set if the audio data is nonaudio due to the detection of a preamble. The nonaudio preamble type register
indicates what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt
unless it changes state.
This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error register is read.
This bit is set if there is no AES3/S/PDIF stream present at the AES3/S/PDIF receiver. Once read, it remains high and does
not generate an interrupt unless it changes state.
This bit is set if a biphase or parity error occurred in the AES3/S/PDIF stream. This bit is not cleared until the register is read.
This bit is set if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not
generate an interrupt unless it changes state.
Receiver Error Mask—Address 0011001 (0x19)
Table 63. Receiver Error Mask Register Bit Map
7
RxValidity
Mask
6
Emphasis
Mask
5
NonAudio
Mask
4
NonAudio Preamble
Mask
3
CRCError
Mask
2
NoStream
Mask
Table 64. Receiver Error Mask Register Bit Descriptions
Bit Name
RxValidity Mask
Emphasis Mask
NonAudio Mask
NonAudio Preamble Mask
CRCError Mask
NoStream Mask
BiPhase/Parity Mask
Lock Mask
Description
Masks the RxValidity bit from generating an interrupt.
0 = RxValidity bit does not generate an interrupt.
1 = RxValidity bit generates an interrupt.
Masks the Emphasis bit from generating an interrupt.
0 = Emphasis bit does not generate an interrupt.
1 = Emphasis bit generates an interrupt.
Masks the NonAudio bit from generating an interrupt.
0 = NonAudio bit does not generate an interrupt.
1 = NonAudio bit generates an interrupt.
Masks the NonAudio preamble bit from generating an interrupt.
0 = NonAudio preamble bit does not generate an interrupt.
1 = NonAudio preamble bit generates an interrupt.
Masks the CRCError bit from generating an interrupt.
0 = CRCError bit does not generate an interrupt.
1 = CRCError bit generates an interrupt.
Masks the NoStream bit from generating an interrupt.
0 = NoStream bit does not generate an interrupt.
1 = NoStream bit generates an interrupt.
Masks the BiPhase/Parity bit from generating an interrupt.
0 = BiPhase/Parity bit does not generate an interrupt.
1 = BiPhase/Parity bit generates an interrupt.
Masks the Lock bit from generating an interrupt.
0 = Lock bit does not generate an interrupt.
1 = Lock bit generates an interrupt.
Rev. A | Page 40 of 60
1
BiPhase/Parity
Mask
0
Lock
Mask
ADAV801
Sample Rate Converter Error—Address 0011010 (0x1A)
Table 65. Sample Rate Converter Error Register (Read-Only) Bit Map
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
TOO_SLOW
2
OVRL
1
OVRR
0
MUTE_IND
Table 66. Sample Rate Converter Error Register (Read-Only) Bit Descriptions
Bit Name
TOO_SLOW
OVRL
OVRR
MUTE_IND
Description
This bit is set when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the
internal convolution.
This bit is set when the left output data of the sample rate converter has gone over the full-scale range and has been
clipped. This bit is not cleared until the register is read.
This bit is set when the right output data of the sample rate converter has gone over the full-scale range and has
been clipped. This bit is not cleared until the register is read.
Mute indicated. This bit is set when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.
The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state
and does not generate an interrupt until it has changed state.
Sample Rate Converter Error Mask—Address 0011011 (0x1B)
Table 67. Sample Rate Converter Error Mask Register Bit Map
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Table 68. Sample Rate Converter Error Mask Register Bit Descriptions
Bit Name
OVRL Mask
OVRR Mask
MUTE_IND MASK
Description
Masks the OVRL from generating an interrupt.
0 = OVRL bit does not generate an interrupt.
1 = OVRL bit generates an interrupt.
Masks the OVRR from generating an interrupt.
0 = OVRR bit does not generate an interrupt.
1 = OVRR bit generates an interrupt. Reserved.
Masks the MUTE_IND from generating an interrupt.
0 = MUTE_IND bit does not generate an interrupt.
1 = MUTE_IND bit generates an interrupt.
Rev. A | Page 41 of 60
2
OVRL Mask
1
OVRR Mask
0
MUTE_IND MASK
ADAV801
Interrupt Status—Address 0011100 (0x1C)
Table 69. Interrupt Status Register Bit Map
7
SRCError
6
TxCSTINT
5
TxUBINT
4
TxCSBINT
3
RxCSDIFF
2
RxUBINT
1
RxCSBINT
0
RxERROR
Table 70. Interrupt Status Register Bit Descriptions
Bit Name
SRCError
TxCSTINT
TxUBINT
TxCSBINT
RxCSDIFF
RxUBINT
RxCSBINT
RxERROR
Description
This bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample
rate converter error register. This bit remains high until the interrupt status register is read.
This bit is set if a write to the transmitter channel status buffer was made while transmitter channel status bits were being
copied from the transmitter CS buffer to the S/PDIF transmit buffer.
This bit is set if the S/PDIF transmit buffer is empty. This bit remains high until the interrupt status register is read.
This bit is set if the transmitter channel status bit buffer has transmitted its block of channel status. This bit remains high
until the interrupt status register is read.
This bit is set if the receiver Channel Status A block is different from the receiver Channel Status B clock. This bit remains
high until read, but does not generate an interrupt.
This bit is set if the receiver user bit buffer has a new block or message. This bit remains high until the interrupt status
register is read.
This bit is set if a new block of channel status is read when RxBCONF3 = 0, or if the channel status has changed when
RxBCONF3 = 1. This bit remains high until the interrupt status register is read.
This bit is set if one of the AES3/S/PDIF receiver interrupts is asserted, and the host should immediately read the receiver
error register. This bit remains high until the interrupt status register is read.
Interrupt Status Mask—Address 0011101 (0x1D)
Table 71. Interrupt Status Mask Register Bit Map
7
SRCError Mask
6
TxCSTINT Mask
5
TxUBINT Mask
4
TxCSBINT Mask
3
Reserved
Table 72. Interrupt Status Mask Register Bit Descriptions
Bit Name
SRCError Mask
TxCSTINT Mask
TxUBINT Mask
TxCSBINT Mask
RxUBINT Mask
RxCSBINT Mask
RxError Mask
Description
Masks the SRCError bit from generating an interrupt.
0 = SRCError bit does not generate an interrupt.
1 = SRCError bit generates an interrupt.
Masks the TxCSTINT bit from generating an interrupt.
0 = TxCSTINT bit does not generate an interrupt.
1 = TxCSTINT bit generates an interrupt.
Masks the TxUBINT bit from generating an interrupt.
0 = TxUBINT bit does not generate an interrupt.
1 = TxUBINT bit generates an interrupt.
Masks the TxCSBINT bit from generating an interrupt.
0 = TxCSBINT bit does not generate an interrupt.
1 = TxCSBINT bit generates an interrupt.
Masks the RxUBINT bit from generating an interrupt.
0 = RxUBINT bit does not generate an interrupt.
1 = RxUBINT bit generates an interrupt.
Masks the RxCSBINT bit from generating an interrupt.
0 = RxCSBINT bit does not generate an interrupt.
1 = RxCSBINT bit generates an interrupt.
Masks the RxError bit from generating an interrupt.
0 = RxError bit does not generate an interrupt.
1 = RxError bit generates an interrupt.
Rev. A | Page 42 of 60
2
RxUBINT Mask
1
RxCSBINT Mask
0
RxError Mask
ADAV801
Mute and De-Emphasis—Address 0011110 (0x1E)
Table 73. Mute and De-Emphasis Register Bit Map
7
Reserved
6
Reserved
5
TxMUTE
4
Reserved
3
Reserved
2
SRC_DEEM1
1
SRC_DEEM0
0
Reserved
1
NonAudio
Subframe_A
0
NonAudio
Subframe_B
Table 74. Mute and De-Emphasis Register Bit Descriptions
Bit Name
TxMUTE
Description
Mutes the AES3/S/PDIF transmitter.
0 = Transmitter is not muted.
1 = Transmitter is muted.
Selects the de-emphasis filter for the input data to the sample rate converter.
00 = No de-emphasis.
01 = 32 kHz de-emphasis.
10 = 44.1 kHz de-emphasis.
11 = 48 kHz de-emphasis.
SRC_DEEM[1:0]
NonAudio Preamble Type—Address 0011111 (0x1F)
Table 75. NonAudio Preamble Type Register (Read-Only) Bit Map
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
DTS-CD
Preamble
2
NonAudio
Frame
Table 76. NonAudio Preamble Type Register (Read-Only) Bit Descriptions
Bit Name
DTS-CD Preamble
NonAudio Frame
NonAudio Subframe_A
NonAudio Subframe_B
Description
This bit is set if the DTS-CD preamble is detected.
This bit is set if the data received through the AES3/S/PDIF receiver is nonaudio data according to the IEC61937
standard or nonaudio data according to SMPTE337M.
This bit is set if the data received through Channel A of the AES3/S/PDIF receiver is subframe nonaudio data
according to SMPTE337M.
This bit is set if the data received through Channel B of the AES3/S/PDIF receiver is subframe nonaudio data
according to SMPTE337M.
Receiver Channel Status Buffer—Address 0100000 to Address 0110111 (0x20 to 0x37)
Table 77. Receiver Channel Status Buffer Register Bit Map
7
RCSB7
6
RCSB6
5
RCSB5
4
RCSB4
3
RCSB3
2
RCSB2
1
RCSB1
0
RCSB0
Table 78. Receiver Channel Status Buffer Register Bit Descriptions
Bit Name
RCSB[7:0]
Description
The 24-byte receiver channel status buffer. The PRO bit is stored at address location 0x20, Bit 0. This buffer is readonly if the channel status is not autobuffered between the receiver and transmitter.
Transmitter Channel Status Buffer—Address 0111000 to Address 1001111 (0x38 to 0x4F)
Table 79. Transmitter Channel Status Buffer Register Bit Map
7
TCSB7
6
TCSB6
5
TCSB5
4
TCSB4
3
TCSB3
2
TCSB2
1
TCSB1
0
TCSB0
Table 80. Transmitter Channel Status Buffer Register Bit Descriptions
Bit Name
TCSB[7:0]
Description
The 24-byte transmitter channel status buffer. The PRO bit is stored at address location 0x38, Bit 0. This buffer is
disabled when autobuffering between the receiver and transmitter is enabled.
Rev. A | Page 43 of 60
ADAV801
Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50)
Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map
7
RxUBADDR7
6
RxUBADDR6
5
RxUBADDR5
4
RxUBADDR4
3
RxUBADDR3
2
RxUBADDR2
1
RxUBADDR1
0
RxUBADDR0
1
RxUBDATA1
0
RxUBDATA0
Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions
Bit Name
RxUBADDR[7:0]
Description
Indirect address pointing to the address location in the receiver user bit buffer.
Receiver User Bit Buffer Data—Address 1010001 (0x51)
Table 83. Receiver User Bit Buffer Data Register Bit Map
7
RxUBDATA7
6
RxUBDATA6
5
RxUBDATA5
4
RxUBDATA4
3
RxUBDATA3
2
RxUBDATA2
Table 84. Receiver User Bit Buffer Data Register Bit Descriptions
Bit Name
RxUBDATA[7:0]
Description
A read from this register reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR0[7:0].
This buffer can be written to when autobuffering of the user bits is enabled; otherwise, it is a read-only buffer.
Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52)
Table 85. Transmitter User Bit Buffer Indirect Address Register Bit Map
7
TxUBADDR7
6
TxUBADDR6
5
TxUBADDR5
4
TxUBADDR4
3
TxUBADDR3
2
TxUBADDR2
1
TxUBADDR1
0
TxUBADDR0
1
TxUBDATA1
0
TxUBDATA0
Table 86. Transmitter User Bit Buffer Indirect Address Register Bit Descriptions
Bit Name
TxUBADDR[7:0]
Description
Indirect address pointing to the address location in the transmitter user bit buffer.
Transmitter User Bit Buffer Data—Address 1010011 (0x53)
Table 87. Transmitter User Bit Buffer Data Register Bit Map
7
TxUBDATA7
6
TxUBDATA6
5
TxUBDATA5
4
TxUBDATA4
3
TxUBDATA3
2
TxUBDATA2
Table 88. Transmitter User Bit Buffer Data Register Bit Descriptions
Bit Name
TxUBDATA[7:0]
Description
A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR0[7:0].
When user bit autobuffering is enabled, this buffer is disabled.
Q Subcode CRCError Status—Address 1010100 (0x54)
Table 89. Q Subcode CRCError Status Register (Read-Only) Bit Map
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
QCRCERROR
0
QSUB
Table 90. Q Subcode CRCError Status Register (Read-Only) Bit Descriptions
Bit Name
QCRCERROR
QSUB
Description
This bit is set if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This
bit is cleared once the register is read.
This bit is set if a Q subcode has been read into the Q subcode buffer (see Table 91).
Rev. A | Page 44 of 60
ADAV801
Q Subcode Buffer—Address 0x55 to Address 0x5E
Table 91. Q Subcode Buffer Bit Map
Address
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
Bit 7
Address
Track
number
Index
Minute
Second
Frame
Zero
Absolute
minute
Absolute
second
Absolute
frame
Bit 6
Address
Track
number
Index
Minute
Second
Frame
Zero
Absolute
minute
Absolute
second
Absolute
frame
Bit 5
Address
Track
number
Index
Minute
Second
Frame
Zero
Absolute
minute
Absolute
second
Absolute
frame
Bit 4
Address
Track
number
Index
Minute
Second
Frame
Zero
Absolute
minute
Absolute
second
Absolute
frame
Bit 3
Control
Track
number
Index
Minute
Second
Frame
Zero
Absolute
minute
Absolute
second
Absolute
frame
Bit 2
Control
Track
number
Index
Minute
Second
Frame
Zero
Absolute
minute
Absolute
second
Absolute
frame
Bit 1
Control
Track
number
Index
Minute
Second
Frame
Zero
Absolute
minute
Absolute
second
Absolute
frame
Bit 0
Control
Track
number
Index
Minute
Second
Frame
Zero
Absolute
minute
Absolute
second
Absolute
frame
Datapath Control Register 1—Address 1100010 (0x62)
Table 92. Datapath Control Register 1 Bit Map
7
SRC1
6
SRC0
5
REC2
4
REC1
3
REC0
Table 93. Datapath Control Register 1 Bit Descriptions
Bit Name
SRC[1:0]
REC[2:0]
AUXO[2:0]
Description
Datapath source select for sample rate converter (SRC).
00 = ADC.
01 = DIR.
10 = Playback.
11 = Auxiliary in.
Datapath source select for record output port.
000 = ADC.
001 = DIR.
010 = Playback.
011 = Auxiliary in.
100 = SRC.
Datapath source select for auxiliary output port.
000 = ADC.
001 = DIR.
010 = Playback.
011 = Auxiliary in.
100 = SRC.
Rev. A | Page 45 of 60
2
AUXO2
1
AUXO1
0
AUXO0
ADAV801
Datapath Control Register 2—Address 1100011 (0x63)
Table 94. Datapath Control Register 2 Bit Map
7
Reserved
6
Reserved
5
DAC2
4
DAC1
3
DAC0
2
DIT2
1
DIT1
0
DIT0
3
POL1
2
POL0
1
MUTER
0
MUTEL
Table 95. Datapath Control Register 2 Bit Descriptions
Bit Name
DAC[2:0]
DIT[2:0]
Description
Datapath source select for DAC.
00 = ADC.
01 = DIR.
10 = Playback.
11 = Auxiliary in.
100 = SRC.
Datapath source select for DIT.
000 = ADC.
001 = DIR.
010 = Playback.
011 = Auxiliary in.
100 = SRC.
DAC Control Register 1—Address 1100100 (0x64)
Table 96. DAC Control Register 1 Bit Map
7
DR_ALL
6
DR_DIG
5
CHSEL1
4
CHSEL0
Table 97. DAC Control Register 1 Bit Descriptions
Bit Name
DR_ALL
DR_DIG
CHSEL[1:0]
POL[1:0]
MUTER
MUTEL
Description
Hard reset and power-down.
0 = Normal, output pins go to VREF level.
1 = Hard reset and low power, output pins go to AGND.
DAC digital reset.
0 = Normal.
1 = Reset all except registers.
DAC channel select.
00 = Normal, left-right.
01 = Both right.
10 = Both left.
11 = Swapped, right-left.
DAC channel polarity.
00 = Both positive.
01 = Left negative.
10 = Right negative.
11 = Both negative.
Mute right channel.
0 = Mute.
1 = Normal.
Mute left channel.
0 = Mute.
1 = Normal.
Rev. A | Page 46 of 60
ADAV801
DAC Control Register 2—Address 1100101 (0x65)
Table 98. DAC Control Register 2 Bit Map
7
Reserved
6
Reserved
5
DMCLK1
4
DMCLK0
3
DFS1
2
DFS0
1
DEEM1
0
DEEM0
3
Reserved
2
ZFVOL
1
ZFDATA
0
ZFPOL
Table 99. DAC Control Register 2 Bit Descriptions
Bit Name
DMCLK[1:0]
DFS[1:0]
DEEM[1:0]
Description
DAC MCLK divider.
00 = MCLK.
01 = MCLK/1.5.
10 = MCLK/2.
11 = MCLK/3.
DAC interpolator select.
00 = 8 × (MCLK = 256 × fS).
01 = 4 × (MCLK = 128 × fS).
10 = 2 × (MCLK = 64 × fS).
11 = Reserved.
DAC de-emphasis select.
00 = None.
01 = 44.1 kHz.
10 = 32 kHz.
11 = 48 kHz.
DAC Control Register 3—Address 1100110 (0x66)
Table 100. DAC Control Register 3 Bit Map
7
Reserved
6
Reserved
5
Reserved
4
Reserved
Table 101. DAC Control Register 3 Bit Descriptions
Bit Name
ZFVOL
ZFDATA
ZFPOL
Description
DAC zero flag on mute and zero volume.
0 = Enabled.
1 = Disabled.
DAC zero flag on zero data disable.
0 = Enabled.
1 = Disabled.
DAC zero flag polarity.
0 = Active low.
1 = Active high.
Rev. A | Page 47 of 60
ADAV801
DAC Control Register 4—Address 1100111 (0x67)
Table 102. DAC Control Register 4 Bit Map
7
Reserved
6
INTRPT
5
ZEROSEL1
4
ZEROSEL0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Table 103. DAC Control Register 4 Bit Descriptions
Bit Name
INTRPT
ZEROSEL[1:0]
Description
This bit selects the functionality of the ZEROL/INT pin.
0 = Pin functions as a ZEROL flag pin.
1 = Pin functions as an interrupt pin.
These bits control the functionality of the ZEROR pin when the ZEROL/INT pin is used as an interrupt.
00 = Pin functions as a ZEROR flag pin.
01 = Pin functions as a ZEROL flag pin.
10 = Pin is asserted when either the left or right channel is zero.
11 = Pin is asserted when both the left and right channels are zero.
DAC Left Volume—Address 1101000 (0x68)
Table 104. DAC Left Volume Register Bit Map
7
DVOLL7
6
DVOLL6
5
DVOLL5
4
DVOLL4
3
DVOLL3
2
DVOLL2
1
DVOLL1
0
DVOLL0
3
DVOLR3
2
DVOLR2
1
DVOLR1
0
DVOLR0
3
DLP3
2
DLP2
1
DLP1
0
DLP0
Table 105. DAC Left Volume Register Bit Descriptions
Bit Name
DVOLL[7:0]
Description
DAC left channel volume control.
1111111 = 0 dBFS.
1111110 = −0.375 dBFS.
0000000 = −95.625 dBFS.
DAC Right Volume—Address 1101001 (0x69)
Table 106. DAC Right Volume Register Bit Map
7
DVOLR7
6
DVOLR6
5
DVOLR5
4
DVOLR4
Table 107. DAC Right Volume Register Bit Descriptions
Bit Name
DVOLR[7:0]
Description
DAC right channel volume control.
1111111 = 0 dBFS.
1111110 = −0.375 dBFS.
0000000 = −95.625 dBFS.
DAC Left Peak Volume—Address 1101010 (0x6A)
Table 108. DAC Left Peak Volume Register Bit Map
7
Reserved
6
Reserved
5
DLP5
4
DLP4
Table 109. DAC Left Peak Volume Register Bit Descriptions
Bit Name
DLP[5:0]
Description
DAC left channel peak volume detection.
000000 = 0 dBFS.
000001 = −1 dBFS.
111111 = −63 dBFS.
Rev. A | Page 48 of 60
ADAV801
DAC Right Peak Volume—Address 1101011 (0x6B)
Table 110. DAC Right Peak Volume Register Bit Map
7
Reserved
6
Reserved
5
DRP5
4
DRP4
3
DRP3
2
DRP2
1
DRP1
0
DRP0
3
AGL3
2
AGL2
1
AGL1
0
AGL0
3
AGR3
2
AGR2
1
AGR1
0
AGR0
Table 111. DAC Right Peak Volume Register Bit Descriptions
Bit Name
DRP[5:0]
Description
DAC right channel peak volume detection.
000000 = 0 dBFS.
000001 = −1 dBFS.
111111 = −63 dBFS.
ADC Left Channel PGA Gain—Address 1101100 (0x6C)
Table 112. ADC Left Channel PGA Gain Register Bit Map
7
Reserved
6
Reserved
5
AGL5
4
AGL4
Table 113. ADC Left Channel PGA Gain Register Bit Descriptions
Bit Name
AGL[5:0]
Description
PGA left channel gain control.
000000 = 0 dB.
000001 = 0.5 dB.
…
101111 = 23.5 dB.
110000 = 24 dB.
…
111111 = 24 dB.
ADC Right Channel PGA Gain—Address 1101101 (0x6D)
Table 114. ADC Right Channel PGA Gain Register Bit Map
7
Reserved
6
Reserved
5
AGR5
4
AGR4
Table 115. ADC Right Channel PGA Gain Register Bit Descriptions
Bit Name
AGR[5:0]
Description
PGA right channel gain control.
000000 = 0 dB.
000001 = 0.5 dB.
…
101111 = 23.5 dB.
110000 = 24 dB.
…
111111 = 24 dB.
Rev. A | Page 49 of 60
ADAV801
ADC Control Register 1—Address 1101110 (0x6E)
Table 116. ADC Control Register 1 Bit Map
7
AMC
6
HPF
5
PWRDWN
4
ANA_PD
3
MUTER
2
MUTEL
1
PLPD
0
PRPD
3
Reserved
2
Reserved
1
MCD1
0
MCD0
Table 117. ADC Control Register 1 Bit Descriptions
Bit Name
AMC
HPF
PWRDWN
ANA_PD
MUTER
MUTEL
PLPD
PRPD
Description
ADC modulator clock.
0 = ADC MCLK/2 (128 × fS).
1 = ADC MCLK/4 (64 × fS).
High-pass filter enable.
0 = Normal.
1 = HPF enabled.
ADC power-down.
0 = Normal.
1 = Power-down.
ADC analog section power-down.
0 = Normal.
1 = Power-down.
Mute ADC right channel.
0 = Normal.
1 = Muted.
Mute ADC left channel.
0 = Normal.
1 = Muted.
PGA left power-down.
0 = Normal.
1 = Power-down.
PGA right power-down.
0 = Normal.
1 = Power-down.
ADC Control Register 2—Address 1101111 (0x6F)
Table 118. ADC Control Register 2 Bit Map
7
Reserved
6
Reserved
5
Reserved
4
BUF_PD
Table 119. ADC Control Register 2 Bit Descriptions
Bit Name
BUF_PD
MCD[1:0]
Description
Reference buffer power-down control.
0 = Normal.
1 = Power-down.
ADC master clock divider.
00 = Divide by 1.
01 = Divide by 2.
10 = Divide by 3.
11 = Divide by 1.
Rev. A | Page 50 of 60
ADAV801
ADC Left Volume—Address 1110000 (0x70)
Table 120. ADC Left Volume Register Bit Map
7
AVOLL7
6
AVOLL6
5
AVOLL5
4
AVOLL4
3
AVOLL3
2
AVOLL2
1
AVOLL1
0
AVOLL0
3
AVOLR3
2
AVOLR2
1
AVOLR1
0
AVOLR0
3
ALP3
2
ALP2
1
ALP1
0
ALP0
3
ARP3
2
ARP2
1
ARP1
0
ARP0
Table 121. ADC Left Volume Register Bit Descriptions
Bit Name
AVOLL[7:0]
Description
ADC left channel volume control.
1111111 = 1.0 (0 dBFS).
1111110 = 0.996 (−0.00348 dBFS).
1000000 = 0.5 (−6 dBFS).
0111111 = 0.496 (−6.09 dBFS).
0000000 = 0.0039 (−48.18 dBFS).
ADC Right Volume—Address 1110001 (0x71)
Table 122. ADC Right Volume Register Bit Map
7
AVOLR7
6
AVOLR6
5
AVOLR5
4
AVOLR4
Table 123. ADC Right Volume Register Bit Descriptions
Bit Name
AVOLR[7:0]
Description
ADC right channel volume control.
1111111 = 1.0 (0 dBFS).
1111110 = 0.996 (−0.00348 dBFS).
1000000 = 0.5 (−6 dBFS).
0111111 = 0.496 (−6.09 dBFS).
0000000 = 0.0039 (−48.18 dBFS).
ADC Left Peak Volume—Address 1110010 (0x72)
Table 124. ADC Left Peak Volume Register Bit Map
7
Reserved
6
Reserved
5
ALP5
4
ALP4
Table 125. ADC Left Peak Volume Register Bit Descriptions
Bit Name
ALP[5:0]
Description
ADC left channel peak volume detection.
000000 = 0 dBFS.
000001 = −1 dBFS.
111111 = −63 dBFS.
ADC Right Peak Volume—Address 1110011 (0x73)
Table 126. ADC Right Peak Volume Register Bit Map
7
Reserved
6
Reserved
5
ARP5
4
ARP4
Table 127. ADC Right Peak Volume Register Bit Descriptions
Bit Name
ARP[5:0]
Description
ADC right channel peak volume detection.
000000 = 0 dBFS.
000001 = −1 dBFS.
111111 = −63 dBFS.
Rev. A | Page 51 of 60
ADAV801
PLL Control Register 1—Address 1110100 (0x74)
Table 128. PLL Control Register 1 Bit Map
7
DIRIN_CLK1
6
DIRIN_CLK0
5
MCLKODIV
4
PLLDIV
3
PLL2PD
Table 129. PLL Control Register 1 Bit Descriptions
Bit Name
DIRIN_CLK[1:0]
MCLKODIV
PLLDIV
PLL2PD
PLL1PD
XTLPD
SYSCLK3
Description
Recovered S/PDIF clock sent to SYSCLK3.
00 = SYSCLK3 comes from PLL block.
01 = Reserved.
10 = Reserved.
11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN.
Divide input MCLK by 2 to generate MCLKO.
0 = Disabled.
1 = Enabled.
Divide XIN by 2 to generate the PLL master clock.
0 = Disabled.
1 = Enabled.
Power-down PLL2.
0 = Normal.
1 = Power-down.
Power-down PLL1.
0 = Normal.
1 = Power-down.
Power-down XTAL oscillator.
0 = Normal.
1 = Power-down.
Clock output for SYSCLK3.
0 = 512 × fS.
1 = 256 × fS.
Rev. A | Page 52 of 60
2
PLL1PD
1
XTLPD
0
SYSCLK3
ADAV801
PLL Control Register 2—Address 1110101 (0x75)
Table 130. PLL Control Register 2 Bit Map
7
FS2_1
6
FS2_0
5
SEL2
4
DOUB2
3
FS1
Table 131. PLL Control Register 2 Bit Descriptions
Bit Name
FS2_[1:0]
SEL2
DOUB2
FS[1:0]
SEL1
DOUB1
Description
Sample rate select for PLL2.
00 = 48 kHz.
01 = Reserved.
10 = 32 kHz.
11 = 44.1 kHz.
Oversample ratio select for PLL2.
0 = 256 × fS.
1 = 384 × fS.
Double-selected sample rate on PLL2.
0 = Disabled.
1 = Enabled.
Sample rate select for PLL1.
00 = 48 kHz.
01 = Reserved.
10 = 32 kHz.
11 = 44.1 kHz.
Oversample ratio select for PLL1.
0 = 256 × fS.
1 = 384 × fS.
Double-selected sample rate on PLL1.
0 = Disabled.
1 = Enabled.
Rev. A | Page 53 of 60
2
FS0
1
SEL1
0
DOUB1
ADAV801
Internal Clocking Control Register 1—Address 1110110 (0x76)
Table 132. Internal Clocking Control Register 1 Bit Map
7
DCLK2
6
DCLK1
5
DCLK0
4
ACLK2
3
ACLK1
2
ACLK0
1
ICLK2_1
0
ICLK2_0
3
ICLK1_0
2
PLL2INT1
1
PLL2INT0
0
PLL1INT
Table 133. Internal Clocking Control Register 1 Bit Descriptions
Bit Name
DCLK[2:0]
ACLK[2:0]
ICLK2_[1:0]
Description
DAC clock source select.
000 = XIN.
001 = MCLKI.
010 = PLLINT1.
011 = PLLINT2.
100 = DIR PLL (512 × fS).
101 = DIR PLL (256 × fS).
110 = XIN.
111 = XIN.
ADC clock source select.
000 = XIN.
001 = MCLKI.
010 = PLLINT1.
011 = PLLINT2.
100 = DIR PLL (512 × fS).
101 = DIR PLL (256 × fS).
110 = XIN.
111 = XIN.
Source selector for internal clock ICLK2.
00 = XIN.
01 = MCLKI.
10 = PLLINT1.
11 = PLLINT2.
Internal Clocking Control Register 2—Address 1110111 (0x77)
Table 134. Internal Clocking Control Register 2 Bit Map
7
Reserved
6
Reserved
5
Reserved
4
ICLK1_1
Table 135. Internal Clocking Control Register 2 Bit Descriptions
Bit Name
ICLK1_[1:0]
PLL2INT[1:0]
PLL1INT
Description
Source selector for internal clock ICLK1.
00 = XIN.
01 = MCLKI.
10 = PLLINT1.
11 = PLLINT2.
PLL2 internal selector (see Figure 38).
00 = FS2.
01 = FS2/2.
10 = FS3.
11 = FS3/2.
PLL1 internal selector.
0 = FS1.
1 = FS1/2.
Rev. A | Page 54 of 60
ADAV801
PLL Clock Source Register—Address 1111000 (0x78)
Table 136. PLL Clock Source Register Bit Map
7
PLL2_Source
6
PLL1_Source
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
3
Reserved
2
SYSCLK1
1
SYSCLK2
0
SYSCLK3
Table 137. PLL Clock Source Register Bit Descriptions
Bit Name
PLL2_Source
PLL1_Source
Description
Selects the clock source for PLL2.
0 = XIN.
1 = MCLKI.
Selects the clock source for PLL1.
0 = XIN.
1 = MCLKI
PLL Output Enable—Address 1111010 (0x7A)
Table 138. PLL Output Enable Register Bit Map
7
Reserved
6
Reserved
5
DIRINPD
4
DIRIN_PIN
Table 139. PLL Output Enable Register Bit Descriptions
Bit Name
DIRINPD
DIRIN_PIN
SYSCLK1
SYSCLK2
SYSCLK3
Description
This bit powers down the S/PDIF receiver.
0 = Normal.
1 = Power-down.
This bit determines the input levels of the DIRIN pin.
0 = DIRIN accepts input signals down to 200 mV according to AES3 requirements.
1 = DIRIN accepts input signals as defined in the Specifications section.
Enables the SYSCLK1 output.
0 = Enabled.
1 = Disabled.
Enables the SYSCLK2 output.
0 = Enabled.
1 = Disabled.
Enables the SYSCLK3 output.
0 = Enabled.
1 = Disabled.
Rev. A | Page 55 of 60
ADAV801
ALC Control Register 1—Address 1111011 (0x7B)
Table 140. ALC Control Register 1 Bit Map
7
FSSEL1
6
FSSEL0
5
GAINCNTR1
4
GAINCNTR0
3
RECMODE1
2
RECMODE0
Table 141. ALC Control Register 1 Bit Descriptions
Bit Name
FSSEL[1:0]
GAINCNTR[1:0]
RECMODE[1:0]
LIMDET
ALCEN
Description
These bits should equal the sample rate of the ADC.
00 = 96 kHz.
01 = 48 kHz.
10 = 32 kHz.
11 = Reserved.
These bits determine the limit of the counter used in limited recovery mode.
00 = 3.
01 = 7.
10 = 15.
11 = 31.
These bits determine which recovery mode is used by the ALC section.
00 = No recovery.
01 = Normal recovery.
10 = Limited recovery.
11 = Reserved.
These bits limit detect mode.
0 = ALC is used when either channel exceeds the set limit.
1 = ALC is used only when both channels exceed the set limit.
These bits enable ALC.
0 = Disable ALC.
1 = Enable ALC.
Rev. A | Page 56 of 60
1
LIMDET
0
ALCEN
ADAV801
ALC Control Register 2— Address = 1111100 (0x7C)
Table 142. ALC Control Register 2 Bit Map
7
Reserved
6
RECTH1
5
RECTH0
4
ATKTH1
3
ATKTH0
2
RECTIME1
1
RECTIME0
0
ATKTIME
3
ALC RESET
2
ALC RESET
1
ALC RESET
0
ALC RESET
Table 143. ALC Control Register 2 Bit Descriptions
Bit Name
RECTH[1:0]
ATKTH[1:0]
RECTIME[1:0]
ATKTIME
Description
Recovery threshold.
00 = −2 dB.
01 = −3 dB.
10 = −4 dB.
11 = −6 dB.
Attack threshold.
00 = 0 dB.
01 = −1 dB.
10 = −2 dB.
11 = −4 dB.
Recovery time selection.
00 = 32 ms.
01 = 64 ms.
10 = 128 ms.
11 = 256 ms.
Attack timer selection.
0 = 1 ms.
1 = 4 ms.
ALC Control Register 3—Address 1111101 (0x7D)
Table 144. ALC Control Register 3 Bit Map
7
ALC RESET
6
ALC RESET
5
ALC RESET
4
ALC RESET
Table 145. ALC Control Register 3 Bit Description
Bit Name
ALC RESET
Description
A write to this register restarts the ALC operation. The value written to this register is irrelevant. A read from this
register gives the gain reduction factor.
Rev. A | Page 57 of 60
ADAV801
LAYOUT CONSIDERATIONS
Getting the best performance from the ADAV801 requires a
careful layout of the printed circuit board (PCB). Using separate
analog and digital ground planes is recommended, because
these give the currents a low resistance path back to the power
supplies. The ground planes should be connected in only one
place, usually under the ADAV801, to prevent ground loops.
The analog and digital supply pins should be decoupled to their
respective ground pins with a 10 μF to 47 μF tantalum capacitor
and a 0.1 μF ceramic capacitor. These capacitors should be
placed as close as possible to the supply pins.
ADC
The ADC uses a switch capacitor input stage and is, therefore,
particularly sensitive to digital noise. Sources of noise, such as
PLLs or clocks, should not be routed close to the ADC section.
The CAPxN and CAPxP pins form a charge reservoir for the
switched capacitor section of the ADC, so keeping these nodes
electrically quiet is a key factor in ensuring good performance.
The capacitors connected to these pins should be of good
quality, either NPO or COG, and should be placed as close as
possible to CAPxN and CAPxP.
The PLL has its own power supply pins. To get the best
performance from the PLL and from the rest of the ADAV801,
it is recommended that a separate analog supply be used. Where
this is not possible, the user must decide whether to connect the
PLL supply to the analog (AVDD) or digital (DVDD) supply.
Connecting the PLL supply to AVDD gives the best jitter
performance, but can degrade the performance of the ADC and
DAC sections slightly due to the increased digital noise created
on the AVDD by the PLL. Connecting the PLL supply to DVDD
keeps digital noise away from the analog supply, but the jitter
specifications might be reduced depending on the quality of the
digital supply. Using the layout recommendations described in
this section helps to reduce these effects.
RESET AND POWER-DOWN CONSIDERATIONS
The DAC requires an analog filter to filter out-of-band noise
from the analog output. A third-order Bessel filter is
recommended, although the filter to use depends on the
requirements of the application.
When the ADAV801 is held in reset by bringing the RESET
pin low, a number of circuit blocks remain powered up. For
example, the crystal oscillator circuit based around the XIN
and XOUT pins is still active, so that a stable clock source is
available when the ADAV801 is taken out of reset. In addition,
the VCO associated with the S/PDIF receiver is active so that
the receiver locks to the incoming S/PDIF stream in the shortest
possible time. Where power consumption is a concern, the
individual blocks of the ADAV801 can be powered down via
the control registers to gain significant power savings. Table 146
shows typical power savings when using the power-down bits
in the control registers.
PLL
Table 146. Typical Power Requirements
DAC
The PLL can be used to generate digital clocks, either for use
internally or to clock external circuitry. Because every clock is a
potential source of noise, care should be taken when using the
PLL. The ADAV801’s PLL outputs can be enabled or disabled,
as required. If the PLL clocks are not required by external
circuitry, it is recommended that the outputs be disabled. To
reduce cross-coupling between clocks, a digital ground trace
can be routed on either side of the PLL clock signal, if required.
Operating
Mode
Normal
Reset low
Power-down
bits
Rev. A | Page 58 of 60
AVDD
(mA)
50
30
12
DVDD
(mA)
25
4
0.1
ODVDD
(mA)
5
2.5
1.3
DIR_VDD
(mA)
5
1
0.7
Power
(mW)
280.5
123.75
46.53
ADAV801
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
32
17
VIEW A
VIEW A
0.50
BSC
LEAD PITCH
ROTATED 90° CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
1.45
1.40
1.35
Figure 57. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADAV801ASTZ 1
ADAV801ASTZ-REEL1
EVAL-ADAV801EBZ1
1
Temperature
Range
−40°C to +85°C
−40°C to +85°C
Control
Interface
SPI
SPI
DAC Outputs
Single-Ended
Single-Ended
Package Description
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 59 of 60
Package
Option
ST-64-2
ST-64-2
ADAV801
NOTES
©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04577-0-7/07(A)
Rev. A | Page 60 of 60
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