AD AD5700-1BCPZ-R5 Low power hart modem Datasheet

Low Power HART Modem
AD5700/AD5700-1
Data Sheet
FEATURES
GENERAL DESCRIPTION
HART-compliant fully integrated FSK modem
1200 Hz and 2200 Hz sinusoidal shift frequencies
115 µA maximum supply current in receive mode
Suitable for intrinsically safe applications
Integrated receive band-pass filter
Minimal external components required
Clocking optimized for various system configurations
Ultralow power crystal oscillator (60 µA maximum)
External CMOS clock source
Precision internal oscillator (AD5700-1 only)
Buffered HART output—extra drive capability
8 kV HBM ESD rating
1.71 V to 5.5 V power supply
1.71 V to 5.5 V interface
−40°C to +125°C operation
4 mm × 4 mm LFCSP package
HART physical layer compliant
UART interface
The AD5700/AD5700-1 are single-chip solutions, designed
and specified to operate as a HART® FSK half-duplex modem,
complying with the HART physical layer requirements. The
AD5700/AD5700-1 integrate all of the necessary filtering, signal
detection, modulating, demodulating and signal generation
functions, thus requiring few external components. The 0.5%
precision internal oscillator on the AD5700-1 greatly reduces
the board space requirements, making it ideal for line-powered
applications in both master and slave configurations. The maximum supply current consumption is 115 µA, making the AD5700/
AD5700-1 an optimal choice for low power loop-powered applications. Transmit waveforms are phase continuous 1200 Hz and
2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate
carrier detect circuitry and use a standard UART interface.
Table 1. Related Products
Part No.
AD5755-1
APPLICATIONS
AD5421
AD5410/
AD5420
AD5412/
AD5422
Field transmitters
HART multiplexers
PLC and DCS analog I/O modules
HART network connectivity
Description
Quad-channel, 16-bit, serial input, 4 mA to 20 mA and
voltage output DAC, dynamic power control, HART
connectivity
16-bit, serial input, loop powered, 4 mA to 20 mA DAC
Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA
current source DACs
Single-channel, 12-bit/16-bit, serial input, current
source and voltage output DACs
FUNCTIONAL BLOCK DIAGRAM
REG_CAP
VCC
CLKOUT XTAL1 XTAL2 XTAL_EN
IOVCC
OSC
DUPLEX
BUFFER
TXD
RTS
CONTROL LOGIC
CD
RXD
AD5700/AD5700-1
FSK
MODULATOR
HART_OUT
DAC
ADC_IP
FSK
DEMODULATOR
CLK_CFG0
BAND-PASS
FILTER AND
BIASING
ADC
HART_IN
VOLTAGE
REFERENCE
RESET
DGND
REF REF_EN
AGND
FILTER_SEL
10435-001
CLK_CFG1
Figure 1.
Rev. D
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AD5700/AD5700-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
FSK Modulator ........................................................................... 13
Applications ....................................................................................... 1
Connecting to HART_OUT ..................................................... 14
General Description ......................................................................... 1
FSK Demodulator ...................................................................... 14
Functional Block Diagram .............................................................. 1
Connecting to HART_IN or ADC_IP .................................... 14
Revision History ............................................................................... 2
Clock Configuration .................................................................. 15
Specifications..................................................................................... 3
Supply Current Calculations ..................................................... 16
Timing Characteristics ................................................................ 5
Power-Down Mode .................................................................... 16
Absolute Maximum Ratings............................................................ 6
Full Duplex Operation ............................................................... 16
Thermal Resistance ...................................................................... 6
Applications Information .............................................................. 17
ESD Caution .................................................................................. 6
Supply Decoupling ..................................................................... 17
Pin Configuration and Function Descriptions ............................. 7
Transient Voltage Protection .................................................... 17
Typical Performance Characteristics ............................................. 9
Typical Connection Diagrams .................................................. 18
Terminology .................................................................................... 12
Outline Dimensions ....................................................................... 21
Theory of Operation ...................................................................... 13
Ordering Guide .......................................................................... 21
REVISION HISTORY
5/13—Rev. C to Rev. D
2/13—Rev. B to Rev. C
Changed 2 V to 5.5 V Power Supply to 1.71 V to 5.5 V Power
Supply, Features Section .................................................................. 1
Changes to Summary Statement, VCC Parameter, and Internal
Reference Voltage Parameter Test Conditions/Comments,
Table 2 ................................................................................................ 3
Changed VCC = 2 V to 5.5 V to VCC = 1.71 V to 5.5 V in the
Summary Statement, Table 3 ........................................................... 5
Changes to Pin 18 Description and EPAD Mnemonic and
Description, Table 6.......................................................................... 7
Changes to Figure 9 and Figure 13 ............................................... 10
Changes to Figure 28 ...................................................................... 18
Change to Figure 30 ....................................................................... 20
7/12—Rev. A to Rev. B
Removed VCC and IOVCC Current Consumption Text, Table 2 .. 3
Added Internal Oscillator and External Clock Parameters
to Table 2 ............................................................................................ 4
Changes to t2 Description and Endnote 2, Table 3........................5
Changes to IOVCC Description, Table 6 ..........................................7
Added Supply Current Calculations Section .............................. 16
Added Transient Voltage Protection Section, Figure 26, and
Figure 27; Renumbered Sequentially ........................................... 17
Changes to Typical Connection Diagrams Section ................... 18
Changes to Figure 29...................................................................... 19
Changes to Figure 30...................................................................... 20
Updated Outline Dimensions ....................................................... 21
4/12—Rev. 0 to Rev. A
Change to Transmit Impedance Parameter, RTS Low, Table 2 ...4
Changes to Figure 3, Figure 4, Figure 5, and Figure 7 ..................9
Changes to Figure 10 and Figure 11 ............................................ 10
Changed AD5755 to AD5755-1 Throughout ............................. 17
Change to Figure 27 ....................................................................... 18
2/12—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet
AD5700/AD5700-1
SPECIFICATIONS
VCC = 1.71 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, AGND = DGND, CLKOUT disabled, HART_OUT with 5 nF load, internal and external
receive filter, internal reference; all specifications are from −40°C to +125°C and relate to both A and B models, unless otherwise noted.
Table 2.
Parameter 1
POWER REQUIREMENTS 2
VCC
IOVCC
VCC and IOVCC Current Consumption
Demodulator
Min
Typ
Max
Unit
5.5
5.5
V
V
115
179
97
µA
µA
µA
157
µA
260
140
193
96
µA
µA
µA
µA
153
µA
270
60
71
285
µA
µA
µA
µA
16
35
75
µA
µA
1.5
1.52
V
1.71
1.71
86
69
Modulator
124
73
Crystal Oscillator 3
33
44
218
Internal Oscillator 4
Power-Down Mode
INTERNAL VOLTAGE REFERENCE
Internal Reference Voltage
Load Regulation
OPTIONAL EXTERNAL VOLTAGE
REFERENCE
External Reference Input Voltage
1.47
18
2.47
ppm/µA
Test Conditions/Comments
B model, external clock, −40°C to +85°C
B model, external clock, −40°C to +125°C
B model, external clock, −40°C to +85°C,
external reference
B model, external clock, −40°C to +125 °C,
external reference
A model, external clock, −40°C to +125°C
B model, external clock, −40°C to +85°C
B model, external clock, −40°C to +125°C
B model, external clock, −40°C to +85°C,
external reference
B model, external clock, −40°C to +125°C,
external reference
A model, external clock, −40°C to +125°C
External crystal, 16 pF at XTAL1 and XTAL2
External crystal, 36 pF at XTAL1 and XTAL2
AD5700-1 only, external crystal not required
RESET = REF_EN = DGND
Internal reference disabled, −40°C to +85°C
Internal reference disabled, −40°C to +125°C
REF_EN = IOVCC to enable use of internal
reference; VCC = 1.71 V minimum
Tested with 50 µA load
2.5
2.53
V
REF_EN = DGND to enable use of external
reference, VCC = 2.7 V minimum
16
21
µA
Modulator
28
33
µA
Internal Oscillator
5.5
7
µA
Current required by external reference in
receive mode
Current required by external reference in
transmit mode
Current required by external reference if
using internal oscillator
4.6
8.6
µA
0.3 × IOVCC
+0.1
V
V
µA
pF
External Reference Input Current
Demodulator
Power-Down
DIGITAL INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Input Capacitance 5
0.7 × IOVCC
−0.1
5
Rev. D | Page 3 of 24
Per pin
AD5700/AD5700-1
Parameter 1
DIGITAL OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
CD Assert 6
HART_IN INPUT5
Input Voltage Range
HART_OUT OUTPUT
Output Voltage
Mark Frequency 7
Space Frequency7
Frequency Error
Data Sheet
Min
85
Unit
100
0.4
110
V
V
mV p-p
REF
1.5
V
V
External reference source
Internal reference enabled
505
mV p-p
AC-coupled (2.2 µF), measured at HART_OUT
pin with 160 Ω load (worst-case load), see
Figure 15 and Figure 16 for HART_OUT
voltage vs. load
Internal oscillator
Internal oscillator
Internal oscillator, −40°C to +85°C
Internal oscillator, −40°C to +125°C
0
0
459
493
1200
2200
Test Conditions/Comments
160
Hz
Hz
%
%
Degrees
Ω
7
70
Ω
kΩ
Worst-case load is 160 Ω, ac-coupled with
2.2 µF, see Figure 19 for recommended
configuration if driving a resistive load
RTS low, at the HART_OUT pin
RTS high, at the HART_OUT pin
−40°C to +85°C
−40°C to +125°C
−0.5
−1
Transmit Impedance
EXTERNAL CLOCK
External Clock Source Frequency
Max
IOVCC − 0.5
Phase Continuity Error5
Maximum Load Current5
INTERNAL OSCILLATOR
Frequency
Typ
+0.5
+1
0
1.2226
1.2165
1.2288
1.2288
1.2349
1.2411
MHz
MHz
3.6496
3.6864
3.7232
MHz
Temperature range: −40°C to +125°C; typical at 25°C.
Current consumption specifications are based on mean current values.
3
The demodulator and modulator currents are specified using an external clock. If using an external crystal oscillator, the crystal oscillator current specification must be
added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode.
4
The demodulator and modulator currents are specified using an external clock. If using the internal oscillator, the internal oscillator current specification must be
added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode.
5
Guaranteed by design and characterization, but not production tested.
6
Specification set assuming a sinusoidal input signal containing preamble characters at the input and an ideal external filter (see Figure 21).
7
If the internal oscillator is not used, frequency accuracy is dependent on the accuracy of the crystal or clock source used.
1
2
Rev. D | Page 4 of 24
Data Sheet
AD5700/AD5700-1
TIMING CHARACTERISTICS
VCC = 1.71 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1
t1
Limit at TMIN, TMAX
1
Unit
Bit time 2 max
t2
1
Bit time2 max
t3
1
Bit time2 max
t4
t5
t6
6
6
10
Bit times2 max
Bit times2 max
Bit times2 max
t7
2.1
ms typ
t8
t9
6
25
ms typ
µs typ
t10
t11
10
30
ms typ
µs typ
1
2
Description
Carrier start time. Time from RTS falling edge to carrier reaching its first peak. See
Figure 3.
Carrier stop time. Time from RTS rising edge to carrier amplitude dropping below
the minimum receive amplitude.
Carrier decay time. Time from RTS rising edge to carrier amplitude dropping to ac
zero. See Figure 4.
Carrier detect on. Time from carrier on to CD rising edge. See Figure 5.
Carrier detect off. Time from carrier off to CD falling edge. See Figure 6.
Carrier detect on when switching from transmit mode to receive mode in the
presence of a constant valid carrier. Time from RTS rising edge to CD rising edge.
See Figure 7.
Crystal oscillator power-up time. On application of a valid power supply voltage at
VCC or on enabling of the oscillator via the XTAL_EN pin. Crystal load capacitors =
8 pF.
Crystal oscillator power-up time. Crystal load capacitors = 18 pF.
Internal oscillator power-up time. On application of a valid power supply voltage
at VCC or on enabling of the oscillator via the CLK_CFG0 and CLK_CFG1 pins.
Reference power-up time.
Transition time from power-down mode to normal operating mode (external
clock source, external reference).
Specifications apply to AD5700/AD5700-1 configured with internal or external receive filter.
Bit time is the length of time to transfer one bit of data (1 bit time = 1/1200 Hz = 833.333 µs).
Rev. D | Page 5 of 24
AD5700/AD5700-1
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4.
Parameter
VCC to GND
IOVCC to GND
Digital Inputs to DGND
Digital Output to DGND
HART_OUT to AGND
HART_IN to AGND
ADC_IP
AGND to DGND
Operating Temperature Range (TA)
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
Power Dissipation
Lead Temperature,
Soldering
ESD
Human Body Model
(ANSI/ESDA/JEDEC JS-0012010)
Field Induced Charge Model
(JEDEC JESD22_C101E)
Machine Model
(ANSI/ESD S5.2-2009)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to +2.5 V
−0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to +0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
24-Lead LFCSP
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
(TJ MAX – TA)/θJA
JEDEC industry standard
J-STD-020
8 kV
1.5 kV
400 V
Rev. D | Page 6 of 24
θJA
30
θJC
3
Unit
°C/W
Data Sheet
AD5700/AD5700-1
20 XTAL2
19 AGND
21 XTAL1
22 DGND
24 FILTER_SEL
23 REF_EN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 VCC
XTAL_EN 1
CLKOUT 2
CLK_CFG0 3
AD5700/
AD5700-1
CLK_CFG1 4
TOP VIEW
(Not to Scale)
RESET 5
17 ADC_IP
16 HART_IN
15 REF
14 HART_OUT
CD 6
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED
TO AGND OR DGND, OR, ALTERNATIVELY, IT CAN
BE LEFT ELECTRICALLY UNCONNECTED. IT IS
RECOMMENDED THAT THE PADDLE BE THERMALLY
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
10435-002
DGND 12
IOVCC 11
9
RXD 10
DUPLEX
RTS 8
TXD 7
13 REG_CAP
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
XTAL_EN
2
CLKOUT
3
4
5
CLK_CFG0
CLK_CFG1
RESET
6
7
8
CD
TXD
RTS
9
DUPLEX
10
11
RXD
IOVCC
12
DGND
13
14
15
REG_CAP
HART_OUT
REF
16
HART_IN
17
ADC_IP
18
VCC
Description
Crystal Oscillator Circuit Enable. A low state enables the crystal oscillator circuit, and an external crystal is
required. A high state disables the crystal oscillator circuit, and an external clock source or the internal oscillator
(AD5700-1 only) provides the clock source. This pin is used in conjunction with the CLK_CFG0 and CLK_CFG1
pins in configuring the required clock generation scheme.
Clock Output. If using the crystal oscillator or the internal RC oscillator, a clock output can be configured at the
CLKOUT pin. Enabling the clock output consumes extra current to drive the load on this pin. See the CLKOUT
section for more details.
Clock Configuration Control. See Table 7.
Clock Configuration Control. See Table 7.
Active Low Digital Input. Holding RESET low places the AD5700/AD5700-1 in power-down mode. A high state on
RESET returns the AD5700/AD5700-1 to their power-on state. If not using this pin, tie this pin to IOVCC.
Carrier Detect—Digital Output. A high on CD indicates a valid carrier is detected.
Transmit Data—Digital Input. Data input to the modulator.
Request to Send—Digital Input. A high state enables the demodulator and disables the modulator. A low state
enables the modulator and disables the demodulator.
A high state on this pin enables full duplex operation. See the Theory of Operation section. A low state disables
this feature.
Receive Data—UART Interface Digital Data Output. Data output from the demodulator is accessed on this pin.
Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. The applied
voltage can be in the range of 1.71 V to 5.5 V. IOVCC should be decoupled to ground with low ESR 10 μF and
0.1 μF capacitors (see the Supply Decoupling section).
Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to
AGND.
Capacitor Connection for Internal Voltage Regulator. Connect a 1 μF capacitor from this pin to ground.
HART FSK Signal Output. See the FSK Modulator section and Figure 28 for typical connections.
Internal Reference Voltage Output, or External 2.5 V Reference Voltage Input. Connect a 1 μF capacitor from this
pin to ground. When supplying an external reference, the VCC supply requires a minimum voltage of 2.7 V.
HART FSK Signal. When using the internal filter, couple the HART input signal into this pin using a 2.2 nF series
capacitor. If using an external band-pass filter as shown in Figure 21, do not connect to this pin.
If using the internal band-pass filter, connect 680 pF to this pin. Alternatively, this pin allows direct connection to
the ADC input, in which case an external band-pass filter network must be used, as shown in Figure 21.
Power Supply Input. 1.71 V to 5.5 V can be applied to this pin. VCC should be decoupled to ground with low ESR
10 μF and 0.1 μF capacitors (see the Supply Decoupling section).
Rev. D | Page 7 of 24
AD5700/AD5700-1
Pin No.
19
20
Mnemonic
AGND
XTAL2
21
XTAL1
22
DGND
23
REF_EN
24
FILTER_SEL
EPAD
EPAD
Data Sheet
Description
Analog Circuitry Ground Reference Connection.
Connection for External 3.6864 MHz Crystal. Do not connect to this pin if using the internal RC oscillator
(AD5700-1 only) or an external clock source.
Connection for External 3.6864 MHz Crystal or External Clock Source Input. Tie this pin to ground if using the
internal RC oscillator (AD5700-1 only).
Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to
AGND.
Reference Enable. A high state enables the internal 1.5 V reference and buffer. A low state disables the internal
reference and input buffer, and a buffered external 2.5 V reference source must be applied at REF. If REF_EN is
tied low, VCC must be greater than 2.7 V.
Band-Pass Filter Select. A high state enables the internal filter and the HART signal should be applied to the
HART_IN pin. A low state disables the internal filter and an external band-pass filter must then be connected at
the ADC_IP input pin. In this case, the HART signal should be applied to the ADC_IP pin.
Exposed Pad. For typical operation, it is recommended to connect this pin to AGND.
Rev. D | Page 8 of 24
Data Sheet
AD5700/AD5700-1
TYPICAL PERFORMANCE CHARACTERISTICS
1.4
1.2
1.4
TA = 25°C; VCC = IOVCC = 3.3V; INT VREF
RTS AND TXD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
1.2
1.0
1.0
CD
RTS
HART SIGNAL (V)
0.8
HART_OUT (V)
TA = 25°C; VCC = IOVCC = 3.3V; INT VREF
CD AND RXD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
0.6
TXD
0.4
0.2
0.8
0.6
RXD
0.4
0.2
HART SIGNAL
0
0
HART_OUT
–0.2
0
0.3
0.6
0.9
1.2
TIME (ms)
1.5
1.8
2.1
–0.4
–5
10435-003
–0.4
–0.3
–4
Figure 3. Carrier Start Time
1.50
TA = 25°C; VCC = IOVCC = 3.3V; INT VREF
RTS AND TXD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
1.25
1.00
HART_OUT (V)
HART_OUT (V)
TXD
HART_OUT
0.2
0.50
CD
HART SIGNAL HAS ALSO
BEEN OFFSET BY –0.6V.
0.25
0
HART_OUT
–0.25
0
–0.50
–0.2
–0.75
–1.5
–1.0
–0.5
TIME (ms)
0
0.5
1.0
Figure 4. Carrier Stop/Decay Time
–7.5
–5.0
–2.5
TIME (ms)
0
2.5
Figure 7. Carrier Detect on When Switching from Transmit Mode to Receive
Mode in the Presence of a Constant Valid Carrier
1.4
100
TA = 25°C
90 VCC = IOVCC = 2.7V TO 5.5V
DEV 1 EXT REF
TA = 25°C; VCC = IOVCC = 3.3V; INT VREF
CD AND RXD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
80
SUPPLY CURRENT (µA)
CD
0.8
0.6
RXD
0.4
0.2
0
HART SIGNAL
–0.2
70
MOD ICC AND IOICC
DEMOD ICC AND IOICC
60
50
40
30
MOD IREF
20
DEMOD IREF
10
0
0.5
1.0
TIME (ms)
1.5
2.0
2.5
0
2.0
10435-005
–0.4
–0.5
HART SIGNAL
–1.00
–10
10435-004
–0.4
–2.0
HART SIGNAL (V)
TA = 25°C; VCC = IOVCC = 3.3V; INT VREF
RTS AND CD DC LEVELS HAVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
0.75
0.4
1.0
1
RTS
RTS
0.8
1.2
0
Figure 6. Carrier Detect Off Timing
1.0
0.6
–1
10435-007
1.2
–2
TIME (ms)
Figure 5. Carrier Detect On Timing
2.5
3.0
3.5
4.0
4.5
VCC = IOVCC (V)
5.0
5.5
6.0
10435-008
1.4
–3
10435-006
–0.2
Figure 8. Supply Currents vs. Supply Voltage—External Reference
Rev. D | Page 9 of 24
AD5700/AD5700-1
200
0
TA = 25°C
VCC = IOVCC = 1.71V TO 5.5V
DEV 1 INT REF
REG_CAP IS CONNECTED
TO VCC FOR SUPPLIES OF ≤ 2.0V
180
160
–2
TA = 25°C
VCC = IOVCC = 3.3V
INT VREF
–4
140
–6
GAIN (dB)
MOD ICC AND IOICC
100
80
DEMOD ICC AND IOICC
–8
–10
–12
60
–14
40
–16
20
–18
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VCC = IOVCC (V)
4.5
5.0
5.5
6.0
EXTERNAL FILTER
INTERNAL FILTER
–20
100
1k
FREQUENCY (Hz)
Figure 9. Supply Currents vs. Supply Voltage—Internal Reference
700
1.5012
TA = 25°C
1.5010 VCC = IOVCC = 1.71V TO 5.5V
1.5008
VREF INTERNAL (V)
500
ICC CURRENT (µA)
10k
Figure 12. Input Filter Frequency Response
TA = 25°C; VCC = IOVCC = 3.3V; INT VREF
CLK CONFIG = XTAL OSCILLATOR
IOICC = 41µA
600
10435-011
120
10435-026
ICC AND IOICC (µA)
Data Sheet
400
TXD = 1
TXD = 0
300
200
1.5006
1.5004
1.5002
1.5000
2.2µF
HART_OUT
1.4998
22nF
100
RLOAD
200
400
600
800
RLOAD (Ω) WITH 22nF TO GND
1000
1200
1.4994
1.0
Figure 10. Current in Tx Mode vs. Resistive Load
1.5004
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
5.5
6.0
VCC = IOVCC = 2.7V
TEMPERATURE = –40°C TO +125°C
1.5002
VREF INTERNAL (V)
175
150
125
100
75
1.5000
1.4998
1.4996
1.4994
TXD = 1
TXD = 0
50
0
0
10
20
30
40
50
CLOAD (nF)
60
1.4990
–40
Figure 11. Current in Tx Mode vs. Capacitive Load
–20
0
20
40
60
80
TEMPERATURE (°C)
100
Figure 14. Reference Voltage vs. Temperature
Rev. D | Page 10 of 24
120
10435-013
1.4992
25
10435-010
ICC CURRENT (µA)
1.5006
TA = 25°C; VCC = IOVCC = 3.3V; INT VREF
CLK CONFIG = XTAL OSCILLATOR
CAPACITIVE LOAD ONLY
IOICC = 41µA
200
2.0
Figure 13. Reference Voltage vs. VCC
250
225
1.5
10435-012
0
10435-009
1.4996
0
AD5700/AD5700-1
500
505
TA = 25°C
VCC = IOVCC = 3.3V
495 INT V
REF
504
HART_OUT (mV p-p)
485
1200Hz
2200Hz
480
475
2.2µF
HART_OUT
22nF
470
TA = 25°C
VCC = IOVCC = 3.3V
INT VREF
CAPACITIVE LOAD ONLY
503
490
502
501
500
499
1200Hz
2200Hz
498
497
RLOAD
0
200
400
600
800
RLOAD (Ω) || WITH 22nF TO GND
1000
1200
Figure 15. HART_OUT Voltage vs. RLOAD
495
0
10
20
30
CLOAD (nF)
40
Figure 16. HART_OUT Voltage vs. CLOAD
Rev. D | Page 11 of 24
50
60
10435-015
496
465
10435-014
HART_OUT (mV p-p)
Data Sheet
AD5700/AD5700-1
Data Sheet
TERMINOLOGY
VCC and IOVCC Current Consumption
This specification gives a summation of the current consumption of both the VCC and the IOVCC supplies. Figure 11 shows
separate measurements for VCC and IOVCC currents vs. varying
capacitive loads, in transmit mode.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/µA.
CD Assert
The minimum value at which the carrier detect signal asserts is
85 mV p-p and the maximum value it asserts at is 110 mV p-p. CD
is already high (asserted) for HART input signals greater than
110 mV p-p. This specification was set assuming a sinusoidal
input signal containing preamble characters at the input and an
ideal external filter (see Figure 21).
HART_OUT Output Voltage
This is the peak-to-peak HART_OUT output voltage. The
specification in Table 2 was set using a worst-case load of 160 Ω,
ac-coupled with a 2.2 µF capacitor. Figure 15 and Figure 16 show
HART_OUT output voltages for both resistive and purely
capacitive loads.
Mark/Space Frequency
A 1.2 kHz signal represents a digital 1, or mark, whereas a
2.2 kHz signal represents a 0, or space.
Phase Continuity Error
The DDS engine in this design inherently generates continuous
phase signals, thus avoiding any output discontinuity when
switching between frequencies. This attribute is desirable for
signals that are to be transmitted over a band limited channel,
because discontinuities in a signal introduce wideband frequency components. As the name suggests, for a signal to be
continuous, the phase continuity error must be 0o.
Rev. D | Page 12 of 24
Data Sheet
AD5700/AD5700-1
THEORY OF OPERATION
The AD5700/AD5700-1 either transmit or receive 1.2 kHz and
2.2 kHz carrier signals. A 1.2 kHz signal represents a digital 1,
or mark, whereas a 2.2 kHz signal represents a 0, or space.
There are three main clocking configurations supported by
these parts, two of which are available on the AD5700 option,
whereas all three are available on the AD5700-1 device:



The modulator converts a bit stream of UART-encoded HART
data at the TXD input to a sequence of 1200 Hz and 2200 Hz
tones (see Figure 17). This sinusoidal signal is internally buffered and output on the HART_OUT pin. The modulator is
enabled by bringing the RTS signal low.
"1" = MARK
1.2kHz
"0" = SPACE
2.2kHz
START
TXD
STOP
10435-016
HART_OUT
8-BIT DATA + PARITY
Figure 17. AD5700/AD5700-1 Modulator Waveform
The modulator block contains a DDS engine that produces a
1.2 kHz or 2.2 kHz sine wave in digital form and then performs
a digital-to-analog conversion. This DDS engine inherently
generates continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies. For more
information on DDS fundamentals, see MT-085, Fundamentals
of Direct Digital Synthesizers (DDS). Figure 18 demonstrates a
simple implementation of this FSK encoding.
External crystal
CMOS clock input
Internal RC oscillator (AD5700-1 only)
DATA
The device is controlled via a standard UART interface. The
relevant signals are RTS, CD, TXD, and RXD (see Table 6 for
more detail on individual pin descriptions).
1
0
1.2kHz
WORD
2.2kHz
WORD
DDS
DAC
CLOCK
Figure 18. DDS-Based FSK Encoder
Rev. D | Page 13 of 24
FSK
10435-017
A single-chip solution, the AD5700/AD5700-1 not only integrate the modulation and demodulation functions, but also
contain an internal reference, an integrated receive band-pass
filter (which has the flexibility of being bypassed if required),
and an internally buffered HART output, giving a high output
drive capability and removing the need for external buffering.
The AD5700-1 option also contains a precision internal RC
oscillator. The block diagram in Figure 1 shows a graphical
illustration of how these circuit blocks are connected together.
As a result of such extensive integration options, minimal
external components are required. The AD5700/AD5700-1
are suitable for use in both HART field instrument and master
configurations.
FSK MODULATOR
MUX
Highway Addressable Remote Transducer (HART) Communication is the global standard for sending and receiving digital
information across analog wires between smart field devices
and control systems. This is a digital two-way communication
system, in which a 1 mA p-p frequency shift keyed (FSK) signal
is modulated on top of a 4 mA to 20 mA analog current signal.
The AD5700/AD5700-1 are designed and specified to operate
as a single-chip, low power, HART FSK half-duplex modem,
complying with the HART physical layer requirements
(Revision 8.1).
AD5700/AD5700-1
Data Sheet
CONNECTING TO HART_OUT
FSK DEMODULATOR
The HART_OUT pin is dc biased to 0.75 V and should be
capacitively coupled to the load. The current consumption
specifications in Table 2 are based on driving a 5 nF load. If
the application requires a larger load value, more current is
required. This value can be calculated from the following
formula:
HART_IN
8-BIT DATA + PARITY
500 mV

1
4 2 × 
2
f
× C LOAD
×
π

(1)
2

 + RLOAD 2


where:
IAD5700 is the current drawn by the AD5700/AD5700-1 in
transmit mode as per specifications (see Table 2). Note that the
specifications in Table 2 assume a 5 nF CLOAD.
f is the output frequency (1.2 kHz or 2.2 kHz).
CLOAD is the capacitive load to ground on HART_OUT.
RLOAD is the resistive load on the loop.
When driving a purely capacitive load, the load should be in the
range of 5 nF to 52 nF. See Figure 11 for a typical plot of supply
current vs. capacitive load.
Example
Assume use of an internal reference, and CLOAD = 52 nF.
ICC + IOICC = 140 µA maximum (from Table 2
specification)
Note that this is incorporating a 5 nF load.
Therefore, to calculate the load current required to drive the
extra 47 nF, use Equation 1.
Substituting f = 1200 Hz, CLOAD = 47 nF, and RLOAD = 0 Ω into
the formula results in ILOAD of 62.6 µA.
If using the crystal oscillator, this adds 60 µA maximum (see
Table 2 for conditions).
Thus, the total worst-case current in this example is:
Figure 20. AD5700/AD5700-1 Demodulator Waveform
(Preamble Message 0xFF)
When RTS is logic high, the modulator is disabled and the
demodulator is enabled, that is, the AD5700/AD5700-1 are in
receive mode. A high on CD indicates a valid carrier is detected.
The demodulator accepts an FSK signal at the HART_IN pin
and restores the original modulated signal at the UART
interface digital data output pin, RXD. The combination of the
ADC, digital filtering and digital demodulation results in a
highly accurate output on the RXD pin. The HART bit stream
follows a standard UART frame with a start bit, 8-bit data, one
parity, and a stop bit (see Figure 20).
CONNECTING TO HART_IN OR ADC_IP
The AD5700/AD5700-1 have two filter configuration options:
an external filter (HART signal is applied to ACP_IP) and an
internal filter (HART signal is applied to HART_IN).
The external filter configuration is shown in Figure 21. In this
case, the HART signal is applied to the ADC_IP pin through an
external filter circuit. In safety critical applications, the AD5700/
AD5700-1 must be isolated from the high voltage of the loop
supply. The recommended external band-pass filter includes a
150 kΩ resistor, which limits current to a sufficiently low level
to adhere to intrinsic safety requirements. In this case, the input
has higher transient voltage protection and should, therefore,
not require additional protection circuitry, even in the most
demanding of industrial environments. Assuming the use of a
1% accurate resistor and 10% accurate capacitor components,
the calculated variation in CD trip voltage levels vs. the ideal is
±3.5 mV.
140 µA + 62.6 µA + 60 µA = 262.6 µA
HART_OUT
If driving a load with a resistive element, it is recommended to
place a 22 nF capacitor to ground at the HART_OUT pin. The
load should be coupled with a 2.2 µF series capacitor. For low
impedance devices, the RLOAD range is typically 230 Ω to 600 Ω.
22nF
HART
NETWORK
REF
1µF
1.2MΩ
ADC_IP
1.2MΩ
300pF
150kΩ
150pF
2.2µF
Figure 21. AD5700/AD5700-1 with External Filter on ADC_IP
RLOAD
10435-018
HART_OUT
AD5700/
AD5700-1
Figure 19. AD5700/AD5700-1 with Resistive Load at HART_OUT
Rev. D | Page 14 of 24
10435-020
I LOAD RMS =
STOP
START
I TOTAL = I AD5700 + I LOAD RMS
10435-019
RXD
Data Sheet
AD5700/AD5700-1
The internal filter configuration is shown in Figure 22. This
option is beneficial where cost or board space is a large concern
because it removes the need for multiple external components.
This configuration achieves an 8 kV ESD HBM rating but
requires extra external protection circuitry for EMC and surge
protection purposes if used in harsh industrial environments.
CMOS Clock Input
A CMOS clock input can also be used to generate a clock for the
AD5700/AD5700-1. To use this mode, connect an external clock
source to the XTAL 1 pin, and leave XTAL2 open circuit (see
Figure 24).
HART_OUT
10435-021
680pF
AD5700/AD5700-1
10435-027
ADC_IP
XTAL2
HART
NETWORK
2.2nF
HART_IN
XTAL1
AD5700/
AD5700-1
Figure 22. AD5700/AD5700-1 Using Internal Filter on HART_IN
CLOCK CONFIGURATION
Figure 24. CMOS Clock Connection
The CLK_CFG0, CLK_CFG1, and XTAL_EN pins configure
the clock generation as shown in Table 7. The AD5700/AD5700-1
can also provide a clock output at CLKOUT (for more details,
see the CLKOUT section).
Consuming typically 218 µA, the low power, internal, 0.5 %
precision RC oscillator, available only on the AD5700-1, has an
oscillation frequency of 1.2288 MHz. To use this mode, tie the
XTAL1 pin to ground and leave the XTAL2 pin open circuit
(see Figure 25).
External Crystal
The typical connection for an external crystal (ABLS-3.6864MHZL4Q-T) is shown in Figure 23. To ensure minimum current
consumption and to minimize stray capacitances, connections
between the crystal, capacitors, and ground should be made as
close to the AD5700/AD5700-1 as possible. Consult individual
crystal vendors for recommended load information and crystal
performance specifications.
Figure 25. Internal Oscillator Connection
CLKOUT
The AD5700/AD5700-1 can provide a clock output at CLKOUT
(see Table 7).
•
ABLS-3-6864MHZ-L4Q-T
18pF
AD5700-1
18pF
XTAL2
•
10435-022
XTAL1
•
AD5700/AD5700-1
Figure 23. Crystal Oscillator Connection
The ABLS-3.6864MHZ-L4Q-T crystal oscillator data sheet
recommended two 18 pF capacitors. Because the crystal current
consumption is dominated by the load capacitance, in an effort
to reduce the crystal current consumption, two 8 pF capacitors
were used on the XTAL1 and XTAL2 pins. The AD5700/AD5700-1
still functioned as expected, even with the resulting reduction in
frequency performance from the crystal due to the smaller
capacitance values. Crystals are available that support 8 pF
capacitors. It is recommended to consult the relevant crystal
manufacturers for this information.
10435-028
External crystal
CMOS clock input
Internal RC oscillator (AD5700-1 only)
XTAL2
•
•
•
Internal Oscillator (AD5700-1 only)
XTAL1
The AD5700/AD5700-1 support numerous clocking configurations to allow the optimal trade-off between cost and power:
If using the crystal oscillator, this clock output can be
configured as a 3.6864 MHz, 1.8432 MHz, or 1.2288 MHz
buffer clock.
If using a CMOS clock, no clock output can be configured
at the CLKOUT pin.
If using the internal RC oscillator, this clock output is only
available as a 1.2288 MHz buffer clock.
The amplitude of the clock output depends on the IOVCC level;
therefore, the clock output can be in the range of 1.71 V p-p to
5.5 V p-p. Enabling the clock output of the AD5700/AD5700-1
increases the current consumption of the device. This increase
is due to the current required to drive any load at the CLKOUT
pin, which should not be more than 30 pF.
This capacitance should be minimized to reduce current
consumption and provide the clock with the cleanest edges.
The additional current drawn from the IOVCC supply can be
calculated using the following equation:
Rev. D | Page 15 of 24
I=C×V×f
AD5700/AD5700-1
Data Sheet
Table 7. Clock Configuration Options
XTAL_EN
CLK_CFG1
CLK_CFG0
CLKOUT
Description
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No output
No output
No output
1.2288 MHz output
No output
3.6864 MHz output
1.8432 MHz output
1.2288 MHz output
3.6864 MHz CMOS clock connected at XTAL1 pin
1.2288 MHz CMOS clock connected at XTAL1 pin
Internal oscillator enabled (AD5700-1 only)
Internal oscillator enabled, CLKOUT enabled (AD5700-1 only)
Crystal oscillator enabled
Crystal oscillator enabled, CLKOUT enabled
Crystal oscillator enabled, CLKOUT enabled
Crystal oscillator enabled, CLKOUT enabled
SUPPLY CURRENT CALCULATIONS
POWER-DOWN MODE
The VCC and IOVCC current consumption specifications shown
in Table 2 are derived using the internal reference and an
external clock source. This specification is given for a
maximum temperature of 85oC (115 µA receive current and
140 µA transmit current) and an extended maximum
temperature of 125oC (179 µA receive current and 193 µA
transmit current). Alternatively, if the external reference is
preferred, (assuming a maximum temperature of 85oC), the
receive and transmit supply current values become 118 µA and
129 µA respectively, including the current required by the
external reference. A similar calculation can be done for the
125oC maximum temperature case.
The AD5700/AD5700-1 can be placed into power-down mode
by holding the RESET pin low. If using the internal reference, it
is recommended to tie the REF_EN pin to the RESET pin so
that it is also powered down. If the reference is not powered
down while RESET is low, the output voltage on the REF pin is
approximately 1.7 V until RESET is brought high again.
If the crystal oscillator or internal oscillator is used, VCC and
IOVCC current consumption figures return to the 115 µA receive
current and 140 µA transmit current. However, the resultant
current consumption from the crystal oscillator or internal
oscillator must now be accounted for, 60 µA maximum additional current for the crystal oscillator, or 285 µA maximum
additional current for the internal oscillator option. This gives
a maximum current consumption of 175 µA in receive mode
and 200 µA in transmit mode, when using the internal reference
and the crystal oscillator. Utilizing the internal reference
and the internal oscillator (AD5700-1 only) results in a total
maximum current consumption of 400 µA for receive current
and 425 µA for transmit current.
In this mode, the receive, transmit, and oscillator circuits are all
switched off, and the device consumes a typical current of 16 µA.
FULL DUPLEX OPERATION
Full duplex operation means that the modulator and demodulator of the AD5700/AD5700-1 are enabled at the same time. This
is a powerful feature, enabling a self-test procedure of not only
the HART device but also the complete signal path between the
HART device and the host controller. This provides verification
that the local communications loop is functional. This increased
level of system diagnostics is useful in production self-test and
is advantageous in improving the application’s safety integrity
level (SIL) rating. The full duplex mode of operation is enabled by
connecting the DUPLEX pin to logic high.
Rev. D | Page 16 of 24
Data Sheet
AD5700/AD5700-1
APPLICATIONS INFORMATION
shows an example of a HART-enabled current input module
that contains transient voltage protection circuitry, which is
very important in harsh industrial control environments.
SUPPLY DECOUPLING
It is recommended to decouple the VCC and IOVCC supplies with
10 μF in parallel with 0.1 μF capacitors to ground. For many
applications, 1 μF in parallel with 0.1 μF ceramic capacitors to
ground should be sufficient. The REG_CAP voltage of 1.8 V is
used to supply the AD5700/AD5700-1 internal circuitry and is
derived from the VCC supply using a high efficiency clocking
LDO. Decouple this REG_CAP supply with a 1 μF ceramic
capacitor to ground. It is also required to decouple the REF pin
with a 1 μF ceramic capacitor to ground. Place decoupling
capacitors as close to the relevant pins as possible.
The module is powered from a 24 V field supply, and the 250 Ω
load is within the low impedance module itself. This configuration
is in contrast to Figure 27, which demonstrates a secondary HART
device, in which the load is outside of the module. For transient
voltage protection, a 10 V unidirectional (for protection against
positive high voltage transients) transient voltage suppressor (TVS)
is placed at the connection point of the current input module.
The TVS component that is used in a given application circuit
must have power ratings that are appropriate to the individual
system. When choosing the TVS, low leakage current is also an
important specification for maintaining the accuracy of the analog
current input. In the event of a transient spike, the 22 Ω series
resistor acts as a current limiting resistor for the FSK output pin.
The FSK input pin is inherently protected by the 150 kΩ resistor,
which forms part of the recommended external filter circuitry
at the FSK input. The voltage divider, made up of both a 75 kΩ
resistor and a 22 kΩ resistor, is used to maintain a 0.75 V dc bias
at the field side of the FSK output switch.
For loop-powered applications, it is recommended to connect a
resistance in series with the VCC supply to minimize the effect of
any noise, which may, depending on the system configuration, be
introduced onto the loop as a result of current draw variations
from the AD5700/AD5700-1. For typical applications, 470 Ω of
resistance has proven most effective. However, depending on the
application conditions, alternative values may also be acceptable
(see R1 in Figure 29).
TRANSIENT VOLTAGE PROTECTION
Many industrial control applications have requirements for
HART-enabled current input and output modules. Figure 26
3.3V
3.3V
75kΩ
2.2µF
6.8nF
VLOOP
24V
AD5700/
AD5700-1
300pF
150kΩ
TXD
10nF
22kΩ
1.2MΩ
MICROCONTROLLER
ADC_IP
150pF
AGND
1.2MΩ
20kΩ
RTS
CD
REF
1µF
RXD
ADC
10µF
10435-031
250Ω
Figure 26. Current Input Module, HART Circuit
3.3V
3.3V
2.2µF
50V
39V
1500W
6.8nF
50V
4.7Ω
0.5W
75kΩ
10V
400W
VCC
20Ω
22kΩ
HART_OUT
10nF
AD5700/
AD5700-1
150kΩ
150pF
300pF
RTS
HOST
CD
REF
1.2MΩ
TXD
RXD
1µF
ADC_IP
1.2MΩ
AGND
Figure 27. Secondary HART Device
Rev. D | Page 17 of 24
10435-030
FIELD
INSTRUMENT
10V
400W
VCC
HART_OUT
22Ω
AD5700/AD5700-1
Data Sheet
As previously mentioned, Figure 27 shows an example secondary
HART device, incorporating two-stage protection circuitry. In
this example, a bidirectional (for protection against both positive
and negative high voltage transients) TVS is included to provide
flexibility in the polarity of the connection points of the module.
Because this module could be connected to any point on the
current loop, the higher TVS rating was chosen. The lower
rated second stage provides added protection for the AD5700/
AD5700-1 device.
combination of Analog Devices industrial converters and the
AD5700/AD5700-1 greatly simplifies system design, enhancing
reliability while reducing overall PCB size.
Figure 29 shows how the AD5700/AD5700-1 HART modem
can be interfaced with the AD5421 (4 mA to 20 mA loop-powered
DAC) and the ADuCM360 microcontroller to construct a loop
powered transmitter circuit. The HART signal from
HART_OUT is introduced to the AD5421 via the CIN pin.
The HART enabled smart transmitter reference demo circuit
(the block diagram shown in Figure 30) was developed by
Analog Devices and uses the AD5421, a 16-bit, loop-powered,
4 mA to 20 mA DAC, the ADuCM360 microcontroller and the
AD5700 modem. This circuit has been compliance tested,
verified, and registered as an approved HART solution by the
HART Communication Foundation. Contact your sales
representative for further information about this demo circuit.
TYPICAL CONNECTION DIAGRAMS
Figure 28 shows a typical connection diagram for the AD5700/
AD5700-1 using the external and internal options. See the
Connecting to HART_IN or ADC_IP section for more details.
The AD5700/AD5700-1 are designed to interface easily with
Analog Devices, Inc., innovative portfolio of industrial
converters like the AD5421 loop-powered current-output DAC,
the AD5410/AD5420 and AD5412/AD5422 family of linepowered current-output DACs, and the AD5755-1, a quad DAC
with innovative dynamic power control technology. The
1.71V TO 5.5V
1.71V TO 5.5V
1.71V TO 5.5V
CONFIGURATION
PINS
+
2.2nF
HART_IN
DGND AGND
CONFIGURATION
PINS
Figure 28. AD5700/AD5700-1 Typical Connection Diagram for External and Internal Filter Options
Rev. D | Page 18 of 24
HART NETWORK
REG_CAP
CLKOUT
XTAL1
XTAL_EN
DGND AGND
1µF
ADC_IP
CLK_CFG1
150pF
VCC
HART_OUT
680pF
RTS
CLK_CFG0
150kΩ
IOVCC
AD5700/AD5700-1
TXD
DUPLEX
1.2MΩ
HART_IN
300pF
0.1µF
REF
FILTER_SEL
XTAL_EN
CLK_CFG1
CLK_CFG0
ADC_IP
DUPLEX
REF_EN
RTS
FILTER_SEL
1.2MΩ
0.1µF
RXD
REF_EN
1µF
AD5700/AD5700-1
CD
RESET
VCC
HART_OUT
ADuC7060 MICROCONTROLLER
IOVCC
REF
TXD
10µF
0.1µF
+
XTAL2
1µF
HART NETWORK
XTAL2
0.1µF
CLKOUT
XTAL1
REG_CAP
10µF
+
RXD
RESET
ADuC7060 MICROCONTROLLER
1µF
CD
10µF
+
10µF
10435-023
1.71V TO 5.5V
In conclusion, the AD5700/AD5700-1 enable quick and easy
deployment of a robust HART-compliant system.
Data Sheet
AD5700/AD5700-1
OPTIONAL
EMC FILTER
OPTIONAL
MOSFET
DN2540
BSP129
10µF
4.7µF
T1
0.1µF
200kΩ
IODVDD DVDD REGOUT
REGIN
VLOOP
RANGE0
RANGE1
DRIVE
ALARM_CURRENT_DIRECTION
RINT/REXT
VLOOP
SYNC
SCLK
SDIN
SDO
FAULT
LDAC
VZ = 4.7V
0.1µF
REXT2
REG_SEL2
REFOUT1 REFIN
0.1µF
REG_SEL1
R1
REFOUT2
1µF
LOOP–
REXT1
COM
OPTIONAL
RESISTOR
CIN COM
SETS REGULATOR
VOLTAGE
47nF
168nF
VCC
AD5700/AD5700-1
TXD
RXD
RTS
CD
HART_OUT
REF
1µF
1.2MΩ
300pF
ADC_IP
AGND DGND
1.2MΩ
150kΩ
150pF
10435-025
R1
470Ω
RL
1MΩ
AD5421
REG_SEL0
ADuCM360
19MΩ
Figure 29. Loop-Powered Transmitter Diagram
Rev. D | Page 19 of 24
AD5700/AD5700-1
3.3V
Data Sheet
ADuCM360
AD5421
VDD
PRESSURE
SENSOR
SIMULATION
ADC 0
TEMPERATURE
SENSOR
PT100
REGIN
+
V-REGULATOR
MICROCONTROLLER
VLOOP
SRAM
FLASH
CLOCK
RESET
WATCHDOG
LEXC
3.3V
ADC
TEMPERATURE
SENSOR
SPI
COM
ADC 1
4.7nF
DAC
COM
WATCHDOG
TIMER
TEST CONNECTOR
50Ω
UART
T1: CD
T2: RTS
T3: COM
CIN
LOOP–
–
T4: TEST
VCC
AD5700
HART_OUT
3.3V
C_HART
C_SLEW
REF
HART MODEM
ADC_IP
HART
INPUT
FILTER
10435-029
AGND DGND
Figure 30. Block Diagram—Analog Devices HART-Enabled Smart Transmitter Reference Demo Circuit
Rev. D | Page 20 of 24
Data Sheet
AD5700/AD5700-1
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.30
0.25
0.20
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
13
12
2.20
2.10 SQ
2.00
6
7
0.25 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
06-11-2012-A
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
Figure 31. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5700BCPZ-R5
AD5700BCPZ-RL7
AD5700ACPZ-RL7
AD5700-1BCPZ-R5
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
AD5700-1BCPZ-RL7
−40°C to +125°C
AD5700-1ACPZ-RL7
−40°C to +125°C
Oscillator Options
External clock, crystal
External clock, crystal
External clock, crystal
External clock, crystal
or internal oscillator
External clock, crystal
or internal oscillator
External clock, crystal
or internal oscillator
Receive Supply
Current
157 µA
157 µA
260 µA
442 µA
Package Description
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
Package
Option
CP-24-10
CP-24-10
CP-24-10
CP-24-10
442 µA
24-Lead LFCSP_WQ
CP-24-10
540 µA
24-Lead LFCSP_WQ
CP-24-10
EVAL-AD5700-1EBZ
1
Evaluation Board for
AD5700 and AD5700-1
Z = RoHS Compliant Part.
Rev. D | Page 21 of 24
AD5700/AD5700-1
Data Sheet
NOTES
Rev. D | Page 22 of 24
Data Sheet
AD5700/AD5700-1
NOTES
Rev. D | Page 23 of 24
AD5700/AD5700-1
Data Sheet
NOTES
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10435-0-5/13(D)
Rev. D | Page 24 of 24
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