TMP86FM29 Difference Comparison table of TMP86C829B/H29B/M29B/PM29A/PM29B/C929AXB and TMP86FM29 TMP86C829B TMP86CH29B TMP86CM29B TMP86PM29A TMP86PM29B TMP86C929AXB (Emulation chip) (Note 3) TMP86FM29F ROM 8 K (Mask ROM) 16 K (Mask ROM) 32 K (Mask ROM) 32 K (OTP) − 32 K (Flash) RAM 512 1.5 K 1.5 K 1.5 K − 2K 42 pin (MCU part) 42 pin I/O 42 pin External Interrupt 5 pin 5 pin AD Converter 10-bit AD converter × 8 ch 10-bit AD converter × 8 ch Timer Counter 18-bit timer × 1 ch 8-bit timer × 4 ch 18-bit timer × 1 ch 8-bit timer × 4 ch Serial Interface 8-bit UART / SIO × 1 ch 8-bit UART / SIO × 1 ch LCD 32 seg × 4 com 32 seg × 4 com (Note 2) Key-on Wakeup 4 ch 4 ch in MCU Mode 1.8 to 5.5 V at 4.2 MHz 2.7 to 5.5 V at 8 MHz 4.5 to 5.5 V at 16 MHz 1.8 to 5.25 V at 4.2 MHz 2.7 to 5.25 V at 8 MHz 4.5 to 5.25 V at 16 MHz 1.8 to 3.6 V at 4.2 MHz (External clock) 1.8 to 3.6 V at 8 MHz (Resonator) 2.7 to 3.6 V at 16 MHz Operating Temperature −40 to 85℃ 0 to 60°C −40 to 85°C Operating Voltage in MCU Mode Writing to Flash Memory − 2.7 to 3.6V at 16 MHz 25°C ± 5°C CPU Wait (Note 1) N/A Available Note 1: The CPU wait is a CPU halt function for stabilizing of power supply of Flash memory. The CPU wait period is as follows. In the CPU wait period except RESET, CPU is halted but peripheral functions are not halted. Therefore, if the interrupt occurs during the CPU wait period, the interrupt latch is set. In this case, if the IMF has been set to “1”, the interrupt service routine is executed after CPU wait period. For details refer to 2.14 “Flash Memory” in TMP86FM29 data sheet. Thus, even if the same software is executed in 86FM29 and 86C829B/H29B/M29B/PM29A/PM29B /C929AXB, the operation process is not the same. Therefore, when the final operating confirmation on target application is executed for software development of Mask ROM Product (86C829B/H29B/M29B), not the Flash product (86FM29) but the OTP product (86PM29A/PM29B) should be used. Condition After reset release Wait Time 10 2 /fc[s] Changing from STOP mode to NORMAL mode (at EEPCR<MNPWDW> = “1”) 2 /fc[s] Changing from STOP mode to SLOW mode (at EEPCR<MNPWDW> = “1”) 2 /fs[s] Changing from IDLE0/1/2 mode to NORMAL mode (at EEPCR<ATPWDW> = “0”) 2 /fc[s] Changing from SLEEP0/1/2 mode to SLOW mode (at EEPCR<ATPWDW> = “0”) 2 /fs[s] 10 3 10 3 Halt/Operate CPU Peripherals Halt Halt Halt Operate Halt Operate Halt Operate Halt Operate 2004-03-01 TMP86FM29 Note 2: The 86FM29 can not drive the 5V LCD panel because the electrical characteristics in 86FM29 is altered from 86C829B/H29B/M29B/PM29A/PM29B/C929AXB. The recommended operating condition of V3 pin in TMP86FM29 is 3.6V(max). For details, refer to “Electrical Characteristics”. When the LCD booster circuit is used in 86FM29, connect the reference voltage and capacitor as shown in "case2". Though the method of "case1" has been recommended in 86C829B /H29B/M29B/PM29A/PM29B datasheets, the 86FM29 should not use method of "case1". Even if the method of "case1" is used in the 86C829B/H29B/M29B/PM29A/PM29B/C929AXB, the function and operation are not issue at all. However, if the "case2" is used, the booster ability becomes higher than "case1". Therefore, when the application board is designed newly in future, the method of "case2" is also recommended in 86C829B/H29B/M29B/PM29A/PM29B/C929AXB. VDD VDD V3 V3 V2 V2 C0 V1 C VSS C C C1 C1 V1 C0 Reference voltage (1 V) Case 1 (For 86C829B/H29B/M29B/PM29A/PM29B/C929AXB) C C Reference voltage (1 V) C VSS Case 2 (For 86FM29 and 86C829B/H29B/M29B/ PM29A/PM29B/C929AXB) Note 3: Flash function, CPU wait period and serial PROM mode cannot be emulated in the 86C929AXB. If the software including the flash function is executed in 86C929AXB, the operation process differs from 86FM29. 2004-03-01 TMP86FM29 CMOS 8-Bit Microcontroller TMP86FM29UG/FG The TMP86FM29 is the high-speed, high-performance and low power consumption 8-bit microcomputer, including FLASH, RAM, LCD driver, multi-function timer/counter, serial interface (UART/SIO), a 10-bit AD converter and two clock generators on chip. Product No. TMP86FM29UG TMP86FM29FG FLASH RAM 32768 × 8 bits 1536 × 8 bits Package P-LQFP64-1010-0.50E P-QFP64-1414-0.80C Emulation Chip TMP86C929AXB Feautures ♦ 8-bit single chip microcomputer TLCS-870/C series ♦ Instruction execution time: 0.25 µs (at 16 MHz) 122 µs (at 32.768 kHz) ♦ 132 types and 731 basic instructions ♦ 19 interrupt sources (External: 5, Internal: 14) ♦ Input/Output ports (39 pins) (Out of which 24 pins are also used as SEG pins) ♦ 18-bit timer counter: 1 ch • ♦ P-LQFP64-1010-0.50E TMP86FM29UG P-QFP64-1414-0.80C Timer, Event counter, Pulse width measurement, Frequencymeasurement modes 8-bit timer counter: 4 ch • Timer, Event counter, PWM output, Programmable divider output, PPG output modes ♦ Time Base Timer ♦ Divider output function TMP86FM29FG 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 86FM29-1 2004-03-01 TMP86FM29 ♦ Watchdog Timer • Interrupt source/reset output (programmable) ♦ Serial interface • 8-bit UART/SIO: 1ch ♦ 10-bit successive approximation type AD converter • Analog input: 8 ch ♦ Four Key-On Wake-Up pins ♦ LCD driver/controller • • • • ♦ Dual clock operation • ♦ Single/Dual-clock mode Nine power saving operating modes • • • • • • • • ♦ Built-in voltage booster for LCD driver With displaymemory LCD direct drive capability (max 32 seg × 4 com) 1/4, 1/3, 1/2duties or static drive are programmably selectable STOP mode : Oscillation stops. Battery/Capacitor back-up. Port output hold/High-impedance. SLOW 1, 2 mode : Low power consumption operation using low-frequency clock (32.768 kHz) IDLE 0 mode : CPU stops, and peripherals operate using high-frequency clock of Time-Base-Timer. Release by falling edge of TBTCR <TBTCK> setting. IDLE 1 mode : CPU stops, and peripherals operate using high-frequency clock. Release by interruputs. IDLE 2 mode : CPU stops, and peripherals operate using high and low frequency clock. Release by interruputs. SLEEP 0 mode : CPU stops, and peripherals operate using low-frequency clock of Time-Base-Timer. Release by falling edge of TBTCR <TBTCK> setting. SLEEP 1 mode : CPU stops, and peripherals operate using low-frequency clock. Release by interrupts. SLEEP 2 mode : CPU stops, and peripherals operate using high and low frequency clock. Release by interrupts. Wide operating voltage: 1.8 to 3.6 V at 8 MHz/32.768 kHz 2.7 to 3.6 V at 16 MHz/32.768 kHz 86FM29-2 2004-03-01 TMP86FM29 Pin Assignments (Top View) P54 (SEG19) P53 (SEG20) P52 (SEG21) P51 (SEG22) P50 (SEG23) P17 (SEG24/ SCK ) P16 (SEG25/TXD/SO) P15 (SEG26/RXD/SI/BOOT) P14 (SEG27/INT3) P13 (SEG28/INT2) P12 (SEG29/INT1) P11 (SEG30) P10 (SEG31) AVDD VAREF P67 (AIN7/STOP5) P20 P60 P61 P62 P63 P64 P65 P66 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ( STOP / INT5 ) (AIN0) (AIN1/ECIN) (AIN2/ECNT) (AIN3/INT0) (AIN4/STOP2) (AIN5/STOP3) (AIN6/STOP4) RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 V2 V1 C1 C0 ( DVO ) P30 ( PWM3 / PDO3 /TC3) P31 ( PWM4 / PDO4 / PPG4 /TC4) P32 ( PWM6 / PDO6 / PPG6 /TC6) P33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG3 SEG4 SEG5 SEG6 SEG7 P77 (SEG8) P76 (SEG9) P75 (SEG10) P74 (SEG11) P73 (SEG12) P72 (SEG13) P71 (SEG14) P70 (SEG15) P57 (SEG16) P56 (SEG17) P55 (SEG18) P-LQFP64-1010-0.50E P-QFP64-1414-0.80C 86FM29-3 2004-03-01 TMP86FM29 Block Diagram I/O Port (Segment Output) Common outputs COM3 to COM0 Power Supply Segment outputs SEG7 to SEG0 VDD VSS P7 LCD driver circuit LCD Power Supply Reset I/O Test Pin P77 (SEG8) P57 (SEG16) P17 (SEG24) to to to P70 (SEG15) P50 (SEG23) P10 (SEG31) C0 C1 V1 V2 V3 RESET TEST P5 P1 Address/Data Bus LCD Voltage booster circuit TLCS-870/C CPU Data Memory (RAM) Program Memory RAM System Control Circuit Standby Control Circuit (Key-On Wake-Up) Interrupt Controller Timing Generator Resonator Connecting Pins Time Base Timer XIN XOUT High frequency Clock Generator Low frequency Watchdog Timer 18-bit Timer/Counter 8-bit Timer/Counter TC1 TC3 TC4 TC5 TC6 UART/SIO SIO UART Address/Data Bus P2 P22 to P20 I/O Ports 10-bit AD Converter AVDD VAREF P6 P3 P67 (AIN7) to P60 (AIN0) P33 to P30 Analog reference Pins 86FM29-4 I/O Ports 2004-03-01 TMP86FM29 Pin Functions Pin Name Input/Output P17 (SEG24, SCK ) P16 (SEG25, TxD, SO) I/O (I/O) I/O (Output) P15 (SEG26, RxD, SI BOOT) I/O (I/O) P14 (SEG27, INT3) I/O (I/O) P13 (SEG28, INT2) I/O (I/O) P12 (SEG29, INT1) I/O (I/O) P11 (SEG30) I/O (Output) P10 (SEG31) I/O (Output) P22 (XTOUT) I/O (Output) P21 (XTIN) I/O (Input) P20 ( INT5 , STOP ) I/O (Input) P33 ( PWM6 , PDO6 PPG6 , TC6) I/O (I/O) P32 ( PWM4 , PDO4 PPG4 , TC4) I/O (I/O) P31 ( PWM3 , PDO3 , TC3) I/O (I/O) P30 ( DVO ) I/O (Output) P57 (SEG16) to P50 (SEG23) I/O (Output) P67 (AIN7, STOP5) I/O (Input) P66 (AIN6, STOP4) I/O (Input) P65 (AIN5, STOP3) I/O (Input) P64 (AIN4, STOP2) I/O (Input) P63 (AIN3, INT0 ) I/O (Input) P62 (AIN2, ECNT) I/O (Input) P61 (AIN1, ECIN) I/O (Input) P60 (AIN0) I/O (Input) P77 (SEG8) to P70 (SEG15) SEG7 to SEG0 COM3 to COM0 V3 to V1 Functions I/O (Output) Output Serial clock input/output 8-bit input/output port with latch. When used as input port, an external interrupt input, serial interface input/output and UART data input/output, the P1LCR must be set to “0” after setting output latch to “1”. When used as a LCD segment output, the P1LCR must be set to “1”. 3-bit input/output port with latch. When used as an input port, the output latch must be set to “1”. 4-bit programmable input/output port (Nch high current output). When used as a timer/counter output or divider output, the output latch must be set to “1”. When used as an input port or timer/counter input, the P3OUTCR must be set to “0” after P3DR is set to “1”. 8-bit input/output port with latch. When used as a LCD segment output, the P5LCR must be set to “1”. 8-bit programmable input/output port (tri-state). Each bit of this port can be individually configured as an input or an output under software control. When used as an analog input, the P6CR must be set to “0” after setting output latch to “0”. When used as an input port, a key on wake up input, an external interrupt input and timer/ counter input, the P6CR must be set to “0” after setting output latch to “1”. 8-bit input/output port with latch. When used as a LCD segment output, the P7LCR must be set to “1”. UART data output Serial data output UART data input Serial data input Serial PROM mode control LCD segment input outputs. External interrupt 3 input External interrupt 2 input External interrupt 1 input Resonator connecting pins (32.768 kHz) For inputting external clock, XTIN is used and XOUT is opened. External interrupt input 5 or STOP mode release signal input Timer counter 6 input/output Timer counter 4 input/output Timer counter 3 input/output Divider output LCD segment outputs STOP 5 input STOP 4 input STOP 3 input STOP 2 input External interrupt 0 input AD converter analog inputs Timer/Counter 1 input LCD segment outputs LCD segment outputs LCD common outputs C1 to C0 LCD voltage booster pin LCD voltage booster pin. Capacitors are required between C0 and C1 pin and V1/V2/V3 pin and GND. XIN, XOUT Input Output Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is opened. RESET TEST I/O Reset signal input or watchdog timer output/address-trap-reset output/system clock reset output Input Test pin for out-going test, and the serial PROM mode control pin. Usually be fixed to low level. When the serial PROM mode starts, be fixed to "1". +5 V, 0 (GND) VDD, VSS VAREF AVDD Power Supply Analog reference voltage inputs (High) AD circuit power supply 86FM29-5 2004-03-01 TMP86FM29 Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 Memory Address Map The TMP86FM29 memory consists of 5 blocks: FLASH memory, BOOT ROM, RAM, DBR (Data buffer register) and SFR (Special function register). They are all mapped in 64-Kbyte address space. Figure 1.1.1 shows the TMP86FM29 memory address map. The general-purpose registers are not assigned to the RAM address space. SFR 0000H 003FH 0040H 64 bytes 1536 bytes RAM 063FH DBR 0F80H 128 bytes 0FFFH BOOT ROM 3800H 2048 bytes 3FFFH 8000H 32688 bytes FLASH memory: FLASH memory includes: FLASH memory Vector table BOOT ROM: FLASH writing program RAM: Random Access Memory includes: Data memory Stack SFR: Special Function Register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word DBR: Data Buffer Register includes: Peripheral control registers Peripheral Status registers FLASH memory FFB0H FFBFH FFC0H FFDFH FFE0H 16 bytes Vector table for interrupts (8 vectors) 32 bytes Vector table for vector call instructions (16 vectors) 32 bytes Vector table for interrupts/reset (16 vectors) FFFFH Figure 1.1.1 Memory Address Maps 1.2 Program Memory (FLASH) The TMP86FM29 has a 32 K × 8 bits (Address 8000H to FFFFH) of Flash memory. 86FM29-6 2004-03-01 TMP86FM29 Electrical Characteristics Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage Output current (Per 1 pin) Output current (Total) (VSS = 0 V) Symbol Pins −0.3 to 4.0 V3 pin −0.3 to VDD + 0.3 VIN V −0.3 to VDD + 0.3 VOUT1 IOUT1 P3, P6 ports −1.8 IOUT2 P1, P2, P5, P6, P7 ports 3.2 IOUT3 P3 ports 30 ΣIOUT2 P1, P2, P5, P6, P7 ports 60 ΣIOUT3 P3 ports mA 80 Power dissipation [Topr = 85°C] PD 350 Soldering temperature (Time) Tsld 260 (10 s) Storage temperature Tstg −55 to 125 Operating temperature Topr −40 to 85 Note: Unit −0.3 to 4.0 VDD VLCD Rating mW °C The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 86FM29-174 2004-03-01 TMP86FM29 (VSS = 0 V, Topr = −40 to 85°C) Recommended Operating Condition-1 (MCU mode) Parameter Symbol Pins Condition NORMAL1, 2 mode fc = 16 MHz IDLE0, 1, 2 mode fc = 8 MHz (In case of connecting the resonator) Supply voltage fc = 4.2 MHz VDD (In case of external clock input) fs = 32.768 kHz Min Max Unit 2.7 NORMAL1, 2 mode IDLE0, 1, 2 mode NORMAL1, 2 mode 1.8 3.6 IDLE0, 1, 2 mode SLOW1, 2 mode SLEEP0, 1, 2 mode V 1.8 STOP mode Input high level VIH1 Except Hysteresis input VIH2 Hysteresis input Input low level VIL2 Except Hysteresis input Hysteresis input fc XIN, XOUT fs XTIN, XTOUT (In case of connecting the resonator) Clock frequency fc XIN, XOUT fs XTIN, XTOUT (In case of external clock input) LCD reference voltage Capacity for LCD booster circuit Note: VDD × 0.30 VDD ≥ 2.7 V 0 VDD = 2.7 to 3.6 V VDD = 1.8 to 3.6 V 30.0 VDD = 1.8 to 3.6 V 1.0 VDD = 2.7 to 3.6 V VDD = 1.8 to 3.6 V LCD booster circuit is enable (V3 ≥ VDD) 8.0 16.0 34.0 4.2 16.0 MHz kHz MHz 30.0 34.0 kHz 0.8 1.2 V 0.1 0.47 µF The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (Supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Recommended Operating Condition-2 (Serial PROM mode) Parameter Supply voltage Clock frequency Note: 1.0 (V3 ≥ VDD) CLCD VDD × 0.25 VDD × 0.10 VDD = 1.8 to 3.6 V Booster circuit is enable V1 VDD VDD × 0.90 VDD < 2.7 V VIL3 Clock frequency VDD × 0.75 VDD < 2.7 V VIH3 VIL1 VDD × 0.70 VDD ≥ 2.7 V Symbol Pins VDD fc XIN, XOUT (VSS = 0 V, Topr = 25°C ± 5°C) Condition Min Max Unit 2 MHz ≤ fc ≤16 MHz 2.7 3.6 V VDD = 2.7 to 3.6 V 2.0 16.0 MHz The operating temperature area of serial PROM mode is 25°C ± 5°C and the operating area of high frequency of serial PROM mode is different from MCU mode. 86FM29-175 2004-03-01 TMP86FM29 DC Characteristics Parameter Hysteresis voltage Input current (VSS = 0 V, Topr = −40 to 85°C) Symbol Pins Condition Min Typ. Max Unit V Hysteresis input VDD = 3.3 V − 0.4 − IIN1 TEST VDD = 3.6 V, VIN = 0 V − − −5 IIN2 Sink open drain, Tri-state VDD = 3.6 V, VIN = 3.6 V/0 V − − ±5 VHS IIN3 RESET VDD = 3.6 V, VIN = 3.6 V − − +5 RIN1 TEST pull down VDD = 3.6 V, VIN = 3.6 V − 70 − RIN2 RESET pull up VDD = 3.6 V, VIN = 0 V 100 220 450 High frequency feedback resistor RFB XOUT VDD = 3.6 V − 3 − Low frequency feedback resistor RFBT XTOUT VDD = 3.6 V − 20 − − − ±10 Input resistance VDD = 3.6 V ILO Output high voltage VOH CMOS, Tri-state VDD = 3.6 V, lOH = −0.6 mA 3.2 − − Output low voltage VOL Except XOUT, P3 port VDD = 3.6 V, IOL = 0.9 mA − − 0.4 Output low current IOL P3 port VDD = 3.6 V, VOL = 1.0 V − 6 − LCD output voltage (LCD booster is enable) V2 pin V3 ≥ VDD − V1 x 2 − V2-3OUT V3 pin Reference supply pin: V1 SEG/COM pin: No load − V1 x 3 − Sink open drain, Tri-state Fetch area Fetch area VOUT = 3.4V/0.2 V MNP = “1” Flash area VDD = 3.6 V RAM area VIN = 3.4 V/0.2 V MNP = “0” fc = 16 MHz MNP•ATP = “1” fs = 32.768 kHz MNP•ATP = “0” Supply current in IDLE 0, 1, 2 mode Supply current in SLOW 1 mode kΩ MΩ Output leakage current Supply current in NORMAL 1, 2 mode µA Flash area RAM area Supply current in SLEEP 1 mode VDD = 3.0 V VIN = 2.8 V/0.2 V fs = 32.768 kHz Supply current in SLEEP 0 mode VDD = 3.6 V Supply current in STOP mode VIN = 3.4 V/0.2 V − 5.3 7.3 − 3.4 5.2 − 3.1 5.2 − 2.2 4.2 MNP = “1” − 850 1200 MNP = “0” − 7 19 MNP•ATP = “1” − 850 1200 MNP•ATP = “0” − 5.5 17 MNP•ATP = “1” − 850 1200 MNP•ATP = “0” − 4.5 15 − 0.5 10 µA V mA V mA µA Note 1: Typical values show those at Topr = 25°C. Note 2: Input current (IIN1, IIN2): The current through pull-up or pull-down resistor is not included. Note 3: IDD does not include IREF current. Note 4: The supply currents of SLOW2 and SLEEP2 modes are equivalent to IDLE0, IDLE1, IDLE2. Note 5: MNP (MNPWDW) shows bit0 in EEPCR register and ATP (ATPWDW) shows bit1 in EEPCR register. Note 6: “Fetch” means reading operation of FLASH data as an instruction by CPU. 86FM29-176 2004-03-01 TMP86FM29 (VSS = 0.0 V, 2.7 V ≤ VDD ≤ 3.6 V, Topr = −40 to 85°C) AD Conversion Characteristics Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Symbol Condition VAREF Min Typ. Max AVDD − 1.0 − AVDD AVDD Unit VDD V ∆VAREF 2.5 − − Analog input voltage VAIN VSS − VAREF Power supply current of analog reference voltage IREF − 0.35 0.61 mA − − − − − − − − ±2 ±2 ±2 ±2 LSB Non linearity error Zero point error Full scale error Total error VDD = AVDD = VAREF = 3.6 V VSS = 0.0 V VDD = AVDD = 2.7 V VSS = 0.0 V VAREF = 2.7 V (VSS = 0.0 V, 2.0 V ≤ VDD < 2.7 V, Topr = −40 to 85°C) Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Symbol Condition VAREF Min Typ. Max AVDD − 0.6 − AVDD AVDD Unit VDD V 2.0 − − VSS − VAREF − 0.20 0.34 mA − − − − − − − − ±4 ±4 ±4 ±4 LSB ∆VAREF VAIN IREF Non linearity error Zero point error Full scale error Total error VDD = AVDD = VAREF = 2.0V VSS = 0.0 V VDD = AVDD = 2.0 V VSS = 0.0 V VAREF = 2.0 V (VSS = 0.0 V, 1.8 V ≤ VDD < 2.0 V, Topr = −10 to 85°C) (Note 5) Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Symbol Condition VAREF Min Typ. Max AVDD − 0.1 − AVDD AVDD Unit VDD V ∆VAREF 1.8 − − Analog input voltage VAIN VSS − VAREF Power supply current of analog reference voltage IREF − 0.18 0.31 mA − − − − − − − − ±4 ±4 ±4 ±4 LSB Non linearity error Zero point error Full scale error Total error VDD = AVDD = VAREF = 1.8 V VSS = 0.0 V VDD = AVDD = 1.8 V VSS = 0.0 V VAREF = 1.8 V Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. Note 2: Conversion time is different in recommended value by power supply voltage. About conversion time, please refer to “2.15.2 Register configration”. Note 3: Please use input voltage to AIN input Pin in limit of VAREF − VSS. When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. Note 4: Analog Reference Voltage Range: ∆VAREF = VAREF − VSS Note 5: When AD is used with VDD < 2.0 V, the guaranteed temperature range varies with the operating voltage. Note 6: When AD converter is not used, fix the AVDD pin and VAREFpin on the VDD level. 86FM29-177 2004-03-01 TMP86FM29 (VSS = 0 V, VDD = 2.7 to 3.6 V, Topr = −40 to 85°C) AC Characteristics Parameter Symbol Condition Min Typ. Max 0.25 − 4 117.6 − 133.3 For external clock operation (XIN input), fc = 16 MHz − 31.25 − ns For external clock operation (XTIN input), fs = 32.768 kHz − 15.26 − µs Min Typ. Max Unit 0.5 − 4 117.6 − 133.3 For external clock operation (XIN input), fc = 4.2 MHz − 119.04 − ns For external clock operation (XTIN input), fs = 32.768 kHz − 15.26 − µs NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode µs SLOW1, 2 mode SLEEP1, 2 mode High Level clock pulse width twcH Low level clock pulse width twcL High level clock pulse width twcH Low level clock pulse width twcL Unit (VSS = 0 V, VDD = 1.8 to 3.6 V, Topr = −40 to 85°C) Parameter Symbol Condition NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode µs SLOW1, 2 mode SLEEP1, 2 mode High level clock pulse width twcH Low level clock pulse width twcL High level clock pulse width twcH Low level clock pulse width twcL Timer Counter 1 input (ECIN) Characteristics (VSS = 0 V, Topr = -40 to 85°C) Parameter Symbol TC1 input (ECIN input) Flash Characteristics tTC1 Condition Frequency measurement Single edge count mode VDD = 2.7 to 3.6 V Both edge count Frequency measurement Single edge count mode VDD = 1.8 to 2.7 V Both edge count Min Typ. Max − − 16 − − 8 Min Typ. Max − − 10 Unit MHz (VSS = 0 V) Parameter Condition Number of guaranteed writes (page VDD = 2.7 to 3.6 V, 2 MHz ≤ fc ≤ 16 MHz writing) to Flash memory in serial PROM (Topr = 25°C ± 5°C) mode 5 Unit Times Recommended Oscillating Conditions Note 1: An electrical shield by metal shield plate on the surface of IC package is recommended in order to protect the device from the high electric field stress applied from CRT (Cathodic Ray Tube) for continuous reliable operation. Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following http://www.murata.co.jp/search/index.html 86FM29-178 2004-03-01