VISHAY SI4401DDY

SPICE Device Model Si4401DDY
Vishay Siliconix
P-Channel 40 V (D-S) MOSFET
DESCRIPTION
CHARACTERISTICS
The attached SPICE model describes the typical electrical
characteristics of the p-channel vertical DMOS. The
subcircuit model is extracted and optimized over the - 55 °C
to + 125 °C temperature ranges under the pulsed 0 V to 10 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage. A novel gate-to-drain
feedback capacitance network is used to model the gate
charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter
values are optimized to provide a best fit to the measured
electrical data and are not intended as an exact physical
interpretation of the device.
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the - 55 °C to + 125 °C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
SUBCIRCUIT MODEL SCHEMATIC
D
CGD
R1
3
M2
Gy
G
RG
+ –
ETCV
Gx
CGS
DBD
M1
S
Note
This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to
the appropriate datasheet of the same number for guaranteed specification limits.
Document Number: 66915
S10-1615-Rev. A, 19-Jul-10
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SPICE Device Model Si4401DDY
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
SIMULATED MEASURED
DATA
DATA
UNIT
Static
Gate-Source Threshold Voltage
Drain-Source On-State Resistancea
VGS(th)
RDS(on)
VDS = VGS, ID = - 250 μA
1.3
-
VGS = - 10 V, ID = - 10.2 A
0.012
0.012
VGS = - 4.5 V, ID = - 8.4 A
0.019
0.018
V
Ω
Forward Transconductancea
gfs
VDS = - 15 V, ID = - 10.2 A
9
10
S
Diode Forward Voltage
VSD
IS = - 8.2 A
- 0.79
- 0.80
V
2990
3007
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = - 20 V, VGS = 0 V, f = 1 MHz
336
335
289
291
VDS = - 20 V, VGS = - 10 V, ID = - 10.2 A
62
64
33
33
VDS = - 20 V, VGS = - 4.5 V, ID = - 10.2 A
9.8
9.8
15.7
15.7
pF
nC
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
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Document Number: 66915
S10-1615-Rev. A, 19-Jul-10
SPICE Device Model Si4401DDY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA TJ = 25 °C, unless otherwise noted
50
10
40
8
30
ID - Drain Current (A)
ID - Drain Current (A)
TJ = 125 °C
VGS = 10 V, 7 V, 6 V, 5 V, 4 V
20
6
TJ = 25 °C
4
2
10
VGS = 3 V
TJ = - 55 °C
0
0
0.0
0.5
1.0
1.5
2.0
0
1
0.030
4500
0.024
3600
VGS = 4.5 V
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
2
3
4
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
0.018
0.012
VGS = 10 V
0.006
Ciss
2700
1800
900
Coss
Crss
0.000
0
0
10
20
30
40
0
50
ID - Drain Current (A)
8
16
24
32
40
VDS - Drain-to-Source Voltage (V)
100
10
8
TJ = 150 °C
VDS = 20 V
IS - Source Current (A)
VGS - Gate-to-Source Voltage (V)
ID = 10.2 A
6
VDS = 32 V
4
10
TJ = 25 °C
1
2
0.1
0
0
14
28
42
Qg - Total Gate Charge (nC)
56
70
0
0.3
0.6
0.9
1.2
VSD - Source-to-Drain Voltage (V)
Note
Dots and squares represent measured data.
Document Number: 66915
S10-1615-Rev. A, 19-Jul-10
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Document Number: 91000
Revision: 18-Jul-08
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