Not Recommended for New Designs: bq29400, bq29400A, bq29405 bq29400, bq29400A bq29401, bq29405 www.ti.com SLUS568C – JULY 2003 – REVISED SEPTEMBER 2005 VOLTAGE PROTECTION FOR 2-, 3-, OR 4-CELL Lion BATTERIES (2nd PROTECTION) FEATURES • • • • • • • FUNCTION 2-, 3-, or 4-Cell Secondary Protection Low Power Consumption ICC < 2 µA [VCELL(ALL) < V(PROTECT)] High Accuracy Over Sense Voltage: – bq29400: 4.35 V ±25 mV – bq29400A: 4.40 V ±25 mV – bq29401: 4.45 V ±25 mV – bq29405: 4.65 V ±25 mV Prefixed Protection Threshold Voltage Programmable Delay Time High Power Supply Ripple Rejection Stable During Pulse Charge Operation Each cell in a multiple cell pack is compared to an internal reference voltage. If one cell reaches an overvoltage condition, the protection sequence begins. The bq2940x device starts charging an external capacitor through the CD pin. When the CD pin voltage reaches 1.2 V, the OUT pin changes from a low level to a high level. PW PACKAGE (TOP VIEW) 1 2 3 4 VC1 VC2 VC3 GND APPLICATIONS • 8 7 6 5 OUT VDD CD VC4 DCT PACKAGE (TOP VIEW) 2nd Level Protection in Lion Battery Packs in – Notebook PCs – Portable Instrumentation – Medical and Test Equipment OUT VDD CD VC4 DESCRIPTION 1 8 2 7 3 6 VC1 VC2 VC3 4 5 GND The bq29400, bq29400A, bq29401, and bq29405 are BiCMOS secondary protection ICs for 2-, 3-, or 4-cell Lithium-Ion battery packs that incorporate a high-accuracy precision over voltage detection circuit. They include a programmable delay circuit for over voltage detection time. ORDERING INFORMATION TA –25°C to 85°C (1) V(PROTECT) PACKAGE MSSOP (DCT3) SYMBOL TSSOP (PW) (1) SYMBOL 4.35 V bq29400DCT3 CIQ bq29400PW 2400 4.40 V bq29400ADCT3 CIT Not Available - 4.45 V bq29401DCT3 CIR bq29401PW 2401 4.65 V bq29405DCT3 CIS Not Available - The bq29400, bq29400A, bq29401, and bq29405 are available taped and reeled. Add an R suffix to the device type (e.g., bq29400PWR) to order tape and reel version. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated Not Recommended for New Designs: bq29400, bq29400A, bq29405 bq29400, bq29400A bq29401, bq29405 www.ti.com SLUS568C – JULY 2003 – REVISED SEPTEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) (2) UNIT Supply voltage range (VDD) –0.3 V to 28 V Input voltage range (VC1, VC2, VC3, VC4) –0.3 V to 28 V (OUT) –0.3 V to 28 V Output voltage range (CD) –0.3 V to 28 V Continuous total power dissipation See Dissipation Rating Table Storage temperature range, Tstg –65°C to 150°C Lead temperature (soldering, 10 sec) (1) 300°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground of this device except the differential voltage of VC1-VC2, VC2-VC3, VC3-VC4 and VC4-GND. (2) PACKAGE DISSIPATION RATINGS PACKAGE TA = 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DCT 412 mW 3.3 mW/°C 264 mW 214 mW PW 525 mW 4.2 mW/°C 336 mW 273 mW RECOMMENDED OPERATING CONDITIONS MIN VDD Supply Voltage VC1, VC2, VC3, VC4 NOM MAX UNIT 4.0 25 V 0 VDD+0. 3 V VI Input voltage range td(CD) Delay time capacitance RIN Voltage-monitor filter resistance 100 1k Ω CIN Voltage-monitor filter capacitance 0.01 0.1 µF RVD Supply-voltage filter resistance CVD Supply-voltage filter capacitance TA Operating ambient temperature range 2 0.22 0 µF 1 0.1 –25 kΩ µF 85 °C Not Recommended for New Designs: bq29400, bq29400A, bq29405 www.ti.com bq29400, bq29400A bq29401, bq29405 SLUS568C – JULY 2003 – REVISED SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, TA = 25°C (unless otherwise noted) (1) PARAMETER V(OA) TEST CONDITION Over voltage detection accuracy MIN TA = –20°C to 85°C bq29400 25 50 4.40 bq29401 4.45 bq29405 4.65 Vhys Over voltage detection hysteresis (1) II Input current V2, V3 , VC4 input = VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = 3.5 V tD1 Over voltage detection delay time CD = 0.22 µF I(CD_dis) CD GND clamp current CD = 1 V ICC Supply current UNIT mV V 300 mV 0.3 1.0 1.5 5 12 2.0 µA S µA VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = 3.5 V (see Figure 1) 2.0 3.0 VC1 = VC2 = VC3 = VC4 = VC3–VC4 = VC4–GND = 2.3 V (see Figure 1) 1.5 2.5 µA VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = V(PROTECT)MAX, VDD = VC1, IOH = 0 mA 7 V VC1=VC2=VC3=VC4=V(PROTECT)MAX, VDD=4.3V, TA= 0°C to 70°C, IOH = – 40µA 1.5 –1 mA 5 µA IOH High-level output current OUT = 3V, VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = 4.7 V IOL Low-level output current OUT = 0.1 V VC1–VC2 = VC2–VC3 = VC3–VC4 = VC4–GND = 3.5 V (1) 35 4.35 Over voltage detection voltage (1) OUT pin drive voltage 25 bq2940A V(PROTECT) V(OUT) NOM MAX 2.0 2.5 V Levels of the over-voltage detection and the hysteresis can be adjusted. For assistance contact Texas Instruments sales representative. 1 VC1 OUT 8 IIN 2 VC2 VDD 7 IIN 3 VC3 CD 6 4 GND VC4 5 ICC V1 V2 V3 IIN V4 Figure 1. ICC, IIN Measurement (TSSOP Package) Terminal Functions TERMINAL DESCRIPTION MSOP (DTC) TSSOP (PW) NAME 8 1 VC1 Sense voltage input for most positive cell 7 2 VC2 Sense voltage input for second most positive cell 6 3 VC3 Sense voltage input for third most positive cell 5 4 GND Ground pin 4 5 VC4 Sense voltage input for least positive cell 3 Not Recommended for New Designs: bq29400, bq29400A, bq29405 bq29400, bq29400A bq29401, bq29405 www.ti.com SLUS568C – JULY 2003 – REVISED SEPTEMBER 2005 Terminal Functions (continued) TERMINAL DESCRIPTION MSOP (DTC) TSSOP (PW) NAME 3 6 CD 2 7 VDD Power supply 1 8 OUT Output An external capacitor is connected to determine the programmable delay time FUNCTIONAL BLOCK DIAGRAM RVD CVD VDD VC1 RIN ICD = 0.2 A (TYP) CIN RIN VC2 CIN VC3 OUT RIN CIN VC4 1.2V (TYP) RIN CIN GND CD OVERVOLTAGE PROTECTION When one of the cell voltages exceeds V(PROTECT), an internal current source begins to charge the capacitor, C(DELAY), connected to the CD pin. If the voltage at the CD pin, VCD, reaches 1.2 V, the OUT pin is activated and transitions high. An externally connected NCH FET is activiated and blows the external fuse in the positive battery rail, see Figure 1. If all cell voltages fall below V(PROTECT) before the voltage at pin CD reaches 1.2 V, the delay time does not run out. An internal switch clamps the CD pin to GND and discharges the capacitor, C(DELAY), and secures the full delay time for the next occurring overvoltage event. Once the pin OUT is activated, it transitions back from high to low after all battery cells reach V(PROTECT) - Vhys. DELAY TIME CALCULATION The delay time is calculated as follows: 4 Not Recommended for New Designs: bq29400, bq29400A, bq29405 bq29400, bq29400A bq29401, bq29405 www.ti.com SLUS568C – JULY 2003 – REVISED SEPTEMBER 2005 t d C 1.2 V C(DELAY) I (DELAY) CD td ICD 1.2 V Where I(CD) = CD current source = 0.2 µA V(PROTECT) V(PROTECT) - Vhys Cell Voltage (VCn - VC(n-1), VC4 - GND) 1.2 V CD tDELAY OUT td = (1.2 V x CDELAY)/ICD Figure 2. Timing for Overvoltage Sensing VCC vs VO(H) (IO(H) = 0mA) VCC vs VO(H) (IO(H) = -1mA 7 8 TA = 85C 6 TA = −25C 5 4 TA = 25C 3 2 1 0 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V 7 6 TA = −25C 5 TA = 85C 4 TA = 25C 3 2 1 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD − Supply Voltage − V VDD − Supply Voltage − V Figure 3. Figure 4. 5 Not Recommended for New Designs: bq29400, bq29400A, bq29405 bq29400, bq29400A bq29401, bq29405 www.ti.com SLUS568C – JULY 2003 – REVISED SEPTEMBER 2005 APPLICATION INFORMATION BATTERY CONNECTIONS The following diagrams show the TSSOP package device in different cell configurations. 1 VC1 OUT 8 1 VC1 OUT 8 2 VC2 VDD 7 2 VC2 VDD 7 3 VC3 CD 6 3 VC3 CD 6 4 GND VC4 5 4 GND VC4 5 CDELAY Figure 5. 4-Series Cell Configuration Figure 6. 3-Series Cell Configuration (Connect together VC1 and VC2) 1 VC1 OUT 8 2 VC2 VDD 7 3 VC3 CD 6 4 GND VC4 5 CDELAY Figure 7. 2-Series Cell Configuration CELL CONNECTIONS To prevent incorrect output activation the following connection sequences must be used. 4-Series Cell Configuration • VC1(=VDD) → VC2 → VC3 → VC4 → GND or • GND → VC4 → VC3 → VC2 → VC1(=VDD) 3-Series Cell Configuration • VC1(=VC2=VDD) → VC3 → VC4 → GND or • GND → VC4 → VC3 → VC1(=VC2=VDD) 2-Series Cell Configuration • VC1(=VC2=VC3=VDD) → VC4 → GND or • GND → VC4 → VC1(=VC2=VC3=VDD) 6 CDELAY PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) BQ29400ADCT3 NRND SM8 DCT 8 3000 Pb-Free (RoHS) CU SNBI Level-1-260C-UNLIM -25 to 85 CIT W BQ29400ADCT3E6 NRND SM8 DCT 8 3000 Pb-Free (RoHS) CU SNBI Level-1-260C-UNLIM -25 to 85 CIT W BQ29400ADCT3R OBSOLETE SM8 DCT 8 TBD Call TI Call TI -25 to 85 BQ29400DCT3 NRND SM8 DCT 8 3000 Pb-Free (RoHS) CU SNBI Level-1-260C-UNLIM CIQ BQ29400DCT3E6 NRND SM8 DCT 8 3000 Pb-Free (RoHS) CU SNBI Level-1-260C-UNLIM CIQ BQ29400PW NRND TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 29400 BQ29400PWR NRND TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 29400 BQ29401PW NRND TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -20 to 85 29401 BQ29405DCT3 NRND SM8 DCT 8 3000 Pb-Free (RoHS) CU SNBI Level-1-260C-UNLIM -25 to 85 CIS W BQ29405DCT3R NRND SM8 DCT 8 TBD Call TI Call TI -25 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2016 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device BQ29400PWR Package Package Pins Type Drawing TSSOP PW 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 7.0 B0 (mm) K0 (mm) P1 (mm) 3.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ29400PWR TSSOP PW 8 2000 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. 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